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Pulsed-laser annealing (PLA) was performed on a preformed Pt-doped Ni-rich silicide film (Ni2Si phase), and its microstructural and phase evolution were studied from submelting to melting condition by varying the laser power density (P). Vertically nonuniform compositional profile with an interfacial intermixing was observed under a solid state reaction regime (P

The importance of optimizing the millisecond annealing (MSA) temperature for Pt-doped NiSi ( ${\mathrm {Ni}}_{{1}-{x}}$ Pt x Si) contact formation was highlighted by implementing and characterizing the ${\mathrm {Ni}}_{{1}-{x}}$ Pt x Si films in the static random-access memory (SRAM) cells fabricated with a 28-nm design rule. MSA at 750 °C–900 °C effectively reduced the junction leakage current compared to that with the conventional rapid thermal annealing, because of its efficient suppression of Ni diffusion in the junction region. Moreover, with an increase in the MSA temperature, the beneficial effects of maintaining a low junction leakage, such as interface flattening and grain size increase, were observed. However, the increase in the MSA temperature deteriorated the statistical distribution of the standby leakage current of the SRAM cells by producing more encroachment and spiking defects; this was attributed to the build-up of a high initial film stress and large stress relaxation during the subsequent back-end processes.

Pt-doped NiSi‒NiSi2 thin films in a uniform lamellar structure with a periodicity on the scale of a few tens of nanometers were formed on Si(001) substrates using a continuous laser scanning process. When the Pt-doped NiSi film was melted at high temperatures and was supercooled at high solidification rates (a high scanning speed of over 200 mm/s), a NiSi‒NiSi2 lamellar structure evolved while interacting with the underlying Si substrate and following the classical eutectic solidification path. The lamellar spacing could be easily controlled by the laser scanning speed. In addition, the periodically formed, nearly single-crystalline NiSi and NiSi2 phases exhibited epitaxial relationships with each other and also with the Si(001) substrate. It is believed that this novel NiSi‒NiSi2 lamellar structure can be used as a template for application areas requiring an electrode with a line/space pattern on the scale of a few tens of nanometers that can be prepared without using costly photolithographic processes.

The objective of this study was to determine detailed microstructure of a Ni1–xPtxSi film formed via a melting/quenching process using high temperature laser annealing on a Si(001) substrate. The orthorhombic Ni1–xPtxSi film was found to be able to epitaxially grow with a crystallographic relationship of Ni1–xPtxSi[010]//Si[110], Ni1–xPtxSi(400)//Si(3 3 ¯ 1), and Ni1–xPtxSi (104)//Si(004). Volume expansion of the Ni1–xPtxSi film due to Pt incorporation was mainly accommodated by an increase in only one direction nearly parallel to the film surface (lattice parameter a). This was explained by the minimum coherent strain at the Ni1–xPtxSi (104)/Si(004) interface with an epitaxial growth tendency. Atomic-scale scanning transmission electron microscopy analyses revealed that the interface of Ni1–xPtxSi/Si had a repetitive atomic-step feature with energetically favorable Ni1–xPtxSi(004) terraces and (400) structural ledges that could increase the coherent area. By generating an array of misfit dislocations with an extra half plane of Ni1–xPtxSi(020), the elastic strain was further relieved.

3D Multi-stacking technology using Cu-Cu hybrid wafer bonding has been developed to achieve superior power, speed performances and higher density with minimized form factor. To realize multi-stacked device by using Wafer on wafer (WoW) bonding, both Face-to-Face (F2F) and Back-to-Face (B2F) interconnection can be required for more efficient and simple I/O pad design as well as lower resistance thanks to shorter interconnections. In this paper, we successfully demonstrated wafer-level multi-stacking structure by applying robust Cu-to-Cu bonding combined with Through-Si-Via (TSV) process. Three key subjects of comprehensive understanding about bonding interface, TSV and edge engineering to avoid defects and yield drop were essential to fulfill this research. Chemical-Mechanical-Polishing (CMP) and surface treatment had a huge impact on the Cu/dielectric hybrid bonding surface. In particular, planarization at the backside of the wafer is the key technology for robust follow up wafer bonding. For TSV formation, etch advancement performed to control the enhanced target compared to existing scheme. One more key subject is the edge engineering including integration considered edge treatment and effect by the process has been conducted to improve wafer bonding quality and reproducibility. Through the optimization of multi-stack oriented processes and integration, we confirmed extremely high yield of electrical connection including wafer edge for multiple layers. Many valuable applications can be introduced for sensors, memories, logic devices and even combinations of them by utilizing this novel processes.

This paper reports a 1280×960 DVS. A 4.95-μm pixel pitch is achieved with in-pixel Cu-Cu connection and the newly designed GIDL-suppression scheme. A sequential column selection scheme and a global event-holding function are implemented to minimize motion artifacts. The power consumption per pixel of 122 nW is 1.25× smaller and the maximum readout speed of 1.3 Geps is 4.33× faster than the previous state-of-the-art.

The low-temperature wafer bonding has been studied on two types of dielectric material (SiO, SiCN) as final bonding layers. It is important for the wafer bonding technology to obtain the higher interfacial energy between two bonding wafers, and oxygen and nitrogen (O 2 , N 2 ) plasma treatments have been studied to properly activate the dielectric film surfaces prior to a bonding process that includes chemical-mechanical polishing, hydration with DI water and heat treatment. The surface activation by the plasma treatments with DI hydration formed ~ 10nm thick SiO x layer on the SiCN films. It is found that a newly formed surface SiOx layer played a role as a bonding medium. The dielectric film surfaces were treated by plasma treatment, then characterized by analyzing chemical binding states in the surface SiO x layer. The characteristics of the new SiO x layers were found to be dependent on the plasma species and bulk dielectric films. The obtained properties of the surface layer have been co-related to the initial bonding energy of the bonded wafers as well as the final bonding energy with heat treatment. As a result, the N 2 plasma treatment to the dielectric films enhanced the initial bonding energy and SiCN-SiCN bonding wafers treated by the O 2 plasma have the better initial bonding energy rather than SiO-SiO bonding due to high hydrogen contents in the surface oxide films. In addition, the chemical analysis (XPS) has revealed the surface activity of the films from the results of the chemical binding states of Si. Basically, we focus on the initial bonding energy and it is crucial to ensure that the Cu pads facing each other comes into contact prior to the heat treatment that causes Cu diffusion across the opposite Cu pads.

Phase change memory (PCM) that is operated on resistance changes caused by joule heating has been suggested as the next-generation memory for scaling since its programming current scales linearly. We propose a U-shaped cell design to further reduce the reset current in PCM devices, which enables easier and more efficient scaling than conventional PCMs. Simulation studies of heat transfer demonstrated that our U-shaped design with a dashed heater has a higher thermal efficiency of 4.97 K/μA compared to 3.36 K/μA in a lance cell with a ring heater for the same storage node. The reset current can be better scaled proportionate to k 2.0 in which the exponent is higher than the lance cell of k 1.5 in non-isotropic scaling. This better scalability is attributed to the small programming volume of the U-shaped cell, which was verified by transmission electron microscopy analysis. Furthermore, the cyclic endurance of the U-shaped cell was enhanced by 1 order of magnitude compared to a lance cell and the thinner CGeSbTe films reduced the reset current further. Our results show that a U-shaped cell is a highly promising design to scale reset current in next-generation PCM devices.

High density 1Gb embedded STT-MRAM in 28nm FDSOI technology was successfully demonstrated. Based on the highly reliable and manufacturable eMRAM technology, high yield over 90% was achieved at the operating temperature from −40°c to 105°c with satisfying read, write function and 10 years retention at 105°c. These results are mainly attributed to the advanced process for better control of MTJ CD, highly manufacturable process window and robust circuit design for high density chip. MTJ properties can be systematically adjusted by tailoring the MTJ stack and MTJ module process. Improved endurance up to 1E10 cycles was achieved to broaden eMRAM applications to eDRAM replacement.

The scaling of semiconductor device below 10nm has faced the higher process difficulty and longer development periods. Three-dimensional integrated circuits (3D IC) using chip partitioning and wafer-to-wafer bonding have been acknowledged as the next generation semiconductor stacking technology because of smaller form factor, higher density integration and higher performance compared to same-node devices. Wafer-to-wafer bonding is widely used in stacked CMOS image sensor, that is, the bonding between pixel and logic wafer, and this technology has the potential to apply other semiconductor devices. Cu-Cu hybrid bonding has achieved by simultaneous wafer bonding of metal (Cu-Cu) and dielectric materials. In this study, it is investigated on the microstructure of Cu pad for Cu-Cu bonding after post-electroplating and post-bonding annealing process. The Cu grain size distribution and orientation are analyzed with different anneal temperature, which is applied on electroplated Cu, and with additional heat treatment as post-bonding process. The effect of pad size as well as the position within pattern array on Cu microstructure is also studied as the bonding pad is required smaller and smaller size for high density bonding. After Cu-Cu bonding, the cross-section analysis of bonding interface is carried out to see inter-diffusion of Cu atoms across the opposite Cu pad. Cu-Cu hybrid bonding is applied to test vehicle having the daisy chain of 2.4 million. The electrical resistance is measured before and after thermal stress and the Cu-Cu bonding interface is confirmed as robust structure.

As the cell size of phase change memory devices decreases to less than 100 nm, the dry etch used for cell patterning becomes extremely critical because of its impact on the properties of memory cells. HBr gas has been known as the etchant that can minimize surface etching damage to GeSbTe-based phase change materials. However, the findings reported herein show that the HBr etch of CGeSbTe (CGST) films causes voids after annealing at temperatures below 400 °C due to the vaporization of volatile bromides (GeBr4, SbBr2, and TeBr2) that form when bromine diffuses during the etch. In this investigation, we report on the use of NH3 etchants to suppress the formation of volatile compounds and thereby eliminate void formation in CGST materials. The properties of NH3 etchants were compared to those of HBr etchants as a function of both etch rate and profiles. The effects of void suppression as observed in transmission electron microscopy images of as-etched CGST film after annealing indicate that phase change memory devices etched using an NH3 exhibited enhanced set cycles that were over 108 superior to results of HBr etchants by 2 orders of magnitude.

We successfully demonstrated the manufacturability of 8Mb STT-MRAM embedded in 28nm FDSOI logic platform by achieving stable functionality and robust package level reliability. Read margin were greatly improved by increasing TMR value and also reducing distribution of cell resistance using advanced MTJ stack and patterning technology. Write margin was also increased by improving the efficiency using novel integration process. Its product reliability was confirmed in package level with passing HTOL 1000 hours tests, 106 endurance test, and retention test. For a wider application, we also demonstrated the feasibility of high density 128Mb STT-MRAM. Based on these results, we clearly verified the product manufacturability of embedded STT-MRAM.

We demonstrate, for the first time, 28-nm embedded STT-MRAM operating at full industrial temperature range (−40~125°C) with >1E+6 endurance and >10 year retention for high speed MCU/IoT application. Robust cell operation is also demonstrated after solder reflow (260°C, 90 second) and during external magnetic disturbance (550-Oe under writing). It is built on 28-nm FDSOI technology in modular format for IP reuse and has great potential to serve wide variety of applications such as IoT, and high performance MCU.

The trap distribution of a polysilicon (poly-Si) channel in a metal–oxide–semiconductor field effect transistor (MOSFET) was extracted successfully using a variable amplitude charge pumping method (VACP) and an energy band bending model. Compared to single crystal Si channels, the poly-Si channels exhibited a high density of bulk channel traps due to the presence of grain boundaries. The densities of the trap states existing in the poly-silicon channel with various grain sizes and channel thicknesses were extracted and compared. The grain size of poly-Si was found to have a stronger impact on the trap distribution than the channel thickness. After hot carrier stress, the trap density in the poly-silicon channel increases and the generated traps are located both at mid gap energy level and near the conduction band energy level.

In this paper, a physical mechanism for hot carrier injection (HCI) induced trap generation and degradation in bulk FinFETs is investigated and verified with both experiment and simulation evidence. HCI degradation is mainly caused by interface states generated by drain avalanche hot carrier injection. From this model, impact ionization intensity, location and trapping immunity are proposed as key parameters to modulate HCI degradation. HCI reliability in I/O FinFETs is severely degraded with respect to planar FETs because of the enhanced capability of the gate to control the channel potential profiles increasing the intensity of the lateral E-field in comparison with planar devices. Based on this FinFET HCI mechanism, we have successfully optimized source/drain junction process to achieve reliable HCI characteristics for 14nm and 10nm FinFET devices.

A two-step annealing method with a low thermal budget is proposed for advanced surface-energy-driven secondary grain growth of Ge films without any agglomeration. In the first-step annealing, the normal grain growth from as-deposited poly-crystalline Ge films was induced to make the grain size equivalent to the film thickness at 800 °C. After the subsequent second-step annealing at 900 °C, the much larger secondary grains were obtained than those by single-step annealing at 900 °C. The possible explanation regarding the final microstructure of the two-step annealed film is proposed. The two-step annealing was able to form the microstructure of Ge thin film with very large-grained matrix without any agglomeration, resulting in higher carrier mobility. Therefore, the proposed two-step annealing is believed to be a promising process applicable for channel formation processes in the next-generation Ge thin film transistors for 3D integrated circuits and vertical NAND flash memories.

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of 300 cm²/Vs, which guarantees “device quality”. In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-theart memory technology.

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (E v ) lowers the E ox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

Three-dimensional stacked memory has attracted much attention due to its advantages such as high-speed operation, low-power consumption, and high-level integration. Many researchers have reported various novel approaches to achieve three dimensional device integration, including wafer bonding, epitaxial lateral overgrowth (ELO), zone melting recrystallization (ZMR), and lateral-solid phase epitaxy (L-SPE). These methods have some limitations, in terms of the requirement of stacked memory process which include simple integration process, low thermal budget due to the performance degradation of underlying devices and single crystalline quality on oxide. In this work, we suggest a laser-induced epitaxial growth (LEG) process that utilizes a single crystalline seed grown by selective epitaxial growth (SEG) process. This seed layer was formed in patterned contact holes linking the substrate Si and the stacked layer. A raised seed could prevent the degradation of electrical properties of underlying devices. An excimer laser was then used as a light source of the epitaxial growth via recrystallization to melt the deposited amorphous Si films both on oxide layer and seed contact during several nano-seconds.

In this study, SiBN films were prepared by plasma assisted atomic layer deposition (PAALD) using dichlorosilane, boron trichloride and ammonia as source gases. In this material system, the reaction control of boron, silicon and nitrogen is a key issue because nitrogen reacts more readily with boron than with silicon. On the other hand, ammonia radicals created by remote plasma during PAALD enhance the reaction between silicon and nitrogen. Therefore, PAALD enables an enhanced controllability of silicon and boron contents. SiBN films with dielectric constant of 4.45 to 5.47 were applied to buried- contact (BC) spacer instead of SiN films in 70 nm DRAM device, and 12 - 24% reduction of bit-line loading capacitance (CBL) was obtained. Low-k SiBN films using PAALD are promising materials for insulating interlayer such as Si3N4 spacer for future sub-70 nm DRAM devices.

In this paper, we investigate the electrical characteristics of SiO2/ZrO2 hybrid tunnel oxide in metal–Al2O3–SiO2–Si3N4–SiO2–silicon (MAONOS) structure in an effort to improve program and erase speed as well as retention characteristics. Inserting ZrO2 into the conventional MAONOS structure increased the programmed V th variation to 6.8 V, and increased the erased V th variation to −3.7 V at 17 MV/cm. The results can be understood in terms of reducing the Fowler–Nordheim (F/N) tunneling barrier due to high-k ZrO2 in the tunneling oxide. In addition, Zr diffusion in SiO2 caused the formation of Zr x Si1− x O2 at the interface region, which reduced the energy band gap of SiO2. The retention property of the hybrid tunnel oxide varied depending on the thickness of SiO2. For thin SiO2 less than 30 A, the retention properties of the tunneling oxides were poor compared with those of the SiO2 only tunneling oxides. However, the hybrid tunneling oxides with SiO2 thickness thicker than 40 A yielded improved retention behavior compared with those of the SiO2-only tunneling oxides. The detailed analysis in charge density of ZrO2 was carried out by ISPP test. The obtained charge density was quite small compared to that of the total charge density, which indicates that the inserted ZrO2 layer serves as a tunneling material rather than charge storage dielectric.

Surface roughening and defect formation of (100) Si at low temperatures during electron cyclotron resonance hydrogen plasma cleaning are studied in an ultrahigh vacuum environment, and a new model is proposed to explain their mechanisms. The effect of process parameters on surface roughness is quantitatively analyzed by atomic force microscopy and reflection high energy electron diffraction. Crystalline defect morphology is studied by transmission electron microscopy to understand its role in surface roughness. Surface roughness is strongly related to {111} platelet defects at the Si subsurface region and subsequent preferential etching at positions where {111} platelet defects intersect the Si surface. The formation of {111} platelet defects is determined by the subsurface hydrogen concentration, which is determined by incident hydrogen flux and substrate temperature. The preferential nucleation of etching reactions on the {111} platelet may be explained by the classical nucleation theory. Hydrogen ion flux and substrate temperature can be controlled successfully to tailor {111} platelet defect formation and hence, surface roughness.

The defect formation in (100) Si at low temperatures during electron cyclotron resonance hydrogen plasma treatment has been studied. The temperature effect on crystalline defect morphology is studied by transmission electron microscopy and high resolution transmission electron microscopy. A high density of hydrogen-stabilized {111} platelets is observed at 240 °C, whereas a large number of amorphous {100} platelets is observed at 385 °C. The formation of amorphous {100} platelets without {111} platelets at 385 °C is reported. The amorphous {100} platelet at 385 °C results from the precipitation of oxygen promoted by hydrogen-enhanced oxygen diffusion. The low-temperature photoluminescence study and the spreading resistance profiles for the hydrogenated Si support the proposed mechanism of the amorphous {100} platelet.

We report on the growth of in situ boron doped Si and Si1−xGex epitaxial layers at 510 °C by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition. Boron concentration increases with B2H6 partial pressure. The boron concentration decreases as microwave power increases in Si epilayers and as Ge fraction increases in Si1−xGex epilayers. Enhanced ion bombardment at these conditions promotes the desorption of boron hydride in the growth surface. No growth rate change is observed in the Si epilayer with B2H6 partial pressure. However, a significant growth rate decrease is observed for the Si1−xGex epilayer with B2H6 partial pressure.

The technology of increasing Internal Vcc without using memory tester is used to enhance the photon emission and the failure range is defined in detail by nano probing. With these methods, we found out that the leakage current was caused by dislocations of STI arranged in a row.

Thin films of LiMn[sub 2]O[sub 4] spinel were fabricated by RF magnetron sputtering. The as-deposited films were amorphous but could be crystallized into a spinel structure by rapid thermal annealing in an oxygen atmosphere. The electrochemical performance of 2000 [angstrom] thick LiMn[sub 2]O[sub 4] thin-film cathodes were tested in a LiMn[sub 2]O[sub 4]/1M LiClO[sub 4] in PC + DME/Li cell. LiMn[sub 2]O[sub 4] spinel films prepared at 750 C showed good intercalation kinetics and very promising cycling behavior. Room temperature cycling of these films had capacities of about 50 [mu]Ah/cm[sup 2]-[mu]m at 200 [mu]A/cm[sup 2] and maintained more than 98% of their original capacity after more than 1000 cycles.

We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 A – 185 A. The TFT charge transfer characteristics such as ON current and effective mobility are dominated not by the thickness itself but by the grain size of poly-Si channel. When the poly-Si channel thickness is decreased with the same grain size, the sub-threshold TFT characteristics are improved without degradation of ON current and reliability properties. These results give us appropriate criteria to establish an excellent poly-Si channel in vertical NAND flash memory.

We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO 2 /a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can be modified, which made it possible to achieve tunnel barrier engineering without employing high-k material. By reducing the erase voltage, the reliabilities of NAND flash memory was improved.

The improvement of device performances has been achieved successfully through OAO IPD EOT scaling, which shows that OAO IPD is applicable to sub-40nm devices which require aggressive scaling of IPD EOT. Charge loss of OAO IPD at high temperature is explained by thermionic emission of alumina traps. Trap profiles of alumina were obtained by monitoring Vth shift above 100°C. OAO IPD shows good data retention at room temperature, which is consistent with trap profiles.

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.

Abnormal gate oxide thickening at active edge (GOTAE) has been investigated in dynamic random access memories (DRAMs) with SiN-lineared shallow trench isolation (STI). 1% of gaseous HCl, which is added during dry oxidation, plays a major role in inducing abnormal GOTAE by the mechanical interaction with thin SiN layers in STI. Other structural parameters, such as the thickness of trench sidewall oxide, liner SiN and sacrificial oxide, are believed to influence the amount of oxide thickening. In order to avoid abnormal GOTAE, wet oxidation is introduced and shown to be effective in suppressing it. Electrical properties, which are susceptible to the extent of GOTAE, are also presented in this paper.

Extended abstract of a paper presented at Microscopy and Microanalysis 2012 in Phoenix, Arizona, USA, July 29 – August 2, 2012.

Novel Al/sub 2/O/sub 3/ process was developed in order to extend the applicability of reliable SIS and MIS Al/sub 2/O/sub 3/ capacitors as well as Al/sub 2/O/sub 3/ EBL for a MIM capacitor. By applying ALD process utilizing a smart growth mechanism, electrical and interfacial properties of Al/sub 2/O/sub 3/ film were surprisingly improved. The SIS and MIS Al/sub 2/O/sub 3/ capacitor technologies with ultra-low thermal budget were confirmed by producing fully working 1 Gbit DRAM with design rule of 0.15 and 0.13 /spl mu/m, respectively. Moreover, Al/sub 2/O/sub 3/ EBL for a MIM capacitor was successfully used to preserve the excellent dielectric characteristics for the application of DRAM with design-rule of 0.10 /spl mu/m, and beyond.

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.

Dislocation-free Si1−xGex epilayers are successfully grown on (100) silicon at 440°C by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition (UHV-ECRCVD). The effects of process parameters on the crystallinity of Si1−xGex epitaxial layers were studied. As the GeH4 flow rate increases and consequently Ge fraction increases above 20%, Si1−xGex epilayers become damaged heavily by ions. When Ge fraction is larger than 20%, process parameters like total pressure need to be adjusted to reduce the ion flux for high quality Sil−xGex. Growth rate of Si1−xGex epitaxial layers increases at 440°C with Ge content in the film. It is presumed that the hydrogen desorption from the surface is the rate-limiting step, however, the enhancement in growth rate is comparatively suppressed and delayed.

not Available.

HfO 2 films were deposited via Hf(OtBu) 4 precursor and ozone oxidant using atomic layer deposition (ALD) atop Al 2 O 3 . We report the impact of annealing conditions on the physical and electrical properties of a HfO 2 on Al 2 O 3 /SiN/Si substrate using medium-energy ion scattering spectroscopy, high-resolution transmission electron microscopy, thermal desorption spectra, and electrical measurements. Annealing temperatures influence the microstructure and impurity levels of Hf(OtBu) 4 HfO 2 /Al 2 O 3 /SiN films. The leakage currents of Al 2 O 3 -HfO 2 bilayer were decreased with the increase of annealing temperature and the structures of the bilayer did not break until 850°C. This change was closely related to the reduction of carbon and organic contamination during annealing. However, annealing at 950°C drastically degraded electrical properties due to the intermixing of the HfO 2 -Al 2 O 3 bilayer structure.

Low-temperature electron cyclotron resonance hydrogen plasma cleaning was developed for low-temperature epitaxial growth of Si by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition on oxide-patterned wafers. Defect-free undoped Si epitaxial layers could be obtained by optimizing the hydrogen ion flux and cleaning time, however, in the case of boron-doped Si epitaxial growth, Si epilayers had defect zones away from the bird’s beak along the window edges and a defect-free zone at the center of the window. Cross section transmission electron microscopy and energy dispersive spectroscopy results suggest that the defect zone formation is closely related with local oxygen contamination. Possible origins of the local oxygen contamination are discussed.

Boron-doped silicon epitaxial layers were grown by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition at 440–510 °C. Reflection high-energy electron diffraction and transmission electron microscopy (TEM) were used to study the effect of boron doping on the crystalline quality of silicon epitaxial layers. At growth conditions where undoped defect-free Si epitaxial layers were successfully obtained at 440 °C, in situ boron-doped epitaxial layers were replete with twins. However, at conditions with increased ion energy flux and at a higher temperature, 470 °C, no twins were observed. TEM analysis revealed the presence of an amorphous phase in the twinned epitaxial layers. It is believed that the amorphous phase formation, presumably from the reaction between B and O during the doping process, appeared to hinder the growth of the epitaxial layer, leading to degradation of the Si crystalline quality. Defect-free boron-doped Si epitaxial layers were able to be obtained by suppressing the amorphous phase formation at conditions with increased growth temperature and higher ion energy flux.Boron-doped silicon epitaxial layers were grown by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition at 440–510 °C. Reflection high-energy electron diffraction and transmission electron microscopy (TEM) were used to study the effect of boron doping on the crystalline quality of silicon epitaxial layers. At growth conditions where undoped defect-free Si epitaxial layers were successfully obtained at 440 °C, in situ boron-doped epitaxial layers were replete with twins. However, at conditions with increased ion energy flux and at a higher temperature, 470 °C, no twins were observed. TEM analysis revealed the presence of an amorphous phase in the twinned epitaxial layers. It is believed that the amorphous phase formation, presumably from the reaction between B and O during the doping process, appeared to hinder the growth of the epitaxial layer, leading to degradation of the Si crystalline quality. Defect-free boron-doped Si epitaxial layers were able to be obtained by suppressing the am...

Low‐temperature, defect‐free, in situ cleaning of silicon prior to homoepitaxy is successfully developed by an electron cyclotron resonance hydrogen plasma treatment in an ultrahigh vacuum chamber. The plasma potential distribution was measured by a Langmuir probe method to understand the effect of the substrate dc bias during hydrogen plasma cleaning. It changes from downhill to uphill distribution as the dc bias changes from a negative to a positive value, which leads to a decrease in the ion number density arriving at the substrate and results in the complete suppression of the defect formation in the Si substrate. In situ hydrogen plasma cleaned Si wafer always resulted in higher quality epilayers than ones cleaned only by so‐called hydrogen passivation after the HF dip. We found that there is a critical dose of the hydrogen ions during in situ plasma cleaning beyond which crystalline defects are observed in the Si substrate, subsequently leading to the poor crystallinity of the epilayers. The dose of the hydrogen ions during plasma cleaning can be effectively controlled by the substrate dc bias, the microwave power, the magnet current, and the cleaning time.