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We have demonstrated, for the first time, a surrounding gate vertical-channel field-effect transistor (FET) with a gate length of 40 nm by introducing back-end-of-line (BEOL) process-compatible oxide semiconductor (OS) In-Al-Zn-O as a channel material. Fabricated FETs exhibited high scalability by excellent thermal stability (~420 °C) compared to conventional In-Ga-Zn-O-channel FETs, with high-mobility (12.7 cm2/V.s) characteristics. Furthermore, the vertical-channel FET also exhibited excellent reliability and stable operation without floating body effect. Endurance of over 1011 cycles was also demonstrated. Our work opens a pathway to realization of high-performance BEOL transistor for 3-D-large-scale integration (LSI) applications.

We propose material design guideline of oxide semiconductor field-effect transistor (OS-FET) based on first-principles calculation, and experimentally demonstrate excellent FET characteristics for the first time. Fluorine-doped In-Ga-Zn-O (IGZO) channel OS-FET exhibits both high thermal stability (>400°C) and high on-current at optimum F doping concentration which are required for co-integration with Si-CMOS as BEOL transistor. Our calculation revealed that high thermal stability comes from the release of overstress in IGZO by substitution of O by F. On the other hand, overdose of F decreases on-current by forming electron traps of metal-metal bonds. Considering these two different mechanisms behind, we successfully propose a breakthrough concept to improve thermal stability of OS-FET without degradation of on-current. Our results pave a new way for realizing high-performance BEOL transistors for 3D-LSI application.

We demonstrate a high-mobility and H2-anneal tolerant InGaSiO/InGaZnO/InGaSiO double heterochannel (DH) thin film transistor (TFT) for 3-D integration with Si CMOS-LSI applications. A novel oxide semiconductor material, InGaSiO (Si/In ratio > 0.47) was found to exhibit semiconductor property even after H2 annealing at 380 °C, whereas a conventional InGaZnO layer changed into a metallic one. Moreover, the DH channel TFT was operated in an enhancement mode and achieved a high mobility of 30 cm2/Vs after the H2 annealing. The proposed DH channel TFT has a potential as a high-performance back end of line transistor with Si-CMOS process compatibility.

In this study, ultrasensitive pH sensing is achieved by charge-coupling with an amorphous(a)-InGaZnO-based thin film transistor (TFT) for use as an ultrasensitive biosensor. To enhance the detection sensitivity using the charge-coupling circuit, an extended-gate a-InGaZnO-based TFT sensor is employed, in which the size of the extended electrode with an oxide film is fixed but the channel size is controllable. The pH sensitivity was enhanced to 313 mV/pH at 25°C, above the ideal potential limit, by decreasing the channel size of the charge-coupling extended-gate TFT, although an insulated-gate TFT showed a standard pH response near the ideal Nernstian potential (59.1 mV/pH at 25°C) because of the non-charge-coupling gate structure. This is because ionic charges at an extended electrode with an oxide film, which are unrelated to the Nernstian interfacial potential, affect the channel conductivity of the TFT, in addition to the Nernstian interfacial potential. A platform based on the charge-coupling extended-gate a-InGaZnO-based TFT is suitable for an ultrasensitive and flexible biosensing system to monitor not only pH but also biomarkers such as glucose in sweat on skin in the future.

We have demonstrated and experimentally verified the advantages of In-Zn-O (InZnO) channel compared with In-Ga-Zn-O (InGaZnO) channel for high performance oxide semiconductor channel field effect transistor (FET) with both ultralow off-state leakage current and high on-current. Compared with InGaZnO FET, high mobility (>30 cm2/Vs) and reduction of source/drain (S/D) parasitic resistance by 75% were achieved by InZnO FET. Analysis of a Schottky barrier height at S/D contact and a band offset between oxide semiconductor channel and gate insulator SiO2 revealed that the reduction of S/D parasitic resistance originated from a lowering of conduction band minimum by InZnO channel. Moreover, ultralow (

An n +-Ge layer with a carrier density of 7 x 1019 cm-3 (physical dopant concentration = 1 x 1020 cm-3) was successfully grown by choosing an appropriate growth condition with a conventional low-pressure CVD technique. We found that a high activation rate of the n-type dopants can be realized at some limited growth pressure range. Ti contacts on the P-doped n +-Ge epi-layers exhibited ohmic properties in contrast to those on P ion-implanted Ge layers of almost the same dopant concentration. Low sheet resistance of 33 Ω/sq and low specific contact resistivity of 1.2 x 10−6 Ωcm2 were obtained for the 65-nm-thick epi-Ge layers as a result of the high activation rate. By applying the n +-Ge layers to Source/Drain region of GeOI-nMISFETs (Lch=60nm) to reduce the parasitic resistances, a high drive current of 300 mA/mm was obtained at Vd=1V, Vg-Vth=1.5V.

Background The class Diphyllatea belongs to a group of enigmatic unicellular eukaryotes that play a key role in reconstructing the morphological innovation and diversification of early eukaryotic evolution. Despite its evolutionary significance, very little is known about the phylogeny and species diversity of Diphyllatea. Only three species have described morphology, being taxonomically divided by flagella number, two or four, and cell size. Currently, one 18S rRNA Diphyllatea sequence is available, with environmental sequencing surveys reporting only a single partial sequence from a Diphyllatea-like organism. Accordingly, geographical distribution of Diphyllatea based on molecular data is limited, despite morphological data suggesting the class has a global distribution. We here present a first attempt to understand species distribution, diversity and higher order structure of Diphyllatea. Results We cultured 11 new strains, characterised these morphologically and amplified their rRNA for a combined 18S–28S rRNA phylogeny. We sampled environmental DNA from multiple sites and designed new Diphyllatea-specific PCR primers for long-read PacBio RSII technology. Near full-length 18S rRNA sequences from environmental DNA, in addition to supplementary Diphyllatea sequence data mined from public databases, resolved the phylogeny into three deeply branching and distinct clades (Diphy I – III). Of these, the Diphy III clade is entirely novel, and in congruence with Diphy II, composed of species morphologically consistent with the earlier described Collodictyon triciliatum. The phylogenetic split between the Diphy I and Diphy II + III clades corresponds with a morphological division of Diphyllatea into bi- and quadriflagellate cell forms. Conclusions This altered flagella composition must have occurred early in the diversification of Diphyllatea and may represent one of the earliest known morphological transitions among eukaryotes. Further, the substantial increase in molecular data presented here confirms Diphyllatea has a global distribution, seemingly restricted to freshwater habitats. Altogether, the results reveal the advantage of combining a group-specific PCR approach and long-read high-throughput amplicon sequencing in surveying enigmatic eukaryote lineages. Lastly, our study shows the capacity of PacBio RS when targeting a protist class for increasing phylogenetic resolution. Electronic supplementary material The online version of this article (10.1186/s12862-018-1224-z) contains supplementary material, which is available to authorized users.

Suppressing the channel shortening effect is a key to realize a short channel InGaZnO Thin-Film-Transistor (TFT). We investigated the lateral diffusion length L_{ext}} of low-resistivity region formed in InGaZnO quantitatively. The TFTs with In-Sn-O (ITO) electrode showed no change of L_{ext}}, even though the TFTs with Ti electrode showed the extension of L_{ext}} after high temperature annealing. We revealed that the suppression effect of channel shortening effect of ITO electrode, by using both of electrical characterization and scanning spreading resistance microscopy (SSRM) observation.

We proposed a comprehensive parameter extraction method for short channel amorphous InGaZnO (α-InGaZnO) thin-film transistors (TFTs) on the basis of measurement data and TCAD simulations. Single parameter set were successfully extracted for channel length down to 500nm by using RPI α-Si TFT model with channel length modulation modeling. It makes possible to more accurate and scalable circuit performance characterization, since the extracted parameters correspond to the physical behavior of α-InGaZnO TFTs.

This paper presents a novel charge-based neuromorphic cell architecture composed of 1-capacitor and 1-transistor using extremely low off leakage (

Germanium is recognized as new channel material to be introduced in near future CMOS technologies. The advantages are the high hole mobility, the high p-type dopant activation and the low contact resistivity, whereas the smaller band gap results in higher off state current than Si devices. Therefore, Ge-MOSFETs are considered to be most promising to use as a pMOS counterpart of III-V nMOSFETs for high-performance CMOS devices. In order to suppress the off leakage current, Ge-on-insulator (GeOI) substrates may be preferable than bulk substrates. On the other hand, the low thermal budget of the fabrication processes can provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs instead of a TSV technology. Poly-Ge CMOS devices on insulating layers may be one of solutions for the 3D-LSIs. In this paper, electrical properties and processes of high performance strained Ge nanowire pMOSFETs and poly-Ge trigate pFETs both on buried oxide (SiO2) layers, which are dedicated for the former and the latter applications, respectively, are presented. The Ge nanowire devices were formed by a two-step Ge condensation technique for the channels and a self-aligned NiGe process for the source and drain [1]. A compressive strain of around 4% along the channel direction of was observed after the condensation process, suggesting that no relaxation of the misfit strain between Si and Ge was occurred. A significantly high-hole mobility of 1922 cm2/Vs has been achieved thanks to the high strain and the good interfacial quality between the gate insulator and the Ge channel. Ion/Ioff over 105 has also been attained for the Ge nanowire pMOSFET with a gate length (Lg ) of 45 nm. Poly-Ge junction-less (JL) pFETs with a Lg down to 40 nm were formed on a SiO2 layer on a Si substrate [2]. The poly-Ge channel was naturally p-type with a hole concentration around 5x1018 cm-3 presumably due to the crystalline defects. No additional doping has been done. A high Ion/Ioff of around 105 was observed for narrow fin (7 nm) devices, although wider devices (>11 nm) exhibited degraded cut-off characteristics. We also found that the current drivability was drastically improved by using a flash lamp annealing (FLA) method due to the high hole mobility in the poly-Ge channel. A drain current value of 280 μA/μm was achieved at Vd =-1 V for the Lg =80 nm device [3], which is comparable with that of a mono-crystalline Si-pMOSFET of 130-nm technology node. In summary, two types of GeOI pMOSFETs for near-future high-performance logic CMOS-ICs and low-cost stackable applications were demonstrated. In both types of devices, the GeOI platform and non-planar gate configurations are key technologies to achieve sufficiently high Ion/Ioff values, which is one of major concerns to implement Ge devices into markets. Acknowledgement This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP). References [1] K. Ikeda et al., Symp. VLSI Tech., (2013), T30 [2] Y. Kamata et al., Symp. VLSI Tech., (2013), T94 [3] K. Usuda, ISDRS 2013 WP3-04

Fabrication of bonded Germanium on insulator (GeOI) substrates with thin Al 2 O 3 /SiO 2 buried oxide layers was demonstrated for the first time. Thin Al 2 O 3 layers grown by an atomic-layer deposition method, which have hydroxyl groups on their surfaces, were inserted to Ge/SiO 2 interfaces to strengthen the adhesion between them. The interface bonded in the atmosphere at room temperature without post-anneal processes is flat and exhibits no additional interface. After the wafer bonding, thick GeOI layers were thinned by mechanical polishing, chemical mechanical polishing and O 3 water etching. The flatness of the surface is equivalent to that of commercially available Ge substrates. The interface state density ( D it ) of the Ge/Al 2 O 3 interface is estimated with low-temperature conductance technique and the D it of as low as 3.9 × 10 11 eV −1 cm −2 at the interface is obtained. This value is almost one order of magnitude lower than previously reported D it of Ge/SiO 2 interfaces. These results suggest that negligible negative impact on carrier mobility and sub-threshold characteristics is expected for the back-side interface in the GeOI substrate with thin Al 2 O 3 /SiO 2 BOX layers.

Tensile strain of over 1% in Ge stripes sandwiched between a pair of SiGe source-drain stressors was demonstrated. The Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET)-like structures were fabricated on a (001)-Ge substrate having SiO2 dummy-gate stripes with widths down to 26 nm. Recess-regions adjacent to the dummy-gate stripes were formed by an anisotropic wet etching technique. A damage-free and well-controlled anisotropic wet etching process is developed in order to avoid plasma-induced damage during a conventional Reactive-ion Etching process. The SiGe stressors were epitaxially grown on the recesses to simulate strained Ge n-channel Metal–Insulator–Semiconductor Field-Effect Transistors (MISFETs) having high electron mobility. A micro-Raman spectroscopy measurement revealed tensile strain in the narrow Ge regions which became higher for narrower regions. Tensile strain of up to 1.2% was evaluated from the measurement under an assumption of uniaxial strain configuration. These results strongly suggest that higher electron mobility than the upper limit for a Si-MOSFET is obtainable in short-channel strained Ge-nMISFETs with the embedded SiGe stressors.

Firstly, advantages and fabrication processes for strained SiGe fin- and wire-pMOSFETs are summarized. It is shown that strained SiGe-on-insulator channels formed by the Ge condensation process is effective to keep strain in the channel and hence to boost the current drivability of pMOSFETs. Secondly, our recent progress on a new gate-stack technology using SrGex interlayer and fabrication process of narrow Ge-fin structures using anisotropic wet etching were demonstrated for all-Ge CMOS applications. It is shown that these processes are beneficial for realizing non-planar Ge-CMOS devices in future technology nodes.

As a template for scaled Ge-FinFETs, anisotropic wet etching was applied to obtain narrow Ge-fins with smooth sidewalls. It was found that Ge (110) facets were formed with a higher pH APM etchant. 100nm-width Ge-fin structures were slimmed to approximately 30nm by the APM etching. Moreover, LWF (Line Width Fluctuation) values of the Ge-fin were reduced by the emergence of (110) facets due to the lower etching rate on {110} surfaces. These results suggest that the wet etching process is applicable to future high-performance Ge-FinFETs.

We evaluated profiles of B, P, As, and Si implanted in Ge substrates by secondary ion mass spectrometry, analyzed the profile data using a quasi-crystal Lindhard-Scharff-Schiott (QCLSS) theory, tuned its parameters, and established a corresponding database based on a tail function. We also predicted Ge, Sb, Ga, In, and Xe profiles in Ge substrates by using the QCLSS theory and also established a corresponding database. We further evaluated the thickness of the amorphous layers formed by ion implantation by transmission electron microscopy and reproduced it in a model by tuning a corresponding parameter of the through dose. Using a profile parameter database and this through dose, we can predict ion implantation profiles and related amorphous layer thicknesses in Ge substrates over a wide range of ion implantation conditions.

We have fabricated NiGe/Ge diodes and Ge pMISFETs with the NiGe S/D, and studied the electrical characteristics in detail. The NiGe/n-Ge Schottcky S/D is shown to be suitable for Ge pMISFETs. The high performance Ge pMISFETs with sub-100nm gate length has been demonstrated. The dependencies of the inversion layer hole mobility of Ge on the impurity concentration and temperature, and the characteristics of short channel pMISFETs were experimentally examined.

We evaluated the dependence of ion-implanted B concentration profiles on dose in crystalline Ge substrates (c-Ge) and evaluated B concentration profiles in amorphous Ge (a-Ge) by a Monte Carlo simulation. We showed that channeling is as significant in c-Ge as it is in crystalline Si (c-Si). We found that the concentration profiles in a-Ge and c-Ge can be fitted using a Pearson IV function and a tail function that has additional parameters for expressing the channeling tail, and we established a corresponding database, which enables us to generate ion-implanted profiles at any dose and energy up to the maximum evaluated energy of 80 keV.

We have fabricated high-performance self-aligned top-gate InGaZnO TFTs with novel silicon-like source and drain (S/D) parasitic resistance (R SD ) reduction processes. Ar ion implantation (Ar I/I) formed S/D extension layers and reduced R SD by inducing high-density carriers. First demonstration of self-aligned S/D metallization processes on InGaZnO surface (In-Ti alloy formation), just like silicidation, realized further R SD reduction. In addition, threshold voltage (V th ) controllability by back-gate bias was enhanced by adopting thin InGaZnO body and BOX. Successful applications of these booster technologies developed for Si LSIs enable us to fabricate high-performance top-gate scaled InGaZnO TFT in 3D LSI.

Effects of thermal treatment under various ambient conditions for Ge(0?0?1) substrates on MIS interface properties have been investigated. Ge?MIS capacitors with Al gates have been fabricated by depositing SiO2 layers on thermally treated Ge surfaces. We characterized the interface structures by transmission electron microscopy, x-ray photoelectron spectroscopy and C?V, G?F (conductance?frequency) measurements. It is found that the ambient conditions significantly change the MIS interface structures and, thus, the interface trap density. As a result, the thermal treatment under O2 ambient condition is very effective at decreasing the interface trap density and the slow trap density as well. This decrease in the interface traps is attributable to the reduction in dangling bonds by forming stoichiometric GeO2 at the MIS interfaces.

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100 nm technology nodes.

Ge-on-insulator (GOI) layer by the Ge-condensation technique is characterized from the viewpoint of the carrier transport. We fabricate GOI channel metal-oxide-semiconductor field-effect transistors (MOSFETs) featuring ultra-low Schottky barrier metal source/drain for holes using Pt germanide where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. P-type and N-type channel MOSFET operations in the accumulation and inversion mode, respectively, are demonstrated successfully, according to Schottky barrier heights for each carrier. Hall measurement for the GOI layers indicates the existence of relatively high carrier density of holes, 1.3 × 10 17 cm − 3 , which is not attributable to doped impurities.

We have proposed Metal Source/Drain MOSFETs (MSD-MOSFETs) with Ge-on-Insulator (GOI) channels using germanides as source/drain metal material. Here the characterization of Schottky barrier hieght (SBH) at the germanide/Ge interfaces is a key issue for a Ge channel MSD-MOSFET. However, there are few published reports on the subject. In this paper, we present the results of the characterization of platinum germanide/Ge interfaces. SBHs of platinum germanide/n- and p-Ge(100) junctions were evaluated to examine the applicability of platinum germanide to MSD-MOSFETs. The SBH for platinum germanide/p-Ge(100) was found to be as low as 0.1 eV over a wide range of anneal temperatures. As a result, we conclude that platinum germanide is a promising S/D material for Ge channel MSD-MOSFETs.

Thin-film transistors (TFTs) with Schottky source/drain (S/D) structures were fabricated using NiSi and laser-annealed polycrystalline silicon (poly-Si) as Schottky barrier metals and active layers, respectively. The whole fabrication process was performed at low temperatures (

We fabricated sub-50-nm-gate i-AlGaN/GaN high electron mobility transistors (HEMTs) on sapphire and measured their DC and RF characteristics at room temperature. The fabricated HEMTs exhibited true device operation and good pinch-off characteristics down to a gate length Lg of 25 nm. For the HEMTs with a source–drain spacing Lsd of 2 μm, we obtained the Lg dependence of the cutoff frequency fT under a drain–source voltage Vds of 3 V. The peak fT was measured to be 102 GHz at Lg = 35 nm. At Lg = 25 nm, fT started to decrease due to the short-channel effect. The highest fT of 110 GHz was obtained by reducing Lsd from 2 to 1.5 μm and by increasing Vds from 3 to 4 V. (© 2003 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at V dd as low as 0.37 V with the help of adaptive back gate bias, V BG control.

n + -Ge layers with a dopant concentration of 1 × 10 20 cm -3 and its dopant activation rate as high as 0.7 were obtained by optimizing the growth conditions in LP-CVD. Ti/n + -Ge contacts utilizing Ge:P layers with a carrier concentration of 7 × 10 19 cm -3 exhibit ohmic property in contrast to the P ion-implanted Ge samples with almost the same P concentration and carrier concentration of 2 × 10 19 cm -3 . Thus, a ρ c value as low as 1.2 × 10 -6 Ωcm 2 was obtained for the Ti / Ge:P contact. A low R sh of 33 (Ω/sqr.) was shown for the 65-nm-thick P-doped Ge layer due to the high carrier concentration. The value of R sh for the epi-layer agrees with the theoretically predicted value, also resulting in reduction of parasitic resistances of the Ge-nMISFETs. The largest I d of Ge-nMISFET was obtained by utilizing the Ge:P to elevated S/D region of GeOI-nMISFETs. We can say that these results pave the way to the feasibility of Ge-CMOS.

One-monolayer deposition characteristics have been investigated for Ge on the Si(1 0 0) surface and Si on the Ge(1 0 0) surface by using a co-axial impact collision ion scattering spectroscopy. A subtracted spectrum method has been proposed for the detailed analysis of the interface structure. Incident angle dependence of the signal intensity shows that both Ge/Si and Si/Ge hetero-interfaces are atomically abrupt without intermixing and surface segregation.

Atomic layer epitaxy of silicon has been studied by alternating exposures of atomic hydrogen and SiH2Cl2. An ideal growth rate of 1 monolayer per cycle has been achieved with a wide temperature window from 550 °C to 610 °C under long SiH2Cl2 residence time and high pressure conditions. These requirements seem to come from the generation of dense SiHCl, the desirable precursor, by gas-phase reaction of SiH2Cl2.

The authors found the method to form HfSiON film with an ultrathin SiO/sub 2/ interfacial layer on the Si substrate by oxidizing the HfSiN. The HfSiN film was deposited by using the metal-organic chemical vapor deposition reactor with the shower head, supplying metal (Hf and Si) precursors and NH/sub 3/ gas separately from discharge nozzles. The authors successfully decreased the leakage current of the metal insulator semiconductor diode with HfSiON/SiO/sub 2/ insulator of 1-nm equivalent oxide thickness to 0.036 A/cm/sup 2/ at V/sub fb/-1 V.

Aiming to clarify why only silver is an effective catalyst for the partial oxidation of ethylene, we studied theoretically the reactivity and the stability of oxygen species on Cu, Ag, and Au surfaces. We used the dipped adcluster model (DAM), since electron transfer from metal to oxygen is important, and the SAC SAC-CI method, since several electronic states are involved. We found that if superoxide species exists on the surface, both Cu and Au surfaces show a reactivity similar to Ag surface, leading smoothly to ethylene oxide, and the barriers leading to complete oxidations should be very high. Therefore, the point is the relative stability of the various oxygen species and, in particular, the stability of the superoxide species on the metal surface. On Cu, superoxide is much less stable than peroxide, which again is less stable than the dissociated species, and no barrier exists for the conversion from superoxide to peroxide. On Au, our DAM calculations show that the electron flow from the bulk metal into the adcluster does not occur, so that the molecularly adsorbed oxygen species, as well as the dissociative ones, find it difficult to exist stably on the clean surface. On Ag, superoxide should certainly have some life time to react with ethylene to give ethylene oxide, which is considered to be the origin of the unique catalytic activity of silver for the epoxidation of ethylene. This is related to the ability of electron transfer and to the geometry of the Ag surface. We have proposed a basic idea for a new catalytic design of the epoxidation reaction.

The partial oxidation of ethylene to ethylene oxide catalyzed by silver is studied by the ab-initio Hartree-Fock and MP2 methods using the dipped adcluster model (DAM). The active species is the superoxide O − 2 which is molecularly adsorbed in a bent end-on geometry on the silver surface. Ethylene reacts with the terminal oxygen atom and the reaction proceeds smoothly without a large barrier to yield ethylene oxide. The complete oxidation of ethylene involving the superoxide is forbidden due to the existence of a large energy barrier. This is one origin of high selectivity. Without the silver surface, the epoxidation reaction is very unfavorable, showing the catalytic activity of the silver surface. The atomically adsorbed oxygen seems not to be selective: it gives both ethylene oxide and complete oxidation products. Therefore, adding to the selectivity due to the superoxide, an overall selectivity larger than 6 7 can be possible. In the process yielding ethylene oxide from atomic oxygen, electron transfer and back-transfer from/to the metal are important processes which can be promoted by both electron donor and acceptor. Detailed electronic mechanisms are clarified and discussed.

Atomic layer etching of Ge has been investigated experimentally based on the surface chemistry that Cl can adsorb on the clean Ge surface at room temperature and desorb thermally as GeCl 2 at high temperatures. The ideal etching rate of one monolayer per cycle has been achieved. The critical Cl 2 dosage for the saturated etching rate was about 7.2×10 6 L. Increase of the surface roughness after etching of 100 cycles was about 3.5 monolayers.

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.