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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanosheet stacked channels provided superior process integration robustness compared to Nanowire-On-Fin stacked channels. For the Nanowire-On-Fin option, using an SOI substrate as the starting material (compared to Si bulk or DSOI) also strongly reduced process variation failure rates.

In the past few years, novel fabrication schemes such as parallel and monolithic 3D integration have been proposed to keep sustaining the need for more cost-efficient integrated circuits. By stacking several devices, wafers, or dies, the footprint, delay, and power can be decreased compared to traditional 2D implementations. While parallel 3D does not enable very fine-grained vertical connections, monolithic 3D currently only offers a limited number of transistor tiers due to the high cost of the additional masks and processing steps, limiting the benefits of using the third dimension. This book chapter introduces an innovative planar circuit netlist and layout approach, enabling a new 3D integration flow called 3D Nanofabric. The flow, consisting of N identical vertical tiers, is aimed at single instruction multiple data processor Arithmetic Logic Units (ALUs). By using a single metal routing layer for each vertical tier, the process flow is significantly simplified since multiple vertical layers can potentially be patterned at once, similar to the 3D NAND flash process. In our study, we thoroughly investigate the layout constraints arising from the Nanofabric flow and the non-crossing planar graph constraint and propose several techniques to overcome them. We then show that by stacking 32 layers to build a 32-bit ALU, the footprint is reduced by \(8.7{\times }\) compared to a conventional 7 nm FinFET implementation.

Interconnect options will be introduced and reviewed targeting tight pitch metal layers at the local levels. Examples include hybrid metallization, semi-damascene interconnects as well as potential new conductor materials.

In the past few years, novel fabrication schemes such as parallel and monolithic 3D integration have been proposed to keep sustaining the need for more powerful integrated circuits. By stacking several devices, wafers, or dies, the footprint, delay, and power can be decreased when compared to traditional 2D implementations. While parallel 3D does not enable very fine-grained vertical connections, monolithic 3D currently only offers a limited number of transistor tiers due to the high cost of the additional masks and processing steps, limiting the benefits of using the third dimension. In this paper, we introduce an innovative planar circuit netlist and layout approach, which enables a new 3D integration flow called 3D Nanofabric. The flow, consisting of $N$ identical vertical tiers, is aimed at single instruction multiple data processor Arithmetic Logic Units (ALUs). By using a single metal routing layer for each vertical tier, the process flow is significantly simplified since multiple vertical layers can potentially be patterned at once, similar to the 3D NAND flash process. In our study, we thoroughly investigate the layout constraints arising from the Nanofabric flow and the unique metal layer rule and propose several ways to overcome them. We then show that by stacking 32 layers to build a 32-bit ALU, the footprint is reduced by $8.7\times$ when compared to a conventional 7nm FinFET implementation.

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $( . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $\mathrm{I}_{\mathrm{on}}-\mathrm{I}_{\mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

For porous low-k film to be integrated into the next generation of interconnects, the pores need to be sealed against metal ions and barrier precursors. Self-assembled monolayers (SAMs) from organosilane precursor are spin coated onto 300mmk=2.2 low-k wafers. Two solvents, propylene glycol monomethyl ether acetate (PGMEA) and methanol with different dielectric constant of 8.3 and 20.1, are evaluated in terms of SAMs layer quality and sealing efficiency at coupon level. SAMs deposited from PGMEA show better sealing than SAMs deposited from methanol and therefore are selected for upscaling. Full wafer spin coating results show that a concentration of 0.05mM or below results in a partial coverage and a tilt angle as high as 70° from the backbone to the normal. Aggregation is observed for all tested concentrations and is worse for higher concentrations, which is possibly induced by the non-negligible presence of water in PGMEA solvents. In order to test the sealing efficiency of the SAMs layer against metal barrier precursors, MnN films by chemical vapor deposition (CVD) and TaNx/Ta (TNT) films by physical vapor deposition (PVD) are deposited on SAM coated low-k wafers. HfO2 is also deposited by Atomic layer deposition (ALD), which is not considered as a barrier but to test the sealing against ALD precursors. Depth profiling Rutherford Backscattering Spectrometry (RBS) measurements indicate an effective sealing of SAMs against CVD and ALD precursors but not against PVD barrier. Display Omitted SAMs are spin coated onto 300mm low-k wafers. After SAMs deposition, źk is 0.1 and decreases to 0.03 after annealing.Solvent dielectric constant affect the pre-condensation of SAMs and therefore sealing.RBS measurements shows that SAMs seal against MnN by CVD but not TNT by PVD.

Three CFET process flow options, starting with Si bulk, SOI or DSOI substrates respectively, were compared in their likelihood to experience process variation failures. This study was performed using virtual fabrication technologies, without requiring the fabrication of any actual test wafers. The SOI process flow option was identified as the most robust option among the three possibilities.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

Area scaling without compromising on performance has become a challenge for technology nodes beyond N7. Gate all-around (GAA) device architecture for N5 and beyond technology nodes is emerging as a promising solution and is being heavily investigated by the semiconductor industry. Imec has recently demonstrated that GAA transistor design offers 50% area scaling for both standard cells and SRAM memory cells, by stacking NMOS and PMOS wires on top of each other (also called complimentary FET (CFET)). In addition, design technology co-optimization analysis indicates that CFET architectures meet the N3 power and performance requirements (Ryckaert et.al.; SPIE 2018, VLSI technology symposium 2018). However, integration and fabrication of such CFET architectures become significantly challenging. A primary requirement for GAA (CFET or separate NMOS/PMOS) devices is the formation of silicon channels / nanowires (NW)/nanosheets (NS). For CFET fabrication, a quintessential challenge is an etching method which can provide required selectivity to recess an epitaxially grown material selective to either NMOS or PMOS channel materials into a low-k gate spacer with adequate etch selectivity in an isotropic manner such that stacked wires or sheets can be formed either sequentially or simultaneously. In the article, we will focus mainly on the Si NW/NS formation (or SiGe etch). Fabricating such NW/NS architecture requires two extremely selective, isotropic, and precise SiGe etches. As shown in Fig.1, step 2 (“SiGe cavity etch”) & step 8 (“channel release”). After the “SiGe cavity etch”, an ALD film of low-k spacer is deposited as the inner spacer (Fig.1, step 3). The SiGe cavity etch (Fig.1, step2) must be controlled with an extreme accuracy and have a straight etch front. The cavity etch will effectively define the inner spacer thickness in the area above and below the Si NW, after the inner spacer etch (step 4, Fig.1). A precise SiGe etch control is essential for the cavity formation, because: (1) if the SiGe recess is below target, the reformed inner spacer thickness will be under specification and may result in high parasitic capacitance between gate and source/drain expected. (2) If the SiGe recess is above target, the reformed inner spacer will penetrate into the replacement gate and will decrease the amount of gate metal wrapping around the nanowire and may impact channel length (Lg). Furthermore, in addition to the above requirements, etch selectivity towards the dummy gate, hard mask, oxide (STI, ILD0), and low K material around the gate (as shown in Fig 1) is essential. We will also demonstrate the process performance for “channel release” as mentioned earlier (Fig 1, step 8) and inner spacer etch (Fig 1, step 4) .To address the requirements described above, a process flow enabled with extremely high selective etches, where the selectivity is a function of film properties and/or etch chemistry is a quintessential advantage. In this article, we will demonstrate the significance of such selective etches for Si NW/NS fabrication.

3 Dstacking using a sequential integration approach is demonstrated for finfet devices on 300mm wafers at a 45nm fin pitch and 110nm poly pitch technology. This demonstrates the compatibility of the 3D sequential approach for aggressive device density stacking at advanced nodes thanks to the tight alignment precision of the first processed top layer to the last processed bottom layer through the top silicon channel and bonding stack during 193nm immersion lithography. The top devices are junction-less devices fabricated at low temperature $(\mathrm{T}\leq 525^{\circ}\mathrm{C})$ in a top Si layer transferred by wafer-to-wafer bonding with a bonding dielectric stack down to 170nm. The top devices offer similar performance as the high temperature bulk finfet technology for LSTP applications. The use of TiN/TiA1/TiN/HfO 2 gate stack provides the proper threshold voltage adjustment while the insertion of the LaSiO x dipole improves device performance and brings the BTI reliability within specification at low temperature.

In this paper, we review the current progress on 3D sequential device stacking, highlighting the main integration challenges and the possible technological solutions. Junction-less devices are shown to be attractive top tier devices for low temperature processing, low complexity of fabrication and meeting reliability specification despite without the use of “reliability” anneal. Next, we explore the potential benefits of 3D sequential stacking at transistor level, CMOS level and for hybrid circuits.

A flow, module steps and key structural elements enabling a surrounding gate transistor (SGT) based 6T-SRAM with 50nm pillar pitch and 0.0205 um2 are presented, with emphasis on process challenges and innovations. A new DTCO/TCAD methodology is used to explore the design space, demonstrate the bit cell functionality and optimize the process. In particular, it is shown that vertical SGT are extremely sensitive to gate misalignment and that buried bottom contact makes the process immune to doping variations and misalignments.

The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.

This paper discusses SRAM scaling beyond the 5nm technology node and highlights the fundamental scaling limits due to FinFET and Gate all-around (GAA) technology. To compensate for expected gate pitch scaling slowdown below 42nm, several scaling boosters are needed to reduce the cell height. However, limited scaling benefits can be achieved in FinFET and GAA technology. Therefore, a novel vertically stacked lateral nanosheet architecture using a forked gate structure is proposed showing superior performance and area scaling compared to FinFET and GAA devices. Moreover, limited additional processing complexity can be achieved. The Fork architecture allows 20% SRAM area scaling at isoperformance and 30% performance increase at iso-area compared to FinFET beyond 5nm technology node.

© 2016 Author(s). For Cu/low-k interconnects, the reversed damascene is an alternative integration approach where the metal wires are patterned first and then the spacing filled with a flowable dielectric. In this paper, the replacement of a sacrificial template by gap-filling ultralow-k dielectrics is studied, focusing on yield and transport performance (“replacement dielectric” scheme). On non-passivated copper, the low-k curing processes induce severe damage to the metal lines, leading to the degraded electrical properties. This is confirmed by chemical inspection on the blanket Cu films and morphological inspection on patterned structures. In order to avoid Cu oxidation and out-diffusion at elevated temperature, Cu passivation by plasma-enhanced chemical vapor deposition SiCN is proposed and studied in detail. The inter-metal dielectric properties of replacement low-k are evaluated by resistance-capacitance and IV measurements using a Meander-Fork structure. By tuning the passivation layer thickness and ultraviolet curing time, high electrical yield is obtained with integrated porous low-k showing promising effective k-values (keff) and breakdown voltages (Ebd), confirming the interest of this specific integration scheme. ispartof: Applied Physics Letters vol:109 issue:23 pages:232901-2329001 status: published

© 2015 AIP Publishing LLC. Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constant of the gap-fill low-k is investigated on a 45 nm 1/2 pitch Meander-Fork structure, leading to keffbelow 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials. ispartof: Applied Physics Letters vol:107 issue:9 pages:092901- status: published

In order to understand the state of process induced stresses in air-gap interconnect structures fabricated by means of etch-back procedure, finite element (FE) models of a 90nm pitch interconnect were developed and stress analysis of the structure was conducted as a function of the dielectric liner and metal barrier (MB) thicknesses in a parametric study in order to minimize the risk of mechanical failure. The results identified the sidewall dielectric liner as the critical location where high stresses can result in failure of structures under thermo-mechanical loads. Simulations suggest that optimal mechanical stability is achieved by minimizing the MB thickness and maximizing the thickness of the conformal dielectric liner. The upper limit of the liner thickness however, is dictated by restrictions imposed by interline capacitance which can lead to RC delay.

It is clear today that further scaling towards smaller dimensions and pitches requires a multitude of additional process steps. Within this work we look for solutions to achieve a middle of line 193i based patterning scheme for N7 logic at a contacted poly pitch of 40-45 nm. At these pitches, trenches can still be printed by means of double patterning. However, they need to be blocked at certain positions because of a limited line end control below 90 nm pitch single print. Based on the 193i patterning abilities, the proposed SRAM (Static Random Access Memory) cell requires 5 blocking layers. Integrating 5 blocking layers is a new challenge since down to N10 one blocking layer was usually sufficient. The difficulty with multiple blocking layers is the removal of the masked parts, especially in cases of overlap. As a solution a novel patterning approach is proposed and tried out on relaxed dimensions (patent pending). The proposed solution is expected not to be sensitive to the number of blocking layers used, and tolerates their overlap. The stack is constructed to be compatible with N7 substrates such as SiGe or P:Si. Experimental results of the stack blocking performance on relaxed pitch will be presented and discussed.

This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.

Post porosity pore protection is studied as a means for low damage integration of porous low-k dielectrics. Homogeneous low-k densification is achieved using poly(methyl methacrylate) (PMMA) as a sacrificial filler. The improvement in plasma-induced damage is investigated on a plasma-enhanced chemical vapor deposition 2.0 porous organo-silicate glass, including damage from radicals and vacuum ultraviolet photons. Open pores are sealed upon polymer protection; therefore the penetration of metal species during deposition of a metal diffusion barrier is avoided. Various solutions for post metallization polymer removal are investigated, such as hydrogen remote plasma and an ultraviolet cure. The PMMA removal process is studied in order to avoid Cu wire degradation. Finally, low-k damage and barrier continuity are investigated on patterned wafers with functional circuits. By means of transmission electron microscopy inspection and electrical measurement, effective integrated k-values are extracted, giving a value k eff ~ 2.5–2.6 for the post metallization polymer removal option.

The use of directed self-assembly (DSA) of cylinder forming block copolymers (BCP) for contact hole shrink applications has gained increased attention due to the dimensions that can be achieved with this materials. Recent work has focused on engineering the dimensions and surface energy of the templates to obtain straight profiles of the cylinders assembled in them. However, the impact of process optimization on defect formation is measured using scanning electron microscopy before and after transferring the BCP features to a hardmask, which provides limited information about the presence of defects or three-dimensional morphologies in the polymer structures. To identify the presence of single defects in arrays of various densities and sizes, we use Kelvin and chain structures available in the IMEC 28-nm node via chain electrical test vehicle, Everest, in combination with templated DSA. We tuned the surface energy and dimensions of the templates with the use of random copolymers and through the exposure conditions, respectively. Finally, the contact holes obtained with templated DSA of BCP were subsequently transferred into a relevant stack to apply advanced metallization processes and, ultimately, validated electrically.

This paper reviews the most encouraging process options for improving backend-of-line reliability performance in advanced technology nodes. Metal capping yields the best electromigration performance; however, this process is most challenging with respect to integration and may also suffer from significantly decreasing grain sizes in trench bottoms for future technologies. Furthermore, time-dependent dielectric breakdown has to be carefully evaluated. Alloying or silicidation techniques are less challenging to implement but can result in unacceptably high resistance increases. We analyze the respective results for each option and compare the performance on 45, 32, and 28nm technology nodes. In addition to electromigration and time-dependent dielectric breakdown, the impact of the various process options on stress migration performance is discussed.

In this paper we present process options to close the gap between electromigration performance needs by design and process performance. We are going to present reliability data for metal capping and advanced copper surface cleaning processes. These processes are showing very good performance and extendibility to 32nm technology nodes and beyond.

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Process simulations provide vital insights to identify the key process steps to dedicate wafer resources for improvement or to determine investment on tool capability. We considered this problem in the context of an industry-like 5nm Back-End-of-Line flow being developed in IMEC and modeled the approximately 150 step process flow in COVENTOR SEMulator3D®. For the first time a one-million wafer Design of Experiments was conducted to sample a 10-dimensional variable space and derive the failure points for each process parameter. A vector based algorithm was used to search the parameter space and derive a hyper-surface to represent the absolute yield limits. The virtual wafers were run to identify process sensitivities and spec limits for expected process variations. This work highlights that process optimization is needed to improve the capability of many processes to the order of 1nm and this methodology should be used to screen standard libraries for process sensitivities.