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A baseline TiAl-containing ALD electrode is established, with properties in line with reported workfunction (WF) materials for scaled RMG nFETs, values below 4.6eV requiring a 25A layer. Furthermore, a novel ALD metal-compound material, MX, is shown to enable at least 10A further scaling of the electrode stack due to its superior scavenging power. It can be finely tuned by the film thickness, allowing for a remarkable 20-30meV WF delta per ALD cycle over a minimum 600meV range. The wet etchability of the electrodes makes multi-Vt and dual-WF integration possible. MX does not degrade transfer characteristics and reliability of RMG FinFETs, while the thinner nWF electrode enables reduced gate resistance, as verified down to 20nm metal gate lengths. For the first time, taking advantage of the MX compound scavenging power to control oxygen filaments, we demonstrate an all-ALD HfO 2 -based ReRAM. Forming voltages match those achieved by optimized PVD contacts, while scaling the active electrode thickness by a factor of 4x, down to 5nm. Conformality of the layers enables vertical-ReRAM architectures with reduced line resistance. We conclude the developed electrode can facilitate both logic scaling beyond the 10nm node, and 3D memory technology.

We have demonstrated, for the first time, a combination of outstanding linearity of analog programming with matched PCM pairs, small analog programming noise, an extremely low resistance drift (R-drift) coefficient (0.005, median) and high endurance for a CVD-based confined phase change memory (PCM) with a thin metallic liner. In-depth analysis of linear analog programming is also presented. MNIST simulations using a pair of these confined PCM devices as a synaptic element yield a high test accuracy of 95%.

Silicon-Germanium (SiGe) is a material that possesses a multitude of applications ranging from transistors to eletro-optical modulators and quantum dots. The diverse properties of SiGe also make it attractive to implementations involving superconducting quantum computing. Here we demonstrate the fabrication of transmon quantum bits on SiGe layers and investigate the microwave loss properties of SiGe at cryogenic temperatures and single photon microwave powers. We find relaxation times of up to 100 $\mu$s, corresponding to a quality factor Q above 4 M for large pad transmons. The high Q values obtained indicate that the SiGe/Si heterostructure is compatible with state of the art performance of superconducting quantum circuits., Comment: 5 pages, 3 figures

We developed an Al2O3/HfO2 bi-layer gate dielectric with an in-situ O3 treatment for interface state density (Dit) and gate leakage current density (Jg) reductions on SiGe channels. We observed Ge-content dependent equivalent oxide thickness (EOT) scaling and EOT 0.44 nm was achieved with an MOS capacitor with a Si0.05Ge0.95 substrate. The O3 treatment enabled application to non-planar device structures and we demonstrated five orders of magnitude lower off currents (IOFF), a sub-threshold slope of 68 mV/decade, and a very high hole mobility of 457 cm $^{2}\text{V}^{\mathrm {-1}}\text{s}^{\mathrm {-1}}$ at an inversion carrier density (Ninv) of $1\times 10^{13}$ cm $^{\mathrm {-2}}$ for asymmetrically strained SiGe PMOSFETs with Ge% of 65%–70%.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of ∼10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm- $L_{g}$ device shows a peak $g_{m}$ of $1.37 \ \text{mS}/\mu \mathrm{m}$ , a subthreshold slope in saturation of 72 mV/decade, and an $I_{on}$ of $355 \ \mu \mathrm{A}/\mu \mathrm{m}$ at 0.5 V $V_{gs}$ , the highest among reported sub-50 nm- $L_{g}$ III-V FETs on Si.

Hot carrier stress is one of the key parameter for CMOS device reliability in semiconductor manufacturing process. Electron holography and scanning capacitance microscopy are used to map the junction for hot carrier stressed and unstressed device. Junction asymmetry is observed for the stressed device comparing with unstressed device, which indicates dopant deactivation (or movement) during the stress and it is contrary to the early proposed mechanism of carrier injection into gate oxide during the stress causing gate oxide damage. Based on that observation, we propose hydrogen atom released from the hot carrier stress de-activates phosphorus dopant on the drain side, which causes lower drive current.

Strained-SiGe, with high-Ge-content, has recently drawn significant attention as an alternate p-channel option for advance FinFETs. Among various technological challenges, gate stack is so critical to enable high-performance FETs. In this paper, key process details of the optimized gate stacks in high-Ge SiGe, such as IL formation and passivation, are disclosed and feasibility of Vth tuning by an ultra-thin replacement metal-gate scheme down to 15nm LG is demonstrated, for the first time. Moreover, near ideal SS, excellent reliability and mobility at scaled EOTs are achieved, which has led to high transconductance devices with proper junction engineering. In addition, we demonstrate the most aggressively-scaled SiGe fins reported to date formed by 3D-Ge-condensation, exhibiting excellent short-channel characteristics.

We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs. We also present some structural details of the gate stack, for the first time. Short channel characteristics of HGC SiGe FinFETs have also been studied for various fin widths. Compared to our earlier RMG work, improved I/I free process with ultra-thin spacers has led to considerable R on and R ext reduction. As a result, we have demonstrated very high SiGe performance with I on =0.45mA/μm at I off =100nA/μm at V dd =0.5V for L G =25nm, matching our record for gate-first SiGe FinFETs and outperforming the gate-first results at such LG.

Electromigration and resistivity of Cu, Co and Ru on-chip interconnection have been investigated. A similar resistivity size effect increase was observed in Cu, Co, and Ru. The effect of liners and cap, e.g. Ta, Co, Ru and SiC x N y H z , on Cu/interface resistivity was not found to be significant. Multilevel Cu, Co or Ru back-end-of-line interconnects were fabricated using 10 nm node technology wafer processing steps. EM in 22 nm to 88 nm wide Co lines, 24 nm wide Cu with and without a thin Co cap and 24 nm wide Ru lines were tested. These data showed that Cu with a Co cap, Co and Ru had highly reliable EM, although Ru was better than Co and Co was better Cu. The electromigration activation energies for Cu with Co cap and Co were found to be 1.5–1.6 eV and 2.1–2.7 eV, respectively.

FinFETs with strained-SiGe channel have recently drawn significant attention due to their built in uniaxial strain, higher mobility and better reliability over conventional Si FETs. Research on pure Ge has been the major focus of many institutes over the past few years. However, with high-Ge-content (HGC) SiGe one can benefit from competitive or better performance over pure Ge and overcome the thermal budget constraints required for Ge. In this paper, we briefly review our latest advancements in high-Ge-content strained-SiGe FinFETs featuring gate first and Replacement HK/MG (RMG) flows with record mobility and short-channel performance to extend the roadmap for advanced FinFET and FDSOI generations.

IBM engineers have developed a holographic imaging technique, called dual-lens electron holography, that provides high spatial resolution and field of view without compromising signal-to-noise ratio. This article reviews the basic principles of the new method and provides several examples of its use. The first few examples demonstrate the junction profiling capabilities of the new method which, in one case, helps to explain why shallow junction devices are made with raised source-drain regions. In the other examples, dual-lens holography is used for strain mapping, in one case, to study strain distributions in sigma-shaped SiGe devices, and in another, to provide evidence that stress memorization occurs in dislocations in the source-drain region of nFET devices.

Epitaxial growth of SrTiO₃ on silicon by molecular beam epitaxy has opened up the route to the integration of functional complex oxides on a silicon platform. Chief among them is ferroelectric functionality using perovskite oxides such as BaTiO₃. However, it has remained a challenge to achieve ferroelectricity in epitaxial BaTiO₃ films with a polarization pointing perpendicular to the silicon substrate without a conducting bottom electrode. Here, we demonstrate ferroelectricity in such stacks. Synchrotron X-ray diffraction and high-resolution scanning transmission electron microscopy reveal the presence of crystalline domains with the long axis of the tetragonal structure oriented perpendicular to the substrate. Using piezoforce microscopy, polar domains can be written and read and are reversibly switched with a phase change of 180°. Open, saturated hysteresis loops are recorded. Thus, ferroelectric switching of 8- to 40-nm-thick BaTiO₃ films in metal-ferroelectric-semiconductor structures is realized, and field-effect devices using this epitaxial oxide stack can be envisaged.

Lanthanum aluminate (LAO) films were grown epitaxially on Si (001) by atomic layer deposition (ALD) using a buffer layer of strontium titanate (STO) grown by molecular beam epitaxy. The ALD growth of LAO was done at 250 °C by using tris(N,N′-diisopropylformamidinate)–lanthanum, trimethylaluminum, and water as co-reactants. Reflection high-energy electron diffraction, X-ray diffraction and transmission electron microscopy were used to determine film crystallinity. The as-deposited LAO films were amorphous and became crystalline after vacuum annealing at 600 °C for 2 h. In-situ X-ray photoelectron spectroscopy (XPS) was used to characterize the LAO/STO/Si interfaces at various stages throughout the growth and annealing process. XPS analysis showed minimal SiO bonding at the STO/Si interface after the ALD process and after post-deposition annealing at 600 °C for 2 h. The results demonstrate a method to integrate epitaxial LAO films on Si (001) substrates by ALD.

High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L G =21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W FIN ) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT∼7A, and excellent μ eff =220cm2/Vs at N inv =1013 for fins with W FIN ∼4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.

A process for fabricating dense graphene nanoribbon arrays using self-assembled patterns of block copolymers on graphene grown epitaxially on SiC on the wafer scale has been developed. Etching masks comprising long and straight nanoribbon array structures with linewidths as narrow as 10 nm were fabricated, and the patterns were transferred to graphene. Our process combines both top-down and self-assembly steps to fabricate long graphene nanoribbon arrays with low defect counts. These are the narrowest nanoribbon arrays of epitaxial graphene on SiC fabricated to date.

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO"2 formation and silicidation and equivalent oxide thickness (EOT) of 5A is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO"2-SiO"2 intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6A with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.

We investigate the determining mechanisms of the inversion-layer capacitance Cinv in the high-k/metal gate stacks, focusing on the two perturbative effects related with the dielectric properties. Those effects are the penetration of inversion-layer carriers into the dielectrics with a finite potential barrier and the image potential acting on the carriers adjacent to the dielectrics with permittivity different from that of the silicon substrate. The experimental and the theoretical analyses of the Cinv dependency on the crystal orientation of silicon substrates enable us to separate the two effects and to prove that the observed Cinv modulation in the high- k/metal gate stacks is attributable not to the image potential effect, but to the penetration effect. Moreover, we investigate the reduction of the total gate capacitance due to the Cinv in the advanced gate stacks scaled down to 0.66-nm equivalent oxide thickness. The influence of the elementary composition, the physical thickness, and the interface layer on a scaling loss due to the Cinv is experimentally evaluated.

Strain engineering for pFETs has been conventionally enabled utilizing embedded SiGe in the source/drain regions to continuously boost the transistor current drive and transconductance [1]. Historically, for planar technologies, transconductance was monotonically improved by advancing the technology generations. However, this trend for transconductance, when properly normalized to the effective device width (fin perimeter) is no longer observed when FinFETs were introduced to the mainstream CMOS to improve the short channel effects for sub 30nm gate lengths [2]. The FinFET transconductance saturation or drop be attributed to ineffectiveness of the embedded SiGe stressors (in spite of higher mobility near-(110) surfaces) and/or increased contribution of the S/D resistance as the contacted gate pitch size aggressively scales down. Unless there is a strong and reliable method to externally apply gigantic strain to the Si fin channel, using strained SiGe (s-SiGe) channel, with built-in uniaxial compression, is a strong option to overcome this issue. In fact, SiGe has been utilized in CMOS industry as a knob to control the threshold voltage (Vth) and in part to boost the pFET reliability and transport [3]. Moreover, introduction of SiGe channel for planar pFET has improved reliability, resulting in further Capacitance-Equivalent-oxide-Thickness (CET) scaling over Si. For s-Si1-xGex FinFETs, choice of Ge content (x) is not trivial. Adding more Ge can ideally build in more channel stress resulting increased hole mobility and current drive. However, epitaxial-defect-driven fin height control due to the critical thickness constraints, process thermal budget, bandgap reduction and gate-induced drain leakage (GIDL) control remain challenging. In particular, High-Ge-Content (HGC) s-SiGe FinFETs are of great interest for two reasons, from the transport point of view: First, very high level of strain (close to 3GPa) can be achieved when lattice matched to Si [4]. Second, if strain-relaxed buffer (SRB) SiGe with moderate Ge % is used to tensily strain Si nFET, higher Ge is required to compressively strain the pFET [5]. The GIDL issue can be mitigated by operating the high-performance (HP) device at a lower VDD, i.e. below 0.6V, in line with logic roadmap [4]. Controlling the HFIN, to be competitive with the state-of-the-art Si FinFETs, remains challenging. Above all, a major challenge is associated with the gate stack and interface trap control which is more pronounced in HGC SiGe than Si and pure Ge. In this talk, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe will be discussed and their impact on key device characteristics will be presented. In particular, we review our recent advancement to achieve optimized RMG IL and passivation [6], high hole mobility and record performing short channel pMOS FinFETs. In additions, a metal gate work-function tuning solution will be presented utilizing an ultra-thin replacement metal-gate scheme to achieve target high-performance off current down to 15nm gate lengths. References: [1] T. Ghani et al., IEDM, 2003, p. 197. [2] P. Hashemi, et al., IEDM, 2017, p. 824. [3] S. Krishnan et al., IEDM, 2011, p. 634. [4] P. Hashemi et al., IEDM, 2014, p. 402. [5] R. Xie et al., IEDM, 2016, p. 47. [6] P. Hashemi et al., VLSI Tech. Symp., 2017, p. 120.

The effect of hot carrier injection on the FET's junction properties has been investigated for CMOS NFET devices. Junction profiles and carrier concentration of stressed and unstressed devices are measured and compared by dual lens electron holography and scanning capacitance microscopy, respectively. The measurements reveal that the width of the junction on the drain side of the device that undergoes hot carrier stressing decreases, indicating a reduction in active carrier concentration. These results are consistent with the hypothesis of phosphorous dopant passivation by the hot carrier induced release of hydrogen into the drain side extension region.

We demonstrate a novel remote interfacial layer (IL) scavenging technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based high-k gate dielectric. The remote IL scavenging shows advantages in carrier mobility and gate leakage current over conventional IL scaling schemes. Moreover, this method enables intrinsic EOT scaling without introducing additional charges and interface degradation. It is shown that the mobility degradation observed for a La-containing high-k is not due to the La-induced dipole but due to the intrinsic IL scaling effect, whereas an Al-induced dipole brings about additional mobility degradation. This unique nature of the La-induced dipole in conjunction with the IL scaling enables aggressive EOT scaling toward the end of the road map.

We discuss options for metal-oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity ('high-k') gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO"2 can be scaled to capacitance equivalent thickness in inversion (T"i"n"v) of 10A and equivalent oxide thickness (EOT) of 6A by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si"3N"4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based 'higher-k' dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO"2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO"2 at the poly-Si contact. We further address the performance of Si"3N"4 and HfO"2 as oxygen barrier layers.

In this work, co-sputtered TaC (tantalum + carbon targets + argon) and reactive sputtered TaC (tantalum + methane + argon) were evaluated and compared for application as metal electrodes in high-K/metal gate stacks aimed at 22 nm and beyond technology nodes. The electrical properties of field effect transistors (FETs) were evaluated as a function of TaC deposition conditions and optimized to achieve Tinv scaling. Controlling the deposition conditions as well as the composition of the TaC films was found to be critical to achieve Tinv < 11 Aå.

In this paper we will review some of our previous work on ALD deposited high-K dielectric stacks as well as present some of our more recent advances. We have shown that ALD can be used successfully to deposit high quality high-K gate dielectrics of Hf and Zr oxide. In addition, because of the inherent conformality of ALD processes, these dielectrics can be easily migrated to advanced device structures such as FINFETs. We have also been successful in developing ALD processes to deposit rare earth oxides (REOs), such as Y2O3 and La2O3. These processes are useful in creating layered dielectric structures where the REO functions as a threshold voltage adjustment layer. We use physical and electrical characterization of the films as deposited by ALD, including spectroscopic ellipsometry, corona oxide semiconductor charge measurement, TXRF, AES, angle resolved XPS, HRTEM, AFM, MEIS, and RBS, to provide information on the film growth mechanism and the primary parameters that influence the ALD growth of high-K oxides. We further correlate these findings with basic electrical results obtained from MOSFET and MOSCAP devices fabricated using our ALD processes to understand how process changes affect both the as-deposited films as well as the resulting devices.

In this paper, we develop a multiplicative model to simulate the tungsten (W) film resistivity and gate resistance for replacement metal gate (RMG) with W electrode. Our multiplicative model predicts that TiN fill offers the lower gate resistance than TiN/W fill for highly scaled gate lengths. By absorbing the results from our model into the real RMG FinFET devices, we observe that TiN fill provides ∼6.4 % performance improvement compared to TiN/W fill. Meanwhile, the employment of gate conductance for gate stack film thickness monitoring is also described in our work.

As semiconductor device scaling continues to reduce the structure size, device geometries are also changing to three dimensional structures such as finFETs, and the materials which compose the devices are also evolving to obtain additional device performance gains. The material change studied in this paper is the introduction of silicon germanium into the electrically active region of a finFET test structure. The paper demonstrates a quantitative energy dispersive X-ray spectroscopy transmission electron microscopy (TEM) technique through the use of blanket film calibration samples of known concentration characterized by X-ray diffraction. The technique is used to identify a test structure issue which could only be diagnosed with a technique having nanometer spatial resolution and atomic percent sensitivity. The results of the test structure analysis are independently verified by the complementary TEM electron energy loss spectroscopy technique.

High mobility (III–V) materials have long been anticipated to replace Si MOSFETs. But only recently [1] were scaled InAs MOSFETs reported to outperform Si devices. However, high-performing III–V devices are typically fabricated on InP substrates which are not compatible with large-scale chip manufacturing. While various III–V on Si fabrication approaches have been reported to overcome this issue, they either suffer from limited material quality or are economically not competitive compared to Si substrates. Here we demonstrate a versatile approach for heterogeneous integration of III–Vs on Si and validate this by the fabrication of multiple-gate (MuG)-FET devices. The study is complemented by performing TEM analysis, TLM and Hall measurements.

We demonstrate scaled High-Ge-Content (HGC) SiGe-OI finFET with Ge up to 71%, using a CMOS-compatible approach. For the first time, aggressively scaled HGC relatively-tall fins with vertical sidewalls and sub-10nm widths have been demonstrated using an enhanced 3D-Ge-condensation technique. An improved Si-cap-free HK/MG process featuring optimized IL has been developed resulting in scaled EOT and impressive long channel SS=69mV/dec. The gate stack results in realization of enhancement-mode devices for Ge content ∼0.6. Moreover, long-channel mobility characteristics at scaled EOT as well as short-channel pMOS FinFETs with decent cut-off behavior and performance are demonstrated, for the first time. As a result, we report the highest HGC SiGe pMOS FinFET mobility of ∼300cm2/Vs at N inv =1013cm−2 at scaled EOT=0.85nm.

International audience; The detailed strain distributions produced by embedded SiGe stressor structures are measured at high spatial resolution with high precision, with dual lens dark field electron holography and precession electron diffraction. Shear strain and lattice rotation within the crystalline lattice are observed at the boundaries between the SiGe and Si regions. The experimental results are compared to micromechanical modeling simulations to understand the mechanisms of elastic relaxation on all the modes of deformation at a sub-micron length scale. (C) 2015 AIP Publishing LLC.

The backscattered electron (BSE) signal in the scanning electron microscope (SEM) can be used in two different ways. The first is to give a BSE image from an area that is defined by the scanning of the electron beam (EB) over the surface of the specimen. The second is to use an array of small BSE detectors to give an electron backscattering pattern (EBSP) with crystallographic information from a single point. It is also possible to utilize the EBSP detector and computer-control system to give an image from an area on the specimen--for example, to show the orientations of the grains in a polycrystalline sample ("grain orientation imaging"). Some further possibilities based on some other ways for analyzing the output from an EBSP detector array, are described.

Origins of effective work function (EWF) roll-off behavior accompanied by equivalent oxide thickness (EOT) scaling for high- κ last replacement metal gate (RMG) stacks are investigated using a low-temperature interfacial layer (IL) scavenging technique. The EWF-EOT roll-off is driven by a high work function metal and the trend is linear and reversible by means of IL scavenging and regrowth reactions. These findings are consistent with the oxygen vacancy model, indicating that the same mechanism that plagued gate-first devices emerges as the IL thickness is scaled

High-spatial-resolution analytical electron microscopy using energy-dispersive X-ray (EDX) and electron energy-loss spectrometry (EELS) of yttrium- and lanthanum-doped Al2O3 has been conducted to ascertain the level of segregation of these impurities to grain boundaries. Line profile analyses indicate that the segregation is confined to a layer thickness of

The benefit of La-Al-O higher-k gate dielectrics is maximized by optimizing the Al/(La+Al) atomic ratio. The Al/(La+Al) atomic ratio modulates the band gap, dielectric constant, and interface dipoles, resulting in change of energy band alignment. The La-Al-O film with an Al/(La+Al) atomic ratio of 0.25 yields a maximum leakage current reduction exceeding HfO2 and La2O3, owing to the optimized band alignment structure. Moreover, a SiON underlayer instead of SiO2 enables additional equivalent oxide thickness scaling down to 7.4 Å while maintaining the fully reduced leakage current with a gate-first process.

We observe the growth of crystalline SiC nanoparticles on Si(001) at 900 °C using in situ electron microscopy. Following nucleation and growth of the SiC, there is a massive migration of Si, forming a crystalline Si mound underneath each nanoparticle that lifts it 4–5 nm above the initial growth surface. The volume of the Si mounds is roughly five to seven times the volume of the SiC nanoparticles. We propose that relaxation of strain drives the mound formation. This new mechanism for relieving interfacial strain, which involves a dramatic restructuring of the substrate, is in striking contrast to the familiar scenario in which only the deposited material restructures to relieve strain.

We demonstrate a Simple Gate Metal Anneal (SIGMA) stack for FinFET Replacement Metal Gate (RMG) technology, which uses only thin TiN layers as workfunction (WF)-setting metals for CMOS integration. The SIGMA stack provides 100× PBTI lifetime improvement via band alignment engineering. Moreover, the SIGMA stack enables 9nm more gate length (L g ) scaling compared to the conventional stack with matched gate resistance and thus opens up pathways for aggressive L g scaling toward the 14nm node and beyond.

We report complementary metal–oxide–semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si–InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

An extremely low contact resistivity of 6-7 × 10-9 Ω·cm2 between Ni0.9Pt0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation. In this scheme, the implantation of B or As is performed into silicide followed by a low-temperature drive-in anneal. Reduction of effective Schottky barrier height is manifested in the elimination of nonlinearities in IV characteristics.

Grain-boundary embrittlement, caused by the segregation of impurity and alloying elements, occurs in many systems and has been the focus of a large amount of research owing to its technological importance. However, the exact mechanism by which the segregating elements cause embrittlement remains unclear. In this paper the localized changes in the electronic structure in the classical embrittling system of Bi in Cu have been studied. Experimental results were obtained by examining the fine structure in the electron energy loss spectrum which was then compared to calculations using the layer Korringa-Kohn-Rostoker (LKKR) method. A change in the d density of states has been observed for the Cu atoms at the grain boundary, associated with Bi, and an electronic model to explain embrittlement is described.

The use of telepresence microsopy (TPM) over the Internet for teaching is demonstrated. A high-resolution field-emission gun transmission electron microscope (TEM) at Oak Ridge National Laboratory was operated by undergraduate students at Lehigh University, 800 miles away. The remote operation used commercial software and freeware. The advantage of computer-controlled TPM and is that students can access dedicated equipment not available in their home laboratory and also parallel hands-on access and instruction can be given to a much larger group of students than usually can be taught on a TEM. Drawbacks include the bandwidth of the Internet.

Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.

SUMMARY To extract quantitative electronic structure information from electron energy-loss near-edge structure typically necessitates the separation of spectra into linearly independent components. For this to be accomplished, certain conditions need to be met concerning the localization of chemical bonding and the linear scaling of fine structure with density of states. The dependence of the processing parameters, such as window widths and positions, of the commonly used ‘two-window intensity-ratio’ method to determine the distribution of π and σ bonding of diamond-like carbon films is investigated. It is shown that, although the selection of the integration windows can lead to very large variations in the resultant bonding fractions, the placement of two small windows centred on the edge structures of interest does permit a robust and reliable estimate of bonding. It is demonstrated that the sp3 variations can be reproducibly monitored with a relative accuracy of about ± 5%, and an absolute concentration given with an accuracy of ± 13% for foils of thickness at least up to twice the inelastic mean free path.

SUMMARY Internal interfaces determine the macroscopic mechanical and electronic properties of materials. Their investigation is therefore essential for an understanding of the relationship between microstructure and the materials properties. Besides the atomic structure, the bonding and electronic structure on an atomic scale are of interest. This information is contained in the interface-sensitive component of the electron energy-loss near-edge structure (ELNES). It can be extracted by the spatial difference method. Such spectra have already been interpreted with respect to the bonding and the local atomic environment of the atoms at the interface. Here we assess critically the application of the spatial difference for the investigation of internal interfaces. The method is subjective because a suitable scaling factor has to be chosen. As a guideline we propose to minimize the number of turning points in the difference spectrum. With this hypothesis we successfully determine the ELNES arising from atoms at two internal interfaces between a metal and a ceramic. This reveals qualitatively which type of bonding is present at the interface and quantitatively how many atoms are involved in it.