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All materials and devices tend to degrade with time. For this reason, reliability physics is of great theoretical and practical importance. Reliability investigations generally start with measuring the degradation rate for a material/device under stress and then a modeling of the time-to-failure versus the applied stress. The term stress, as used here, is very general: stress will refer to any external agent (electrical, mechanical, chemical, thermal, electrochemical, etc.) that is capable of producing material/device degradation. Time-to-failure occurs when the amount of degradation reaches some critical threshold level. Since devices often require different levels of degradation to induce failure, time-to-failure becomes statistical in nature and two common failure distributions are discussed: Weibull and Lognormal. Time-to-failure (TF) modeling generally assumes either a power law or exponential stress-dependence with either an Arrhenius or Eyring-like activation energy. From these TF models, acceleration factors can be deduced and these tend to serve as the foundation for accelerated testing. During this presentation, several semiconductor failure mechanisms will be reviewed: Electromigration (EM), Stress Migration (SM), Time-Dependent Dielectric Breakdown (TDDB), Hot-Carrier Injection (HCI), Negative-Biased Temperature Instability (NBTI), Plasma-Induced Damage (PID), Single-Event Upsets (SEU), Surface Inversion, Thermal Cycling Fatigue, and Corrosion. This tutorial should provide the attendee with a solid foundation for a better understanding of the papers presented at the IRPS.

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (

A molecular physics-based complementary model, which includes both field and current, is introduced to help resolve the E versus 1/E-model controversy that has existed for many years as to the true physics behind time-dependent dielectric breakdown (TDDB). It is shown here that either TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths 3 eV, the bond breakage must be hole catalyzed by current-induced hole injection and capture. Under these conditions, the TDDB physics is described well by the 1/E model.

The underlying physics behind the success of the thermochemical E model in describing time-dependent dielectric breakdown (TDDB) in SiO2 thin films is presented. Weak bonding states can be broken by thermal means due to the strong dipolar coupling of intrinsic defect states with the local electric field in the dielectric. This dipole-field coupling serves to lower the activation energy required for thermal bond-breakage and accelerates the dielectric degradation process. A temperature-independent field acceleration parameter γ and a field-independent activation energy ΔH can result when different types of disturbed bonding states are mixed during TDDB testing of SiO2 thin films. While γ for each defect type alone has the expected 1/T dependence and ΔH shows a linear decrease with electric field, a nearly temperature-independent γ and a field-independent ΔH can result when two or more types of disturbed bonding states are mixed. The good agreement between long-term TDDB data and the thermochemical model su...

For a collection of devices, it is critically important to be able to understand the expected failure rate for the devices. For the supplier of such devices, the expected failure rate will be an important indicator of future warranty liability. For the customer, the expected failure rate will be an important indicator of future satisfaction. For mission-critical applications, it is of paramount importance for one to know that the expected failure rate will be extremely low.

Advanced microelectronics interconnect systems can have metal leads several hundred meters long with minimum metal to metal spacing of

Time-dependent dielectric breakdown (TDDB) of low-k dielectrics is reported for fully integrated carbon-doped silica dielectric (SiOC, keff=2.9) at wafer level over a wide range of area and electric-field test conditions at 105degC. In addition, long-term package level TDDB data were taken at 105degC for over 2 years on integrated comb-serpent test structures. The field acceleration parameter (gamma=4.5 plusmn 0.5 cm/MV) was found to be approximately independent of area (over 4 decades of area) and over a wide range of field (1.5-6.0 MV/cm), respectively. TDDB data, taken over long periods, agree well with predictions based on more rapid wafer-level TDDB testing. The low-k TDDB data suggest that, while the time-to-failure is a strong function of area and field, the time-to-failure physics does not vary greatly for fully integrated SiOC films as both the area and field are scaled. Furthermore, the fact that gamma is approximately constant (independent of area and applied E-field) indicates that silica-based low-k dielectric TDDB follows closely a thermochemical E-model for all areas and fields examined.

Using a generalized Mie-Gruneisen bonding potential, a quantum mechanical treatment (WKB method) for Si-O bond breakage in silica is presented under the conditions of high electric field, hole injection and hydrogen release. The full spectrum of bound-state energy eigenvalues is used to calculate the transmission probability whereby bond breakage occurs when the Si-ion goes from 4-fold to 3-fold coordination. When this full spectrum of bound-state energy eigenvalues is considered, it is shown that, due to the mass of the Si-ion and the width of the potential energy barrier separating the 4-fold and 3-fold coordinated bonding positions, the tunneling probability is relatively small and thus the transmission probability is described well by thermionic emission. It is further shown that stretched bonds, hole capture and hydrogen release can all have a significant impact on the barrier height and thus greatly impact the transmission probability.

Extensive time-dependent dielectric breakdown (TDDB) data were taken for several silica-based low-k interconnect dielectrics so that the full statistical-distribution for the field acceleration parameter (gamma) could be determined. The low-k materials tested during this study included: SiOF (k=3.6), SiOCl (k=2.9), SiOC2 (k=2.6) and MSQ (k=2.3). While a strong material-dependence was found for the breakdown strength and time-to-failure, all of these silica-based materials tested at 105degC were observed to have a similar field acceleration parameter of gamma = 4.13 +/- 0.85 cm/MV

Future CMOS technology generations may implement multi-gate architectures according to S. M. Kim et al. (2004), D Ha et al. (2004), S.-Y. Kim et al. (2005), W.-S. Liao et al. (2005), S. Maeda et al. (2004), N. Collaert et al. (2005),and C. Jahan et al. (2005), together with a change from SiO2-based to high-k gate dielectrics and a change from poly-silicon to metal gate. The purpose of this work is to identify the influences of multi-gate architecture and metal gate on gate dielectric reliability and to demonstrate the dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric

The shrinking of line-to-line spacing in interconnect systems for advanced IC technology and the use of new lower dielectric constant materials create the need for tools to evaluate the interconnect dielectric reliability. A multi-temperature, dual ramp-rate voltage-ramp to breakdown methodology is presented and used here to extract important dielectric breakdown parameters accurately for minimum spaced metal-lines. It is demonstrated that correction for the true minimum line-to-line spacing distributions become critically important and that the minimum spacing can be extracted electrically and compares favorably to electron microscopy cross sections. The spacing-corrected breakdown field distributions, at various temperatures, for the organo-silicate materials tested, indicated a very low apparent zero-field activation energy (0.14/spl plusmn/0.02 eV) and an apparent field acceleration parameter /spl gamma/ = 4.1/spl plusmn/0.3 cm/MV that has little or no temperature dependence. Constant-voltage time-dependent-dielectric-breakdown (TDDB) measurements were found to agree well with these observations.

Charge trapping in HfSiON and HfO/sub 2/ gate dielectrics was studied using both DC and pulsed I/sub D/-V/sub G/ characterization techniques. The data shows a significant amount of hysteresis in HfO/sub 2/ but negligible instability in HfSiON. Constant voltage stress measurements of HfO/sub 2/ and HfSiON films show that the threshold voltage shift in HfO/sub 2/ films is as much as 10 times higher than that of HfSiON. Further, modeling of the time dependence of the threshold voltage shows that the trap capture cross section responsible for the instability of HfO/sub 2/ films is 10 times higher than the trap capture cross section of HfSiON. Our data indicate that amorphous HfSiON has better electrical stability than HfO/sub 2/.

Electrical instability due to charge trapping in high-k materials is a primary concern for the usefulness of these films in future CMOS devices. This paper reports the effect of charge trapping on the threshold voltage and transistor drive current of devices made with HfSiON gate dielectric. Our results show that the physics of the charge trapping in HfSiON is unique and follows logarithmic dependence with time rather than usual exponential dependence. NMOS devices fabricated with HfSiON films show acceptable electrical stability for 10 years without substantial degradation of either the threshold voltage or the drive current.

The reliability physics of low-k interconnect dielectrics is of great interest. Leakage, breakdown and TDDB data are presented for fluorinated silica, porous carbon-doped silica, and very porous carbon-doped silica. The breakdown and TDDB performance of the dielectrics are observed to degrade with the degree of porosity but the failure kinetics (field acceleration parameter and activation energy) seem to rather insensitive to porosity. A percolation model has been developed whereby the pores are treated as defects. The percolation model seems to describe well the observed breakdown and TDDB behavior.

Dielectrics with high dielectric constant k will likely be required for future replacement of conventional SiO/sub 2/ gate dielectric. Physical models are needed which describe the reliability tradeoffs associated with the high-k material selection. In this paper we report on a fundamental relationship existing between the dielectric breakdown E/sub bd/ and dielectric constant k. An approximate E/sub bd/ /spl sim/ (k )/sup -1/2/ relation is found and seems to be universal, i.e., the relation holds over nearly two decades of dielectric constant. A physics-based model has been developed to understand this critically important relationship. The good fit of the physical model (with no adjustable parameters) to the experimental data suggests that the local electric field (Lorentz-relation/Mossotti-field) in these high-k materials plays a very important role in the observed E/sub bd/ /spl sim/ (k)/sup -1/2/ behavior. The very high local electric field (in high-k materials) tends to distort/weaken polar molecular-bonds thereby lowering the enthalpy of activation required for bond breakage by standard Boltzmann processes.

Stress-induced voiding is observed in Cu-based, deep-submicron, dual-damascene technologies where voids are formed under the via when the via connects to a wide metal lead below it. The voiding results from the supersaturation of vacancies that develops due to grain growth when the Cu is not properly annealed prior to being fully constrained. The driving force for voiding is shown to be stress migration with a maximum in voiding rate observed at /spl sim/190/spl deg/C. A diffusional model is presented which shows that the voiding mechanism is an issue primarily for vias connected to wide Cu leads. A thermomechanical stress exponent of 3.2 and a diffusional activation energy of 0.74 eV were determined for this stress-induced voiding mechanism.

Switched polarization fatigue was investigated for CVD PZT ferroelectric films of thickness

The susceptibility to chlorine-induced corrosion of Al-Cu and Al-Cu-Si films has been measured. The adverse impact of Cu on the corrosion susceptibility of unsintered films is clearly evident at 0.3% and increases sharply between 1.0% and 2.0% with the latter being 6 times more corrosive than the former. Adding 1.0% Si to the Al-Cu (2%) alloys tends to lower the corrosion susceptibility of unannealed films by a factor of 9. This effect is shown to be caused by higher quality native aluminum oxide resulting in a delay in the onset of the corrosion rather than a slower rate once corrosion has begun. Annealing (30 min at 450 degrees C) the copper containing films also has a beneficial effect on corrosion susceptibility. >

Alternate gate-dielectric films are required for future replacement of conventional SiO/sub 2/. Replacement is needed to reduce gate-leakage while still maintaining good reliability and a high-level of transistor performance. One such candidate is HfSiON dielectric film. In this paper we report for the first time, IV and CV characteristics, stability and reliability results for amorphous HfSiON dielectric films scaled below 13 /spl Aring/. Our results show that leakage current through this material is reduced by two orders of magnitude versus an equivalent SiO/sub 2/ film, while the interface and TDDB stability remains good. The positive leakage, stability and reliability results indicate that HfSiON may be a suitable candidate for gate-oxide replacement in CMOS applications where an effective hyper-thin gate-oxide is required for performance reasons and a reduced gate-leakage for low-power applications.

Leakage and breakdown characteristics of low-k dielectrics are becoming increasingly important reliability issues for interconnects as they are scaled to 0.18 um and below. Several of the low-k dielectrics, integrated into a dual-damascene Cu process flow, are quite leaky and have difficulty in meeting a leakage spec of 1E-8 A/cm/sup 2/ at 25/spl deg/C. Time-dependent dielectric breakdown (TDDB) for some of the low-k candidate films is also an issue because of generally low breakdown strengths

A temperature-independent field acceleration parameter /spl gamma/ and a field-independent activation energy /spl Delta/Ho can result when different types of disturbed bonding states are mixed during time-dependent dielectric breakdown (TDDB) testing of SiO/sub 2/ thin films. While /spl gamma/ for each defect type alone has the expected 1/T dependence and /spl Delta/Ho shows a linear decrease with electric field, a nearly temperature-independent /spl gamma/ and a field-independent /spl Delta/Ho can result when two or more disturbed bonding states are mixed. These observations suggest strongly that the oxygen vacancy is an important intrinsic defect for breakdown and that field, not current, is the cause of TDDB under low-field conditions.

The system soft error rate (SSER) of 4M/16M DRAMs has been shown to be dependent on the cosmic ray neutron flux. A simple model and accelerated soft error rate (ASER) measurements made with an intense, high energy neutron beam support this result. The model predicts that cosmic ray neutron induced soft errors will become important at the 64M DRAM generation and beyond.

The electromigration (Er) performance of layered Al-0.5%Cu and Al-1%Si-0.5%Cu metallization systems was investigated, including leads with refractory barrier and capping layers, and tungsten-filled via holes. While the W-plugs exhibited a lifetime shorter than the leads, a dramatic improvement in EM performance of the vias was achieved by incorporating a thin layer of titanium between the aluminum and its cap. Among the most likely explanations for this observation is that the aluminum is protected from physical damage during via etch by the continuous TiAl/sub 3/ layer which forms by reaction between the titanium and the aluminum. Current flow simulations show complex crowding effects at the bottom of the vias. The role of grain boundaries and the effects of dopants on early via failure modes are also discussed. >

Electromigration performance is investigated for Al-Si(1%)-Cu(0.5%) alloy on a CVD-W or Ti:W barrier layer, and the effectiveness of a Ti:W capping layer to suppress electromigration is explored. Compared to a Ti:W barrier layer, the surface roughness of the CVD-W barrier layer degrades electromigration performance, however, a capping layer of Ti:W sequentially sputtered on top of the aluminum-alloy will substantively improve the electromigration performance when either barrier layer system is used. The improvement is observed to increase with the thickness of the Ti:W capping layer. Investigations of the failure kinetics and material properties indicate the EM performance improvement is primarily due to changes in the Al-alloy micro-structure.© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The results of a study using DC polarization techniques are explained on the basis of the galvanic couple formed between the metallization and the barrier layer, as well as the difference between the surface topographies of CVD W and sputtered W-Ti (10%). A galvanic series developed for several couples was used to compare materials that exhibited a strong tendency to corrode, or were more anodic, to those which did not, or were more noble. Although the galvanic series revealed that the CVD W and sputtered W-Ti (10%) barrier metals were more noble than Al, polarization scans demonstrated that the Al and the W-Ti (10%) barrier layers exhibited passive behavior and were not as susceptible to corrosion because of the protection afforded by a protective oxide layer. In addition, the corrosion rate was enhanced by the increased cathodic surface area afforded by the CVD W, which acted as an efficient cathode. Immersion tests substantiated these results. >

The AC electromigration of multilayered interconnect systems consisting of TiW-AlSiCu and CVD W-AlSiCu is studied under stress of repetitive dual-pulse current waveforms at 2 MHz. By using a general AC waveform in which the peak current density of the first pulse j/sub 1/ is fixed and the second is varied from +j/sub 1/ to -j/sub 1/, a continuous electromigration spectrum from DC through pulsed DC to pure AC conditions is obtained. Although an average current model fits the data well, there is a singularity in the median time-to-failure at pure-AC conditions. To avoid this singularity, a modification of the average current model, called the average current recovery model, is developed. It heuristically accounts for the degree of damage recovery during opposite-polarity pulses through a single recovery parameter. >

The shrinking line-to-line spacing in interconnect systems for advanced integrated circuit technology and the use of lower dielectric constant materials create the need for tools to evaluate the interconnect dielectric reliability. A multi-temperature, dual-ramp-rate voltage-ramp-to-breakdown methodology is presented and used here to extract important dielectric-breakdown parameters accurately for minimum-spaced metal lines. It is demonstrated that correction for the true minimum line-to-line spacing distributions become critically important and that the minimum spacing can be extracted electrically and compares favorably to electron microscopy cross sections. The spacing-corrected breakdown field distributions, at various temperatures, for the organosilicate material tested, indicated a very low apparent zero-field activation energy (0.14±0.02eV) and an apparent field-acceleration parameter γ=4.1±0.3cm∕MV that has little or no temperature dependence. Constant-voltage time-dependent-dielectric-breakdown m...

Analyse de donnees de disruption electrique en fonction du temps concernant des couches minces SiO 2 de 100 A d'epaisseur, en utilisant un modele d'Eyring

Time dependent dielectric breakdown (TDDB) data for 100A of thermally grown SiO2 has been analyzed using an Eyring model based on thermodynamic free energy considerations. The model describes well the following features of the data: (1) an apparent activation energy which is a function of the stressing electric field and (2) a field acceleration parameter that is a function of temperature. Quantitatively, the model suggests the proper field dependence for the activation energy and the observed temperature dependence of the field acceleration in the 100A oxide material. The apparent activation energy is found to decrease from > leV at low field stressing (Eb(50%) - Es > 5 MV/cm) to

Plastic package thermal resistance reductions of 50% were achieved by leadframe attachment to a novel SiC/graphite composite heatspreader prior to the plastic molding operation of silicon chips. As determined by extended high temperature operational life-tests on special VLSI chips dissipating 0.5 watt, the heatspreader resulted in a 2x improvement in chip lifetime for a wearout mechanism such as electromigration. In addition, Arrhenius extrapolations of instrinsic failure rates to 35°C ambient conditions indicate that an increase in reliability occurs (lower failure rate) of 2x, 4x, and 8x for chips consuming 0.5 watts, 1.0 watts, and 2.0 watts, respectively. Standard environmental lifetests such as biased humidity, autoclave, high temperature storage, and temperature cycling were conducted with favorable results reported.

Due to recent reports of stress-dependent activation energy, a generalized Eyring model has been developed in order to better understand thermally activated failure mechanisms. The model predicts a stress-dependent activation energy provided two necessary requirements are satisfied: (1) the applied stress must be the same order of magnitude as the strength of the material and (2) the stress acceleration parameter ? must be a function of the temperature. This model has been successfully applied to diverse failure mechanisms such as: dielectric breakdown under electric-field stress, metal failure under mechanical stress, and electromigration failure under current density stress. Application of model to the specific case of electromigration suggests that the current density exponent N for failure is not a unique value but increases with current density from N=1 at J ? 1 × 105 A/cm2 to N?2 at J ? 1 × 106 A/cm2.

The failure kinetics for both titanium silicided and non-silicided contacts are discussed for Al-Si (1%) metallization. The activation energies for accumulation of silicon in silicided and non-silicided contacts as well as the depletion of silicon from non-silicided contacts were found to correspond to diffusion of silicon in aluminum, 0.8 to 0.9 eV. The dependence of the reaction rate on current was found to vary with the level of applied stress. Depletion related leakage failures for TiSi2 contacts proceed at a much slower rate than the depletion of silicon from contacts to silicon and an activation energy of 1.5 eV was observed.

The laser blowing of MoSi2/Poly-n + fuse links is reported. The polycide links were successfully blown under 10K A of PSG (phospho silicate glass used for isolation between the link and the aluminum) at laser power levels comparable to those used for standard poly link vaporization. Also, the size of the crater in the PSG, produced by the expanding gases associated with link vaporization, was found to be less than that for standard poly links. Laser power levels were found which gave both a near unity blowing probability and produced no substrate damage when the link was located on top of 7-10K A of field oxide. The successful blowing of silicide links is very important with respect to the use of both laser redundancy and silicides in VLSI technology.© (1983) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We report on the reliability properties of a high-density ferroelectric memory based on a 70nm thick MOCVD PZT process technology. We observe that the polycrystalline texture plays an important role in the electrical and reliability properties of these thin films. Data retention loss is primarily due to the imprint effect, which shows a 1.5eV "Time-to-Fail" activation energy. Good correlation is observed between stand alone test capacitors and memory arrays integrated into a 130nm, 5LM, Cu/FSG logic CMOS process. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ read/write cycles.