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This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

In this work, the X-ray irradiation impact on the back gate conduction and drain current for Triple-Gate SOI FinFETs is investigated for strained and unstrained devices. Both types (P and N) of transistors were analyzed. Since X-rays promote trapped positive charges in the buried oxide, the second interface threshold voltage shifts to lower gate voltage. The performance of n-channel devices presented a strong degradation when submitted to X-rays, while for p-channel devices the opposite trend was observed. Two different dose rates were analyzed.

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.

This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the reduced variation observed of the gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. Even with the larger mobility of the rotated nMuGFET devices when compared with the standard ones, the larger output conductance degradation resulted in an almost similar intrinsic voltage gain. P-channel devices, when implemented on the rotated layout, offer a lower intrinsic voltage gain.The GIDL current was also analyzed on these devices, indicating to be larger in thinner metal gate and rotated configuration.

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

In this work, a simple model that accounts for the variation of electron mobility as a function of the silicondielectric interface crystallographic orientation is presented. Simulations were conducted in order to compute the effective mobility of planar devices and its results were compared to experimental data for several interface orientations. The error between experimental data and the proposed model remained bellow 4%. The model has been applied to nMOS circular surrounding gate (thin-pillar transistor - CYNTHIA) and allowed the observation of current density variations as a function of the interface orientation around the silicon pillar.

This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.

The influence of Selective Epitaxial Growth (SEG) and the Uniaxial and Biaxial Strain are studied in triple gate FinFETs, analyzing the Drain Induced Barrier Lowering Effect (DIBL). The splits using SEG present better performance for strained devices than the unstrained ones but the inverse is observed for devices without SEG. The DIBL values are higher for SEG devices in all cases. For devices without SEG, the effect of mechanical stress is more pronounced and the mobility is higher in the uniaxially strained devices. These devices have lower VT values in the saturation condition causing the highest DIBL.

The theoretical and experimental study of drain leakage current behavior in Graded-Channel ( GC ) SOI nMOSFETs operating at high-temperatures ( up to 300oC ) is analyzed and discussed here. Through the studies it was noticed that drain leakage current depends strongly on the ratio between the length of the lowly doped region and the mask channel length. Also, it was observed that the drain leakage behavior is similar to the conventional SOI nMOSFETs which effective channel length being equal in both structures when the GC SOI nMOSFETs has the same channel doping level in the higher doped region. Numerical bidimensional simulations and experimental data were used in order to compare and discuss all the results.

This work presents an experimental andThis work presents an experimental and simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation. simulated analysis of the Negative-Bias-Temperature-Instability (NBTI) on omega-gate nanowire (NW) pMOSFETS transistors, focusing on the influence of channel length and width, since it is an important reliability parameter for advanced technology nodes. To better understand the obtained results of NBTI effect in NW, the 3D-numerical simulations were performed. The results shows a high NBTI in NW (ΔVT≈200-300mV – for WNW=10nm) due to the higher gate oxide electric field accelerating the NBTI effect providing a higher degradation.

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

The Back Enhance (BE) SOI MOSFET is a device whose operation can be tuned by the back gate bias (VGB), i.e., it can act as an n- or p-type MOSFET if VGB is positive or negative enough, respectively. This characteristic was explored in the bio-sensing application, in which a charge-based sensor was studied through simulation. Physical dimensions (gate and underlap lengths, gate oxide, silicon and buried oxide thicknesses) were varied in order to determine the most sensitive case. The buried oxide thickness presented highest variation in the results, showing the importance of the substrate on its operation. The biomaterial charge concentration analysis showed a better sensitivity of the device for positive charges when biased as an n-type transistor, while the p-type bias presented better sensitivity to negative charges. Thus, the versatility of the BESOI MOSFET can be used as an advantage in the field of biosensors.

In this work, a simple methodology is proposed to simulate the current mirror circuit based on the triple-gate SOI FinFET experimental data, before and after proton-irradiation. The method is called lookup table in Verilog-A, consisting of a detailed experimental characterization of the device aiming the construction of lookup table with the data to be used in simulations, once the device do not have an accurate first order analytic model (1-4). Even though the SOI technology provides significant immunity to single-event phenomena when compared to bulk transistors, the radiation effect still have to be considered because the trapped charges in the buried oxide (BOX) degrades the transistor characteristics due to the higher Total Ionization Dose (TID) (5-9). The studied devices are p- and n-type triple-gate SOI FinFETs fabricated in imec, Belgium. They were processed on SOI substrates with a thick buried oxide (tBOX) of 150 nm. The gate dielectric of the devices consists of 2 nm HfSiON on 1 nm SiO2 interfacial layer, resulting in an Equivalent Oxide Thickness (EOT) of 1.5 nm. The gate is 10 nm TiN covered by 100 nm poli-Si. The fin height (hFIN) is 65 nm, the channel length (L) is 150 nm and three different fin widths (WFIN) were evaluated: 20 nm, 120 nm and 870 nm. Each transistor has 5 fins in parallel. The proton irradiation has been performed at the Cyclone facility in Louvain-la-Neuve (Belgium) with the beam energy of 60 MeV up to fluence of 1012 p/cm2. Figure 1 shows the experimental drain current (IDS) as a function of the front gate voltage (VGF) for different fin widths before and after the radiation. It is possible to notice that although narrow devices (WFIN=20nm) showed to be almost immune to proton irradiation due to a higher coupling between gates, the wider devices presents a degradation on subthreshold swing (SS) for n-FinFETs while for p-FinFET the SS improves. The reason is that the radiation induces positive charges in the buried oxide, resulting in a reduction of the threshold voltage at the back interface (Vth2), which is good for p-FinFET and bad for n-FinFET, as explained in (8-10), Figure 2 shows the drain current (IDS) as a function of the drain voltage (VDS) for different fin widths before and after the radiation, for simulated and experimental data. It shows that the simulation values accurately fit the experimental data. Some important figures-of-merit of analog performance for circuit applications should also be evaluated, such as transistor efficiency (gm/IDS) and the intrinsic voltage gain (Av). Figure 3 shows that the n-FinFETs presents a degradation of the transistor efficiency (except for narrow fin) after radiation since the weak inversion region is inversely proportional to SS. For p-FinFETs after radiation, the opposite behavior of gm/IDS was obtained once SS improves. At the strong inversion region, there is only a slightly variation of the transistor efficiency due to mobility degradation. From figure 4 it is possible to observe that the radiation causes an improvement of intrinsic voltage gain (Av = gm/IDS x VEA) for p-FinFETs and a degradation for n-FinFETs, for all inversion conditions, following the gm/IDS tendency. It is also expected that narrow devices present higher gain due to the higher VEA, caused by the better coupling between gates, for both types of transistor. The evaluated current mirror circuit regarding the behavior with different loads (VLOAD) is schematic represented in Figure 5. Figure 6 presents the relation between drain currents (ILOAD/IREF) as a function of the VLOAD before and after the circuit be submitted to proton irradiation. For this analysis, the perfect matching situation, i.e. drain current ratio of 1, was obtained for |VGS=1V| for both devices types before radiation. From the insets of figure 6 it is possible to visualize that after radiation, the perfect matching situation presents a slightly variation and is obtained for a more negative VGS bias, for both types, due to the threshold voltage (VT) change (promoted by the Vth2 reduction). In addition, from figure 6 it can also be noticed the influence of VEA on VLOAD at the operation region of the current mirror, which results in a maximum current variation smaller than 10 percent, even for radiated current mirrors. Beside the matching situation, it is also possible to notice that narrow transistors present a higher compliance voltage even for radiated devices due to the better coupling between gates and consequently the immunity to the buried oxide charges. Figure 1

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2). The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm. The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5). It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart. In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC. The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2). The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av. As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length. Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively. Figure 1

Made available in DSpace on 2022-04-28T19:41:36Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-12-01 An Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed that, when the IG is negligible, there is a trade-off between the DC open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si NW MOSFET OTA presented the lowest AV0 (52 dB) but the largest GBW (9.5 MHz). The largest gain was obtained by the Si NW TFET (97 dB) but it also presents the lowest GBW (30 kHz). The SiGe-source TFET stands in the middle, with an AV0 of 88 dB and a GBW of 715 kHz. However, when IG is not negligible and included in the model, the gain of the TFET OTAs decreases considerably, down to 38.3 dB in the case of the Si TFET and down to 52.6 dB in the case of the SiGe-source TFET. This decrease in gain is mostly caused by an alteration in the desired bias point in the second stage of the OTA due to the change of the output voltage and bias currents. This issue possibly can be mitigated by using circuit design strategies. Nevertheless, the SiGe-source TFET OTA is less impacted by the gate current than the Si TFET OTA and still presents a larger gain than the Si NW MOS OTA (52.6 dB against 50 dB) when the IG is considered. LSI/PSI/USP University of Sao Paulo UNESP Sao Paulo State University Imec ClaRoo E.E. Dept KU Leuven UNESP Sao Paulo State University

Made available in DSpace on 2022-04-28T19:40:54Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-10-01 The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz. Imec, Kapeldreef 75 Universidade Tecnológica Federal do Paraná UNESP Sao Paulo State University LSI/PSI/USP University of Sao Paulo EE Depart. KU Leuven, Kasteelpark Arenberg 10 UNESP Sao Paulo State University

This paper presents the design of an Operational Transconductance Amplifier (OTA) with Gate-All-Around Nanosheet MOSFETs (GAA-NSH). The circuit simulation was performed using an experimental Lookup Table (LUT) approach. The experimental drain current and gate capacitance were extracted and used in a Verilog-A model in order to design the OTA for different transistor efficiency (gm/ID) values. The results present a compromise between power consumption (PC), voltage gain (AV) and the Gain-Bandwidth-Product (GBW). For gm/ID of 8 V-1 an AV of 71.8 dB is obtained for a GBW of 361.3 MHz. These results were compared with other OTA designs using FinFET and TFET devices. The NSH OTA presents higher GBW, and considering the Av and PC, while NSH present better behavior than FinFETs, the behavior is worse than TFET OTA circuit for strong inversion operation.

This work presents an experimental analysis of the trade-off between transistor efficiency (gm/I D ) and unit gain frequency (f T ) of nanosheet field effect transistors (NSFETs) with different metal gate (MG) stack, considering the influence of high temperature (T), until T=200 °C. The results are very promising for both MG stacks. The MG stack (n*) presents a high f T about 260 GHz (T=25 °C and L=28 nm) and a gm/I D about 37 V-1 (T=25 °C and L=200 nm). The MG stack (m*) also presents very good characteristics, like a f T about 252 GHz (T=25 °C and L=28 nm) and a gm/I D about 35 V-1 (T=25 °C and L=200 nm). From the analyses as a function of the inversion coefficient (IC), it was possible to determine that the optimal operation point occurs in the transition from moderate to strong inversion for L=28 nm and it is in strong inversion for long channel devices. In all cases, although the intrinsic voltage gain (A V ) is degraded moving away from weak inversion, the degradation was not very pronounced up to the optimal operation point and considering the temperature variation, the A V presents a greater stability at the optimal point than in weak inversion.

Made available in DSpace on 2022-04-28T19:42:42Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-09-01 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Current mirrors (CMs) are essential building blocks for biasing integrated circuits. The gate-all-around silicon nanosheet MOSFETs (GAA-NS) are excellent candidates for the sub 7 nm technology node. In this work, CMs designed with GAA-NS are studied for the first time. This study is performed from room temperature to 200 ◦C using Verilog-A with Look Up Table based on experimental data of n- and p-type GAA-NS for circuit simulation. The current source (reference current) that supplies the CM is designed with an inverter with feedback for simplicity. Due to the zero temperature coefficient (ZTC) region, multiple designs are made to evaluate each type of biasing (before, after and in the ZTC region). Symmetric and asymmetric VTH for n- and p-type GAA-NS are also analyzed. The asymmetric approach presents a compliance voltage of 0.7 V and 0.8 V, for an n- and p-mirror, respectively, while the symmetric one yields a compliance voltage of 0.75 V for both mirror types, and errors lower than 6%, for the design biasing the transistors before the ZTC region. LSI/PSI/USP University of Sao Paulo Imec UNESP Sao Paulo State University UNESP Sao Paulo State University

The study of a dielectric-modulated biosensor built on the BESOI MOSFET structure showed a crossing point of the transfer characteristics curves for target biomaterials with different dielectric constants (CID – Current Invariant Dielectric). The CID corresponds to an insensitive region for biosensing application, although it can be interesting as a reference signal measurement. It was evaluated that this behavior arises from the threshold shift and the transconductance increase as a function of the biomaterial dielectric constant. The gate voltage at the crossing point presented higher variation as a function of the metal gate-semiconductor workfunction difference, when compared to the influence of the programming gate voltage and the gate oxide charge concentration.

This work presents a trade-off analysis between transistor efficiency (gm/I D which is proportional to the intrinsic voltage gain A v ) and the unit gain frequency (f T ) of the nanosheet (NSH) NMOS devices. The analyses were performed experimentally as a function of the inversion coefficient (weak, moderate, or strong inversion levels-IC) in order to determine the best operation region for optimization of both parameters. These analyses were performed with NSH NMOS for the channel length ranging from 28 nm to 200 nm. It was observed that the optimal operation point takes place in the transition between moderate and strong inversion (IC=10), where the highest value obtained for gm/I D x f T was found. In this optimum bias point the A V is 50 dB (L=200 nm) and 37 dB (L=28 nm) and f T is 7 GHz (L=200nm) and 160 GHz (L=28nm), which should be suitable for many applications.

In this work, an improvement of Schottky junction was performed for application in Back Enhanced BESOI MOSFET. It was observed that the formation of NiSi prior to the deposition of the aluminum on it, protects the Schottky junction from the aluminum interaction with Ni during thermal treatment. As a result, the Schottky junction obtained with this new process fabrication presents a better electrical behavior with ideality factor, n, close to 1 (n = 1.02 for Werner method and n = 0.95 for Gromov method) and Schottky barrier height, Φ b = 0.42 eV.

Made available in DSpace on 2022-04-28T19:44:05Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-08-23 Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) — In this work we further investigate the operation of theBESOI (Back-Enhanced Silicon-On Insulator) Dual-Technology FET, analyzing not only its behavior as a p-type Tunnel-FET when a negative back bias is applied to the struc-ture, but also as an nMOS when a positive back bias is applied. The working principle is based on the generation of a channel of either holes or electrons by the back gate electric field, which can then be depleted through the front gate bias. TCAD device simulation was used for the proof of concept. LSI/PSI/USP University of Sao Paulo UNESP Sao Paulo State University UNESP Sao Paulo State University CAPES: 2017/26489-7 CNPq: 2017/26489-7 FAPESP: 2017/26489-7

This paper presents the DC design of a differential amplifier, an important building block on analog and mixed signal designs, utilizing the Verilog-A approach on Gate-All-Around Nanosheet (GAA-NSH) devices. The GAA-NSH is a device with two stacked silicon sheets in which the gate fully surrounds the channel, presenting the best electrostatic coupling possible for MOS technologies. The device has a 104nm effective width while having a physical width of only 15nm. The differential amplifier was designed with a V DD of 2.1V and input common mode of 1.4V, while biased in different inversion regions with gm/I D values of 5 V-1, 8 V-1 and 11 V-1. The gm/I D = 8V-1 project was compared against a FinFET differential amplifier project, showing an improvement of gain and transconductance while occupying less physical area. Higher efficiency projects (gm/I D = 11 V-1) present a higher gain while decreasing current consumption.

This paper reports the study of the Back Enhanced SOI (BESOI) MOSFET improvement through the inclusion of ndoped regions on the drain and source regions underlapped with the gate. This study was performed using TCAD Synopsys Sentaurus simulator. The main characteristic of the original BESOI MOSFET is the reconfigurable behavior, depending on the back-gate bias (V GB ) the device can act as a p- or n-type transistor. However, the I on current is typically asymmetric. The proposed new structure by adding n-doped regions improves the drain current when the new BESOI is in the n-type BESOI configuration, which may take both transistor types to the same current level. The best results to L MP = 1 μm was obtained for V GB = |30| V, mainly when the transistor is in the triode region.

The quantum effect on the Gate-All-Around Nanosheet (GAA NS) NMOS devices are studied in this paper from 200°C down to -100°C. The experimental results for different channel lengths (down to 28 nm) are used from 200°C to room temperature and the behavior down to -100°C is extrapolated using calibrated TCAD simulation. The quantum confinement is present in all devices, but only for the h = 5nm case its contribution for the threshold voltage increase is more relevant. This increment is constant with the temperature, but it becomes proportionally more important for higher temperatures due to the VT decrease in such conditions. The subthreshold swing is not affected by the quantum model and its value is close to (kT/q)ln(10) in all cases, with the best results obtained for the lowest device height.

Made available in DSpace on 2022-04-28T17:20:13Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-07-01 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) The analysis of vertically stacked nanosheet (NS) n-type transistors with two different metal gate-stacks (with a total thickness of 7.5 and 4.7 nm) is presented in this work from room temperature to 200 degrees C. The focus in this work is on the classical analog figures of merit (FoM). In all NS devices, superior performance is observed that is confirmed by the subthreshold swing variation with temperature, which is very close to the theoretical thermal limit. The Al-based (n*) gate-stack NS n-channel NS field effect transistors (NSFETs) in general present higher transconductance, transistor efficiency, early voltage, and intrinsic voltage gain (A(V)) thanks to the better electrostatic coupling between the gates and the silicon NSs. An A(V) of about 47 dB (gate-stack (n*), L = 200 nm, 200 degrees C) is obtained. The low-frequency noise analysis demonstrates the presence of flicker noise dominated by carrier number fluctuations as the main type of noise and presents a low current noise power spectral density Sid of 10(-19) A(2)/Hz at a drain current of 1 mu A and a drain voltage of 50 mV for a frequency of 10 Hz. Univ Sao Paulo, BR-05508010 Sao Paulo, Brazil IMEC, B-3001 Leuven, Belgium Univ Sao Paulo, PSI Elect Syst Engn Dept, BR-05508010 Sao Paulo, Brazil Sao Paulo State Univ, Dept Elect & Telecommun Engn, BR-13876750 Sao Joao Da Boa Vista, Brazil Sao Paulo State Univ, Dept Elect & Telecommun Engn, BR-13876750 Sao Joao Da Boa Vista, Brazil

Made available in DSpace on 2019-10-06T15:38:16Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-09-01 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) This paper reports an improved method for estimating the thermal resistance of a MOSFET device using the inverse of the transistor efficiency as a function of the power applied to the transistor's channel. This method was deduced considering that the main effect of the self-heating is on the carriers’ mobility, where the temperature dependency, vertical/lateral field degradation and saturation velocity were taken into account. After performing the analytical considerations, the method was validated through numerical simulations to verify if its results were compatible with other traditional pulsed-like method for the thermal resistance extraction. This improved method was applied experimentally to attest its robustness. The advantages of this method are the use of DC measurements only and differences smaller than 10 K in the estimation of the absolute channel temperature due to the self-heating effect compared to a traditional pulsed-like method for the UTBB SOI studied in this work. LSI/PSI/USP University of Sao Paulo, Sao Paulo Sao Paulo State University (UNESP), Sao Joao da Boa Vista Sao Paulo State University (UNESP), Sao Joao da Boa Vista

The implementation of a barrier potential layer underneath the channel region, well known as Ground Plane (GP) implantation, and its influence on the performance of relaxed germanium pFinFET devices is investigated in this manuscript. This study aims to explain the fin width dependence of the threshold voltage from experimental data and evaluates the ground plane doping concentration and its depth influence on relaxed p-type channel germanium FinFET parameters, as threshold voltage, transconductance and subthreshold swing, through Technology Computer-Aided Design (TCAD) numerical simulations. The threshold voltage variation reaches up to 80 mV from the narrowest device to the widest one, considering the studied range of ground plane doping concentration. Concerning the subthreshold swing parameter, neither the GP doping concentration, nor its depth play a significant role since the electrostatic coupling is predominant.

Made available in DSpace on 2019-10-06T15:56:00Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-01-01 The proposal of this work is to present an analysis of omega-shaped-gate silicon nanowire field-effect-transistors operating in the subthreshold region. It is analyzed three channel widths (WNW), 220, 40 and 10 nm. In the widest device is noted a back interface conduction that it was extrapolated through numerical simulations adding the positive fixed charges (Qox) and interface traps (Nit) at the interface between the channel and the buried oxide. While studying the effects of these charges, it is noticed that besides causing a threshold voltage (VT) shift it does not present a significant variation in the subthreshold swing (SS). Since the total ionizing dose can be simulated by adding Nit and Qox in the gate and buried oxides, this study is extended, aiming to analyze the impact of ionizing radiation in the subthreshold region of nanowire devices. The nanowires presents a high immunity in SS due to the supercoupling provided by the small silicon height (hfin), which is confirmed through the analysis of the surface electrostatic potential. The hfin increase results in a worst coupling and, the Nit and Qox degrades the SS while increasing WNW. For WNW = 10 nm even with hfin = 65 nm, no significant influence in SS is observed. LSI/PSI/USP University of Sao Paulo Sao Paulo State University (UNESP) Sao Paulo State University (UNESP)

In this paper, the sensitivity of the fringing field n-type tunneling field-effect transistor biosensor (Bio-nTFET) was investigated over the influence of positive fixed charges density (Q Bio ) and dielectric constant k, in the source underlap (L US ) region. Numerical simulations were performed using Sentaurus TCAD device simulator. The presence of different biomolecules, in the L US region, affects the drain current of the on-state (I On ). It is shown that the sensitivity of the Bio-nTFET increases 3 orders of magnitude from k = 1 to k = 10 due to the improved fringing field that reduces the tunneling length resulting in a higher tunneling current. The sensibility also increases for a higher values of Q Bio . The highest sensitivity value obtained in this work was 6.103 A/A for QBio = 1.1012 cm-2 and k = 10. The proposed device shows great potential as a biosensor based on TFET devices.

This paper shows an experimental analysis of the zero-temperature coefficient (ZTC) bias point of vertically stacked gate-all-around nanosheet pMOS devices (GAA-NS) for different channel lengths (L), in linear and saturation regions. The gate voltage at ZTC point (V ZTC ) experimental results are compared with the values obtained by analytical model (CM-ZTC model) in order to evaluate the behavior of the ZTC of the GAA-NS pMOS transistors. The comparison between the data from the CM-ZTC model and the experimental values resulted a difference smaller than 7% when operating in linear region, which means that the behavior of GAA-NS in ZTC point can be well described through the mobility degradation and threshold voltage shift basic models like in planar fully depleted SOI devices. However, in saturation region the difference increases substantially due to the high series resistance, and in case of 28 nm channel devices, due to the short-channel effect (SCE), which is not considered in the analytical model. But the experimental V ZTC in saturation region does not change too much (|V ZTZ | ≅ 0.75V with standard deviation ≅ 0.06V) for all studied devices (from 200 nm down to 28 nm channel lengths) which means that the GAA-NS is a trusted device for analog circuits biased at ZTC point.

This paper presents a simple analytical modelling of a Electronically Tunable Potentiometer (ETP) circuit, made of a pseudo-resistor pair and a feedback mechanism that keeps resistance invariant to common mode voltage. The modelling utilizes the first order quadratic equations for the MOS transistor. In order to validate the analytical model, a Verilog-A model was written using the same MOS equations, and later matched to the ibm 130nm technology node resulting in a satisfactory approximation, with relative errors within 15%. Analysis of the ETP control voltage, pseudo-resistor current and pseudo-resistor resistance using the simple model were performed as a function of body factor. When the body factor decreases (better gate to channel electrostatic coupling) the pseudo-resistance increases for the same silicon chip area.

In this work, the influence of proton-irradiation in the voltage gain of two-stage operational transconductance amplifier (OTA) designed with silicon-on-insulator (SOI) fin field effect transistors (FinFETs) is studied. The OTA simulations were performed using Verilog-A approach based on experimental data extracted from the SOI FinFET electrical characterization, before and after proton-irradiation. The OTA is designed with SOI FinFETs of fin widths (W fin) of 20 nm, 120 nm, and 870 nm, all in the same predefined inversion region (g m/I D = 8 V−1). All evaluated OTA circuits exposed to proton-irradiation presented a voltage gain increase (compared with pre-irradiation circuits), of 0.87 dB, 1.19 dB, and 6.16 dB for fin widths of 20 nm, 120 nm, and 870 nm, respectively. The results show that despite the typical radiation effect of degradation of the individual transistors (it being more severe for larger fin width SOI FinFET), these effects combined in OTA circuits result in an unexpected improvement in DC voltage gain, especially for wider fins. Focusing on the fin width impact on the OTA voltage gain, before and after proton-irradiation, it is much greater for narrow fin width SOI FinFET thanks to the better Early voltage.

In this paper, we present a comprehensive study of the Fringing Field Biosensor Tunnel-FET (Bio-TFET) device based on 2D-device simulation. The presence of a biomaterial with a distinct dielectric constant (k, where ε = k*ε 0) on the underlap region (LUD) between gate and drain affects the ambipolar drain current (ID). The Bio-TFET can be observed in the ambipolar region (i.e., for negative gate voltage in an n type Bio-nTFET device) due to the variation of the k, biomaterial thicknesses (tBio), the LUD, and/or the presence of charges (QBio) into the biomaterial/silicon interface. The results show that the maximum sensitivity is observed when LUD = 30 nm (3 orders of magnitude higher compared with LUD of 25 nm lower or higher than 30 nm). When tBio increases from 10 nm to 30 nm (for k = 10), the sensitivity increases up to 1 orders of magnitude. The presence of QBio into the biomaterial also increases the sensitivity of 60 times for a fixed value of tBio = 30 nm and k = 10 and QBio changing from 1 × 1010 cm−2 to 1 × 1012 cm−2. The results show that the sensitivity of the fringing field Bio-nTFET is strongly dependent on the tunneling length modulation.

Made available in DSpace on 2022-04-28T19:42:10Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-01-01 An evaluation of a dielectrically modulated (DM) and a fringing field (FF) biosensor based on a tunneling field-effect transistor (Bio-TFET) by 2D numerical simulation is presented. The bio detection is based on the presence of a biomaterial with a distinct dielectric constant (k) on the sensitivity area. The performance of the devices is compared in terms of drain current in the ambipolar region (i.e., for negative gate voltage in an n-type Bio-nTFET device) due to the variation of the k, drain underlap length (LUD), and the presence of charges (QBio) into the biomaterial/silicon interface. The results show that the DM biosensor with LUD = 25 nm exhibits a higher sensitivity in all k simulated compared with FF biosensor, resulting in more than 2 orders of magnitude for k = 10. In the presence of charges, the DM shows a higher sensitivity in all of the range studied. Higher sensitivity values over a wider range of LUD and QBio are desirable and DM Bio-TFET achieves a better result compared with the FF Bio-TFET. Results show a new outlook for each type of biosensor. LSI/PSI/USP University of Sao Paulo UNESP Sao Paulo State University UNESP Sao Paulo State University

Nanoribbons built on gateless (GL) Ultra-Thin Body and Buried Oxide (UTBB) Back Enhanced SOI (BESOI) pMOSFET were analyzed as a charge-based (CB) biosensor for positive and negative charges into the biomaterial for the first time. Experimental GL BESOI pMOSFET was used as the basic structure for the CB biosensor and the influence of the charges were studied by numerical simulations. In general, when the CB biosensor was biased at weak inversion, the sensitivity is higher than when it was biased at strong inversion. For negative charges in the biomaterial, the conduction at front interface is favored. On the other hand, the conduction at back interface is higher if the biomaterial has positive charges. The nanoribbon GL UTBB BESOI pMOSFET showed to be a promising structure for an integrated charged based biosensor.

In this paper MISHEMTs with two different gate dielectrics (Al 2 O 3 and SiNx) are analyzed focusing on some analog figures of merit like transconductance, output conductance, transistor efficiency, Early voltage and intrinsic voltage gain. The Al 2 O 3 dielectric MISHEMT presented a degraded output characteristic in the bias range studied with a large self-heating turning the analog parameters impossible to be determined. The gate leakage of the SiNx MISHEMT is very high which degrades the subthreshold regime, decreasing the transistor efficiency at weak inversion, but the DIBL is much better than for the Al 2 O 3 devices. The SiNx devices present much better output characteristics resulting in a relatively large Early voltage and intrinsic voltage gain in strong inversion for this kind of devices up to 84 V/V (38.5 dB). The degradation with the temperature is small (around 1.5 dB from 25 °C to 150 °C) at strong inversion operation regime.

This work reviews the low-frequency noise performance of different flavors of silicon Gate-All-Around Nanowire (NW) (or Nanosheet - NS) transistors. For the horizontal devices, the 1/f-like noise is dominated by the number fluctuations mechanism, so that the Power Spectral Density (PSD) is directly proportional with the trap density in the gate stack. The impact of different process options and device architectures (junctionless versus inversion mode) is discussed. Overall, it is found that the average 1/f noise PSD is reducing going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices and, finally, vertical NW FETs. In the latter case, white noise may dominate the low-frequency noise spectrum.

In this paper we optimize the Dual-Technology Back-Enhanced SOI (DT BESOI) FETs varying the thickness of gate oxide, silicon film and buried oxide focusing on transfer characteristics. The DT BESOI optimization takes into account its behavior as both nMOS and pTunnel-FET device, which are obtained through the variation of positive and negative back biases. In the studied range, the optimized results were tox=lnm, tsi = 10nm and tBOX = 20nm. These DT BESOI results are compared with the conventional nMOS and pTFET devices.

Made available in DSpace on 2020-12-10T17:40:00Z (GMT). No. of bitstreams: 0 Previous issue date: 2020-09-01 Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) In this paper operational transconductance amplifiers (OTA) were designed with nanowire (NW) tunnel field effect transistors (TFET) with different source materials (Si, SiGe, and Ge) and compared with NW Si MOSFET devices. Lookup tables with experimental data were used to model the transistors and simulate the OTAs. At the same dimensions and transistor efficiency region, the TFET OTAs have larger gain than the MOSFET circuit. The Ge-source TFET OTA presents the highest differential gain (105 dB), followed by the Si TFET (96 dB) and the SiGe-source TFET (90 dB), with the MOSFET presenting the lowest gain (51 dB). However, the MOSFET has the best gain-bandwidth product (GBW) (9.2 MHz) followed by the Ge-source TFET (1.6 MHz), the SiGe-source TFET (900 kHz) and the Si TFET (41 kHz). The second group of OTAs, where the same power consumption was considered and where the gain of the MOSFET OTA and the GBW of the TFETs' circuits were increased was also studied. The gain of the MOSFET OTA increased to 56 dB, but it is still lower than the TFET circuits (96, 90 and 102 dB for the Si TFET, SiGe-source TFET and Ge-source TFET, respectively). The GBW of the Si TFET, SiGe-source TFET and Ge-source TFET circuits increased to 71 kHz, 1 MHz, and 2 MHz, respectively. Nevertheless, the MOSFET OTA has the best GBW (4.7 MHz) again but being just 2.35 times the GBW of the Ge-source TFET case. Therefore, because of the high gain of the TFETs OTAs, they are indicated for low power, low-frequency applications, with the Ge-source TFET presenting a good compromise between gain and GBW. The circuits' linearity was also verified, and they demonstrate to be more dependent on bias choices than on the devices themselves. Univ Sao Paulo, LSI PSI USP, Sao Paulo, Brazil Sao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil Sao Paulo State Univ, UNESP, Sao Joao Da Boa Vista, Brazil

This work analyzes the impact of temperature on the Analog figures of Merit of vertically stacked nanosheet nMOSFETs. The excellent electrostatic control between gate and channel results in a strong reduction of the short channel effect, as expected. The analog parameters like the intrinsic voltage gain, transistor efficiency and Early voltage are analyzed as a function of temperature. A high intrinsic voltage gain and a weak temperature dependence are observed, mainly at strong inversion region. The transistor efficiency and subthreshold swing maintain their value close to the theoretical limit.

An Operational Transconductance Amplifier (OTA) circuit designed with SiGe-source nanowire Tunnel-FETs is presented for the first time. The results are compared with Si nanowire TFET and with Si nanowire MOSFET designs. The transistors were modeled using experimental data in order to obtain a lookup table and the Verilog-A language for the circuit simulation. It was observed that there is a trade-off between the open loop gain (AV0) and the gain-bandwidth product (GBW) of these circuits. The Si-nanowire MOSFET OTA presents the lowest AV0 but the best GBW, while the Si nanowire TFET OTA presents the highest gain but the lowest GBW. The SiGe-source nanowire TFET OTA studied in this paper achieves a better compromise, which is, a better open loop gain (88 dB) than the Si-nanowire MOSFET circuit and a better gain-bandwidth product (718 kHz) than the Si nanowire TFET OTA.

Made available in DSpace on 2020-12-12T01:20:44Z (GMT). No. of bitstreams: 0 Previous issue date: 2020-05-01 This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET's saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition. LSI/PSI/USP University of Sao Paulo Imec ClaRoo E.E. Dept KU Leuven Sao Paulo State University (UNESP) Sao Joao da Boa Vista Sao Paulo State University (UNESP) Sao Joao da Boa Vista