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Limiting the location where electron injection occurs at the cathode interface to a narrower region is the key factor for achieving a highly improved RS performance, which can be achieved by including Ru Nanodots. The development of a memory cell structure truly at the nanoscale with such a limiting factor for the electric-field distribution can solve the non-uniformity issue of future ReRAM.

The fabrication and electrical characteristics of transparent hafnium-indium-zinc oxide (HIZO) thin film transistors (TFTs) are presented in detail. The devices incorporate an etch stopper structure, which may consist of either a single SiO x layer deposited by plasma enhanced chemical vapor deposition (PECVD) at 150 °C, or a dual stack of SiO x layers grown at 150 °C and 350 °C. The electrical properties suggest that the latter is more effective at protecting the underlying oxide semiconductor in the course of source-drain etching, hence resulting in high performance transparent TFTs. The saturation mobility and the subthreshold swing of the transparent HIZO TFTs fabricated with the dual etch stopper are 7.6 cm 2 /Vs and 0.30 V/decade, respectively. A 4-inch QVGA (320 × 240) transparent active matrix organic light emitting diode (AMOLED) display was realized using a backplane array of the above TFTs.

The bipolar resistive switching mechanisms of a p-type NiO film and n-type TiO2 film were examined using local probe-based measurements. Scanning probe-based current–voltage (I–V) sweeps and surface potential/current maps obtained after the application of dc bias suggested that resistive switching is caused mainly by the surface redox reactions involving oxygen ions at the tip/oxide interface. This explanation can be applied generally to both p-type and n-type conducting resistive switching films. The contribution of oxygen migration to resistive switching was also observed indirectly, but only in the cases where the tip was in (quasi-) Ohmic contact with the oxide.

The effects of post-thermal annealing on the stability of Ga2O3In2O3-ZnO (GIZO) thin film transistors (TFT) were investigated by comparing the GIZO TFTs annealed for 3 hour and for 65 hours under high-field bias stress, light illumination, and long-term storage in air. We found that the poor stability of the GIZO TFTs under these stresses was remarkably improved after 65 hours’ postthermal annealing at 250 O C. The improvement of the stability is ascribed to the reduction of the trap sites in the GIZO layer and curing of weak atomic bonds otherwise susceptible to breaking during the stress. pioonauaoeni Recently amorphous oxide semiconductor thin film transistors (TFT) have attracted much attention for large-area electronics such as active-matrix liquid displays (AMLCDs) and active-matrix organic light emitting diode (AMOLED) displays because the mobility is higher than that of the amorphous silicon (a-Si) TFT facilitating the integration of driving circuits and because the uniformity is expected to be superior to that of the lowtemperature polycrystalline silicon (LTPS) TFT due to structural homogeneity. In addition, the lower process temperature enables to use low-cost soda-lime glass substrate (1, 2). Although the stability of a TFT under electrical and environmental stresses is no less important than the other characteristics in commercialization, there have been few reports on the improvement of the poor stability of the oxide semiconductor TFTs. We investigated extensively to improve the stability of the oxide semiconductor TFTs especially for the amorphous Ga2O3-In2O3-ZnO (GIZO) TFT because of its high performances such as high mobility and steep subthreshold slope. We have found that a post-thermal annealing for a long duration is the most effective method to enhance the stability. In this letter we report the effects of the post-thermal annealing on the stability of the GIZO TFTs under electrical bias stress, light illumination, and long-term storage in air.

Degradation of Ga2O3–In2O3–ZnO (GIZO) thin-film transistors (TFTs), which are promising for driving circuits of next-generation displays, was studied. We found a degradation mode that was not observed in silicon TFTs. A parallel shift without any change of the transfer curve was observed under gate voltage stress. Judging from the bias voltage dependences we confirmed that the mode was mainly dominated by a vertical electric field. Thermal distribution was measured to analysis the degradation mechanism. Joule heating caused by drain current was observed; however, a marked acceleration of degradation by drain bias was not found. Therefore, we concluded that Joule heating did not accelerate degradation. Recovery of electrical properties independent of stress voltage were observed.

We have investigated the effects of annealing temperature on the physical and electrical properties of the HfO 2 film deposited by an atomic layer deposition (ALD) method for high- k gate oxides in thin-film-transistors (TFTs). The ALD deposition of HfO 2 directly on the Si substrate at 300 °C results in the formation of thin HfSi x O y interfacial layer between Si and HfO 2 . The subsequent low temperature N 2 -annealing of HfO 2 films (i.e., 300 °C) using a rapid thermal processor (RTP) improves the overall electrical characteristics of HfSi x O y –HfO 2 films. Based on the current work, we suggest that HfO 2 film deposited by the ALD method is suitable for high- k gate oxides in TFTs, which have to be fabricated at low temperature.

We have investigated the annealing effects of HfO 2 films deposited by an atomic layer deposition (ALD) method on the electrical and physical properties in the Si/SiO 2 /Pt/ALD-HfO 2 /Pd metal–insulator–metal (MIM) capacitors. If the annealing temperature for HfO 2 films was restricted below 500 °C, an annealing step using a rapid thermal processor (RTP) improves the electrical properties such as the dissipation factor and the dielectric constant. On the other hand, annealing at 700 °C degrades the electrical characteristics in general; the dissipation factor increases over the frequency range of 1∼4 MHz, and the leakage current increases up to 2 orders at the low electric field regions. We found that the degradation of electrical properties is due to the grain growth in the HfO 2 film (i.e., poly-crystallization of the film) by the high temperature annealing processing. We suggested that the annealing temperature must be restricted below 500 °C to obtain the high quality high- k film for the MIM capacitors.

Low-temperature Si thin film transistor (TFT) and its possibility as a new device process are described. Currently, an extensive study is performed in order to realize an advanced system on glass (SoG) by incorporating additional functional devices or circuits. By reducing further the process temperature down to 200 °C or below and by improving the fabrication process as an ultra-low temperature polycrystalline Si (U-LTPS), not only liquid crystal display (LCD) but also organic light emitting diode (O-LED) flat panel display (FPD) driven by using polycrystalline Si (poly-Si) TFTs is expected to be mounted on a flexible plastic substrate. Although technical issues to be solved remain for the fabrication of channels, gate insulator etc., it is possible for the Si TFT to be developed into a smart system on plastic for unique applications as well as a functional Si system-on-insulator in a ubiquitous information technology (IT) era.

We studied the growth of nanocrystalline silicon (nc-Si) thin film exhibiting a strong room temperature photoluminescence (PL) at 1.81– 2.003 eV . The amorphous silicon was crystallized by Ni silicide mediated crystallization (Ni SMC) and then Secco-etched to exhibit the PL. The PL peak energy and intensity increase with increasing the metal density on the a-Si because of the reduction in the grain size down to 2 nm . The photoluminescence energy and peak intensity depend strongly on the Secco etch time because the grain size is reduced by etching the grain boundaries.

The electrical stability of amorphous HfInZnO (HIZO) thin-film transistors (TFTs) was investigated under static and dynamic stress conditions, with simultaneous visible light radiation. The extent of device degradation is found to be strongly sensitive to the gate voltage, pulse duty ratio, pulse frequency, and exposure to visible light. Dynamic stress experiments demonstrate that highly stable devices can be realized by adjusting the pulse duty ratio and frequency, which suggests that amorphous HIZO TFTs are a promising candidate of switching devices for large-area high-resolution AMLCD applications.

Hafnium indium zinc oxide thin-film transistors (TFTs) with a double-gate structure were evaluated for the first time. Compared with devices with a single bottom gate, TFTs with an additional top gate exhibit improved subthreshold swing, threshold voltage, and field-effect mobility, as well as smaller subthreshold currents upon exposure to visible light. This phenomenon is attributed to the more effective suppression of excess photocurrents by the application of a double-gate structure. Negative-bias stress experiments under illumination indicate that the double-gate TFT exhibits very high stability compared with the device with a single-gate configuration.

We report the electrical stability of double-gate (DG) Ga-In-Zn-O thin-film transistors (TFTs). The threshold voltage (VT) shift of the DG TFT after 3 h of positive-bias temperature stress (VGS = + 20 V, VDS = + 0.1 V, and Temperature = 60°C) is as small as +2.7 V, while that of a conventional single-gate (SG) TFT is +6.6 V. The results of negative-bias temperature stress [(NBTS); VGS = - 20 V, VDS = + 10 V, and Temperature = 60°C] are more dramatic: The VT shift of the DG TFT is only +0.1 V, whereas that of the SG TFT is -9.1 V. With backlight illumination, the VT shift of the SG TFT under the same NBTS becomes severe ( -11.1 V). However, it remains as small as -0.7 V for the DG TFT.

The stability of transparent hafnium-indium-zinc oxide (HIZO) thin-film transistors (TFTs) was investigated under negative-bias stress conditions. TFTs that incorporate transparent electrode materials such as indium-tin oxide or indium-zinc oxide were studied, and the bias stress experiments showed that transparent TFTs undergo severe degradation (negative shift in threshold voltage VT) with simultaneous exposure to white light, in comparison with the results obtained in dark. The time evolution of VT indicates that the deterioration under illumination occurs mainly by the trapping of photogenerated carriers near the HIZO/dielectric interface.

A Ga-In-Zn-O thin-film transistor with double-gate structure is reported. Enhancement-mode operation that is essential to the constitution of a low-power digital circuitry is easily achieved when the upper and lower gate electrodes are tied together. The saturation mobility and the subthreshold swing are improved from 3.65 cm2/(V·s) and 0.44 V/dec to 18.9 cm2/(V·s) and 0.14 V/dec, respectively, compared with the single-gate structure. We can modulate the threshold voltage of either gate by adjusting the bias on the other gate.

The fabrication process and the characteristics of bottom-gate Ga2O3-In2O3-ZnO (GIZO) thin-film transistors (TFTs) are reported in detail. Experimental results show that oxygen supply during the deposition of GIZO active layer and silicon oxide passivation layer controls the threshold voltage of the TFT. The field-effect mobility and the threshold voltage of the GIZO TFT fabricated under the optimum process conditions are 2.6 cm2/V ldr s and 3.8 V, respectively. A 4-in QVGA active-matrix organic light-emitting diode display driven by the GIZO TFTs without any compensation circuit in the pixel is successfully demonstrated.

Polycrystalline silicon (poly-Si) films were prepared directly at a low temperature (

In this work, we propose a new polycrystalline silicon (poly-Si) film of large grain for thin film transistor on flexible substrate. Thin films of amorphous silicon were deposited on plastic substrate by using ion beam deposition (IBD) and crystallized by excimer laser annealing. The entire process was carried out at room temperature. Si film formed by IBD has much lower impurity such as Ar, O, and H than that deposited by conventional sputtering method. This high purity of Si film makes large grain size (0.5 µm) and shows high endurance of excimer laser energy both on quartz and plastic substrate for flexible active matrix organic light emitting diode (AMOLED).

The advanced low-temperature polysilicon (poly-Si) thin-film transistor with three-dimensional channels of fin-like profile has been demonstrated using excimer laser annealing and unique undercut structure without any additional patterning process. This approach provides a very narrow fin-like channel in devices with high ratio of film thickness to the width as well as a high-quality poly-Si film in channels with better crystallinity for the effect of columnar-like grain growth following the shrinkage of silicon stripe after laser irradiation. Due to that and the stronger electrical stress on the channel by the multigate, the new device with a fin-like channel structure shows good characteristics of the highest mobility up to 395 cm/sup 2//V/spl middot/s, a subthreshold voltage slope below 400 mV/dec, and an ON-OFF current ratio higher than 10/sup 6/.

We deposited amorphous silicon (a-Si) films below 150 °C with a custom-designed catalytic chemical vapor deposition (Cat-CVD) system. The hydrogen content of the films was controlled at less than 1.5 at. %. Excimer laser crystallization was performed without the preliminary dehydrogenation process. Crystallization occurred at a laser energy density above 70 mJ/cm2. Thin-film transistors (TFTs) were fabricated while the entire process temperatures were maintained at below 200 °C. We obtained a field-effect mobility of higher than 100 cm2/(V s) and a sub-threshold slope of 116 mV/dec. The a-Si film prepared by a low temperature Cat-CVD is a promising candidate for polycrystalline silicon TFTs of the active matrix display.

Flexible displays on plastic substrates, using polycrystalline Si (poly-Si)-based thin film transistor (TFT) devices to drive either active matrix liquid crystal displays (AMLCDs) or active matrix organic light emitting diode (AMOLED) display are expected to be a driving force of the display industry in the near future. The main challenges that are anticipated in the manufacture of poly-Si TFTs on plastic are the deposition of the precursor a-Si, and the crystallization of this layer at temperatures compatible with the plastic substrates–generally below 200 � C. 1,2) A major bottleneck in developing a low temperature poly silicon (LTPS) TFT on plastic substrate is the deposition of the precursor a-Si film. Generally, only plasma enhanced chemical vapor deposition (PECVD) and sputter technique can support low temperature processes. Although many works have been reported for PECVD a-Si film, relatively little work has focused on the sputtered a-Si film. 3–7) However, hydrogen-rich a-Si film by PECVD is unattractive for laser processing in that a-Si film was ablated by explosive hydrogen evolution. The low content of hydrogen in the a-Si film is easily controlled using the sputtering technique. However, the sputtered a-Si film also has the problem of film delamination during excimer laser annealing (ELA) at higher laser energy densities. Some reports explain that this delamination is due to film ablation by explosive evolution of captured Ar gas. 5) In the previous work, we deposited the precursor a-Si film with impurity gas of 0.39 at. % by Xe sputtering 8) and suppressed the delamination of Si film during laser irradiation.

Stable TiSi2 was formed by rapid thermal annealing (RTA) on single-crystal Si. Subsequently a 600 nm-thick Al-1%Si-0.5%Cu layer was deposited on the top of the formed TiSi2 followed by furnace annealing for 30 min at 400–600 ‡C in N2 ambient atmosphere. The thermal stability of Al-1%Si-0.5%Cu/TiSi2 bilayer and interfacial reaction were investigated by employing four-point probe, scanning electron microscopy (SEM) and Auger electron spectroscopy (AES). The composition and the phase of precipitates formed by the reaction of Al-1%Si-0.5%Cu with TiSi2 were studied by energy dispersive spectroscopy (EDS) and X-ray diffraction (XRD). It was found that the TiSi2 layer was consumed by the reaction between TiSi2 and Al-1%Si-0.5%Cu layer, resulting in precipitates at 550 ‡C. The results from EDS revealed that the precipitates were composed of Ti, Al and Si. The precipitates were identified as Ti7Al5Si12 ternary compound from XRD analysis.

Transparent hafnium indium zinc oxide thin-film transistors adopting single- and double-etch-stopper layers were evaluated. Compared to devices with a single SiOx etch stopper (ES) grown at 150°C, a double ES with a second SiOx film grown at 350°C provides a superior device performance such as improved subthreshold swing, threshold voltage, field effect mobility, and higher stability under a negative bias stress. The stretched-exponential analyses of the bias stress results indicate that the denser high-temperature SiOx protects more effectively the underlying semiconductor during the source/drain etch process and suppresses the generation of defect states therein.

Microcrystalline silicon was deposited on glass by standard plasma enhanced chemical vapor deposition using H2 diluted SiH4. Raman spectroscopy indicated a crystalline volume fraction of as high as 40% in films deposited at a substrate temperature 350oC. The deposition rate in films was as high as 10Å/sec. This process produced ¥ìc-Si TFTs with both an electron mobility of 10.9cm2/Vs, a threshold voltage of 1.2V, a subthreshold slop of 0.5V/dec at n-channel TFTs and a hole mobility of 3.2cm2/Vs, a threshold voltage of -5V, a subthreshold slop of 0.42V/dec at p-channel TFTs without post-fabrication annealing.

Forming high-quality Si film on glass with low cost has become one of key challenges in making high performance low temperature poly-Si TFT (LTPS) for future SOG applications. A new method of applying a finlike channel structure into the LTPS TFT is proposed. During the simple ELC process, the geometry size difference between the source/drain (S/D) and the channel region produces a new effect of self-selective enhanced crystallization on the fin-like channel. Via this effect, a high quality poly-Si with larger grain, smoother surface and more compact grain arrangement is achieved. Meanwhile, just like its precursor the SOI FinFET, the fin-like LTPS TFT structure demonstrates a sharp subthreshold slope, and higher transconductance and short channel effect immunity than the conventional thin film device. This was confirmed by ISE simulation.

The charge trapping characteristics of 30-nm-thick Si3N4 and 3-nm-thick Al2O3 layers between amorphous In-Ga-Zn-O thin films and 100-nm-thick blocking oxides made of thermal SiO2 were examined. The Si3N4 layer showed several discrete trap levels with relatively low density, while the Al2O3 layer showed a higher trap density with continuous distribution for electron trapping. When no tunneling oxide was adopted, the trapped carriers were easily detrapped, even at room temperature. Adoption of a 6-nm-thick SiO2 tunneling layer grown by atomic layer deposition largely improved the retention of the trapped charges and retained ∼60% of the trapped charges even after 10 000 s.

The negative bias illumination temperature stress instability of amorphous Hf-In-Zn-O thin film transistors with different dimensions was evaluated. The threshold voltage (Vth) shift increased in devices with shorter channel lengths but showed almost no association with the channel width. This behavior was attributed to the diffusion and drift of the photogenerated holes at the channel/dielectric interface from regions near the drain to those near the source, which were due to the simultaneous presence of gate and drain biases. The Vth near the source, which shows the largest shift and hence has the highest local value, governs the overall Vth.

In this study, we examine the possibility of using Ti/Cu bilayer as source/drain electrodes for SiNx-passivated Hf–In–Zn–O (HIZO) thin film transistors by comparing their electrical properties with devices that use Mo electrodes. The Mo devices operate in depletion mode with a higher field effect mobility, while the Ti/Cu devices exhibit an improved subthreshold swing and operate in enhancement mode. Transmission electron microscopy characterization reveals the formation of an amorphous TiOx layer at the Ti/HIZO interface, which is suggested to be responsible for the disparate device characteristics in terms of contact resistance and threshold delay.

The threshold voltage instability (Vth) in indium-gallium-zinc oxide thin film transistor was investigated with disparate SiNx gate insulators under bias-temperature-illumination stress. As SiNx film stress became more tensile, the negative shift in Vth decreased significantly from −14.34 to −6.37 V. The compressive films exhibit a nitrogen-rich phase, higher hydrogen contents, and higher N–H bonds than tensile films. This suggests that the higher N–H related traps may play a dominant role in the degradation of the devices, which may provide and/or generate charge trapping sites in interfaces and/or SiNx insulators. It is anticipated that the appropriate optimization of gate insulator properties will help to improve device reliability.

not Available.

Ga-In-Zn-O (GIZO) thin film transistors (TFTs) with disparate passivation structures were fabricated and their stabilities were compared. The devices were subjected to a negative bias stress with simultaneous exposure to visible light. TFT that incorporates a dual passivation composed of a SiO x layer grown at a relatively high temperature with an additional SiN x film deposited shows only -0.8 V V th shift, whereas a -5.7 V shift was observed for a TFT covered by a single SiO 2 film. The device degradation is susceptible to the ability of protecting external moisture, which may adsorb on the surface of the GIZO semiconductor to create donor states therein.

We investigated the effect of device configuration on the light-induced negative bias thermal instability of gallium indium zinc oxide transistors. The V th of back-channel-etch (BCE)-type transistors shifted by ―3.5 V, and the subthreshold gate swing (SS) increased from 0.88 to 1.38 V/decade after negative bias illumination temperature stress for 3 h. However, etch-stopper-type devices exhibited small V th shifts of ―0.8 V without degradation in the SS value. It is believed that the inferior instability of the BCE device is associated with the formation of an interfacial molybdenum (Mo) oxychloride layer, which occurs in the course of dry etching Mo using Cl 2 /O 2 for source/drain patterning.

We investigated the impact of photon irradiation on the stability of gallium-indium-zinc oxide (GIZO) thin film transistors. The application of light on the negative bias temperature stress (NBTS) accelerated the negative displacement of the threshold voltage (Vth). This phenomenon can be attributed to the trapping of the photon-induced carriers into the gate dielectric/channel interface or the gate dielectric bulk. Interestingly, the negative Vth shift under photon-enhanced NBTS condition worsened in relatively humid environments. It is suggested that moisture is a significant parameter that induces the degradation of bias-stressed GIZO transistors.

Degradation of Ga2O3–In2O3–ZnO (GIZO) thin-film transistors (TFTs), which are promising for driving circuits of next-generation displays, was studied. We evaluated degradation caused by applying gate voltage and drain voltage stress. A parallel shift of the transfer curve was observed under gate voltage stress. The amount of threshold voltage shift when applying gate and drain voltage stress was smaller than that in the case of only gate voltage stress. Joule heating caused by the drain current was observed. We reproduced this degradation of transfer curve change by device simulation. When we assumed the trap level as the density of state (DOS) model and increased two kinds of trap density, we obtained properties that show the same trends as the experimental results. We concluded that two degradation mechanisms occur under gate and drain voltage stress conditions. # 2009 The Japan Society of Applied Physics

Effects of plasma treatments on the back-channel of amorphous Ga 2 O 3 -In 2 O 3 -ZnO (GIZO) thin film transistors (TFTs) are compared for N 2 and N 2 O plasma. Acceptor-like states originating from the oxygen adsorbed on the back-channel of the GIZO TFTs suppress the back-channel current by capturing the electrons in the GIZO active layer and thus shift the threshold voltage to the positive direction. It is also shown that the oxygen in a silicon oxide passivation layer reduces the back-channel current. An enhancement-mode GIZO TFT has been successfully fabricated by combining the N 2 O plasma treatment and the silicon oxide passivation layer.

Bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) were fabricated and evaluated their characteristics and electrical stability under various stress condition. nc-Si with high crystallinity was deposited employing Inductively coupled plasma chemical vapor deposition(ICP-CVD) system. We employed helium gas diluted deposition and all the process temperature was kept under 350oC. We fabricated conventional inverted-staggered nc-Si TFTs. Fabricated nc-Si TFTs showed fine electrical characteristics, such as electrical mobility of 0.64~0.77 cm2/V⋅sec. We investigated its stability through constant-voltage stress and constant-current stress. The threshold voltage shift after 30,000 seconds gate bias (10V) stress was only 0.098V, which is considerably less compared to a-Si:H TFT. Under the static current stress condition, the threshold voltage of the nc-Si TFT was shifted less than that of a-Si:H TFT. It demonstrates that nc-Si TFT exhibit better stability than conventional a-Si:H TFT.

We successfully fabricated GIZO (Ga2O3-In2O3-ZnO) TFTs with high mobility of 2.6 cm2/Vs and threshold voltage standard deviation of 0.7V which is comparable to that of a-Si TFTs. Because conventional 5 mask process and bottom gate TFT structure of back channel etch type with channel length of 5 μm is used, it is expected to be transferred to mass production line in near future. Also we report the dependency of threshold voltage on the post process after the back surface of GIZO is exposed and suggest the effective method for controlling the threshold voltage of amorphous GIZO TFTs. Finally we demonstrate 4 inch QVGA AMOLED display driven by GIZO TFTs.

A technique of ion shower doping was performed to form source-drain contacts for polysilicon thin-film transistors (TFTs) on polyethersulfone (PES) substrates. The doped layer was subsequently annealed with an excimer laser to electrically activate the dopant atoms. The doped polysilicon films on the PES substrate showed much higher sheet resistances than those on the glass substrate with the identical doping and activation conditions. Moreover, the plastic substrates is easily heated up and caused a film failure for the prolonged exposure of the ion shower doping. The effective doping time and the resulting ion dose could be increased remarkably by reducing the radio-frequency power as well as by inserting interval pulses for dopants relaxation during the ion doping. As a result, a sheet resistance value as low as 300 ohms/sq. was obtained, which is low enough for a good ohmic contact.

LTPS TFTs realized with 3D Fin-like multiple-channels exhibit better electrical characteristics than those of conventional planar TFTs, due to their novel structure and the higher film quality in their device channels obtained through an ELC (Exicmer Laser Crystallization) process. The processes developed to form high TSi/WSi ratio Si fins serve to provide a larger ELC process window without involving additional patterning steps.