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Electron spin resonance (ESR) spectroscopy measures paramagnetic free radicals, or electron spins, in a variety of biological, chemical, and physical systems. Detection of diverse paramagnetic species is important in applications ranging from quantum computation to biomedical research. Countless efforts have been made to improve the sensitivity of ESR detection. However, the improvement comes at the cost of experimental accessibility. Thus, most ESR spectrometers are limited to specific sample geometries and compositions. Here, we present a nonresonant transmission line ESR probe (microstrip geometry) that effectively couples high frequency microwave magnetic field into a wide range of sample geometries and compositions. The nonresonant transmission line probe maintains detection sensitivity while increasing availability to a wider range of applications. The high frequency magnetic field homogeneity is greatly increased by positioning the sample between the microstrip signal line and the ground plane. Sample interfacing occurs via a universal sample holder which is compatible with both solid and liquid samples. The unavoidable loss in sensitivity due to the nonresonant nature of the transmission line probe (low Q) is recuperated by using a highly sensitive microwave interferometer-based detection circuit. The combination of our sensitive interferometer and nonresonant transmission line provides similar sensitivity to a commercially available ESR spectrometer equipped with a high-Q resonator. The nonresonant probe allows for transmission, reflection, or dual-mode detection (transmission and reflection), where the dual-mode results in a √2 signal enhancement.

The polarization switching speed of ferroelectric (FE) hafnium zirconium oxide (HZO) is studied with the device size down to sub-μm in lateral dimension. Ultrafast measurement of transient switching current on metal-ferroelectric-metal (MFM) device with a crossbar array or a single crossbar structure is performed to analyze the switching dynamics. A record fast polarization switching of 360 ps is achieved for 15 nm thick HZO with 0.1 μm2 crossbar array device structure. The observed record switching speed is found to be limited by domain wall propagation speed in the nucleation limited switching process. It is further verified after significant reduction of RC delay of the devices and the implementation of crossbar array structure.

Carbon nanotubes (CNT) resistance-change memory devices were assessed for neuromorphic applications under high frequency use conditions by employing the ultra-short (100 ps -10 ns) voltage pulse technique. Under properly selected operation conditions, CNTs demonstrate switching characteristics promising for various NN implementations.

The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to curtail the overshoot by decreasing the parasitic capacitance using highly integrated 1T-1R or 1R-1R device structures. While this is readily achievable in single device test structures, it poses an intricate design constraint for memory array designs. Several papers (Degraeve et al., 2010, 2014; Fantini et al., 2013; Raghavan et al., 2013; Padovani et al., 2015) suggest that there is insufficient current to form stable filaments for small parasitic capacitances and/or low current compliance levels. Thus, the relationship between minimizing overshoot current and improved filament stability is tenuous. In this study, we utilize the forming energy-based understanding of filamentary forming to reveal that the parasitic capacitance should be optimized, rather than minimized for better filament control.

We report on a novel semiconductor reliability technique that incorporates an electrically detected magnetic resonance (EDMR) spectrometer within a conventional semiconductor wafer probing station. EDMR is an ultrasensitive electron paramagnetic resonance technique with the capability to provide detailed physical and chemical information about reliability limiting defects in semiconductor devices. EDMR measurements have generally required a complex apparatus, not typically found in solid-state electronics laboratories. The union of a semiconductor probing station with EDMR allows powerful analytical measurements to be performed within individual devices at the wafer level. Our novel approach replaces the standard magnetic resonance microwave cavity or resonator with a small non- resonant near field microwave probe. Using this new approach we have demonstrated bipolar amplification effect and spin dependent charge pumping in various SiC based MOSFET structures. Although our studies have been limited to SiC based devices, the approach will be widely applicable to other types of MOSFETs, bipolar junction transistors, and various memory devices. The replacement of the resonance cavity with the very small non- resonant microwave probe greatly simplifies the EDMR detection scheme and allows for the incorporation of this powerful tool with a wafer probing station. We believe this scheme offers great promise for widespread utilization of EDMR in semiconductor reliability laboratories.

We observe a gamma-irradiation-induced change in electrically detected magnetic resonance (EDMR) in TiN/Ti/HfO2/TiN resistive random access memory (RRAM). EDMR measurements exclusively detect electrically active defects, which are directly involved in the transport mechanisms within these devices. The EDMR response has an isotropic g value of 2.001 ± 0.0003. The response increases dramatically with increased gamma irradiation. We tentatively associate this EDMR response with spin-dependent trap-assisted tunneling events at O2− centers coupled to hafnium ions. Although our study cannot fully identify the role of these defects in electronic transport, the study does unambiguously identify changes in transport defects caused by the ionizing radiation on defects involved in electronic transport in RRAM devices. This paper also contributes more broadly to the RRAM field by providing direct, though incomplete, information about atomic scale defects involved in electronic transport in leading RRAM systems.

To combat the large variability problem in resistive random access memory, current compliance elements are commonly used to limit the in-rush current during the forming operation. Regardless of the compliance element (1R-1R or 1T-1R), some degree of current overshoot is unavoidable. The peak value of the overshoot current is often used as a predictive metric of the filament characteristics and is linked to the parasitic capacitance of the test structure. The reported detrimental effects of higher parasitic capacitance seem to support this concept. However, this understanding is inconsistent with the recent successes of compliance-free ultrashort pulse forming which guarantees a maximum peak overshoot current. We use detailed circuit analysis and experimental measurements of 1R-1R and 1T-1R structures to show that the peak overshoot is independent of the parasitic capacitance while the overshoot duration is strongly dependent on the parasitic capacitance. Forming control can be achieved, in ultrashort pulse forming, since the overshoot duration is always less than the applied pulse duration. The demonstrated success of ultrashort pulse forming becomes easier to reconcile after identifying the importance of overshoot duration.

Charge-capture/emission is ubiquitous in electron devices. Its dynamics often play critical roles in device operation and reliability. Treatment of this basic process is found in many text books and is considered well understood. As in many electron device models, the individuality of immobile charge is commonly replaced with the average quantity of charge density. This has worked remarkably well when large numbers of individual charges (ensemble) are involved. As device geometries become very small, the ensemble “averaging” becomes far less accurate. In this work, the charge-capture/emission dynamic of Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is re-examined with full consideration of individual charges and the local field in their immediate vicinity. A dramatic modification of the local band diagram resulted, forcing a drastic change in emission mechanism. The implication is that many well-understood phenomena involving charge capture/emission will need to be reconsidered. As an example, this new picture is applied to the random telegraph noise (RTN) phenomenon. When the screening of a trapped charge by a polar medium such as SiO2 is quantitatively accounted for in this local field picture, a new physically sound RTN emission mechanism emerges. Similarly, the dynamics of post-stress recovery of Negative-Bias-Instability of p-channel MOSFET can be more rationally explained.

Resistive random access memory (RRAM) technology promises superior performance and scalability while employing well-developed fabrication processes. Conductance in insulating oxides employed in RRAM devices can be strongly affected by atomic-level changes that makes cell switching properties extremely sensitive to operation conditions inducing local structural modifications. This opens an opportunity to condition the memory cell stack by forming a conductive filament capable of high frequency, low energy switching. Certain materials with pre-existing conductive paths, in particular some polycrystalline oxides, like hafnia, are shown to respond well to this approach. For this class of materials, the concept of ultra-fast pulse technique as an ultimate method for assessing RRAM switching capabilities in circuitry operations is discussed. Hafnia-based cells demonstrate compliance-free (1R) forming with no current overshoot, low operation currents, and reduced variability.

We report on new fluctuation dynamics of the high resistance state of Hafnia-based RRAM devices after RESET. We observe that large amplitude fluctuations occur more frequently immediately after programming and their frequency of occurrence decays in the tens of microseconds. The fluctuation amplitude, on the other hand, does not decay noticeably over the entire millisecond read time. While post-programming instability and post-programming resistance dispersion have both been reported in the literature, the relaxation in the frequency of occurrence without a commensurate amplitude decay is new. Since picosecond pulses were used for our RESET operation, post-programming thermalization occurs on the nanosecond time scale. This clearly eliminates a thermally driven mechanism as the cause of the observed fluctuation behavior. Furthermore, reducing the READ voltage by tenfold does not have any effect and also eliminates read disturb as possible cause.

Switching variability in polycrystalline compliance-free HfO 2 -based 1R RRAM is evaluated employing ultra-fast low voltage pulse approach. Changes in filament conductivity are linked to the variations of energy consumed in a switching process. This study indicates that variability is reduced (suppressed) in more resistive filaments.

We report a new technique for the rapid measurement of full capacitance-voltage ( $C$ – $V$ ) characteristic curves. The displacement current from a 100-MHz applied sine wave, which swings from accumulation to strong inversion, is digitized directly using an oscilloscope from the MOS capacitor under test. A $C$ – $V$ curve can be constructed directly from this data but is severely distorted due to nonideal behavior of real measurement systems. The key advance of this paper is to extract the system response function using the same measurement setup and a known MOS capacitor. The system response correction to the measured $C$ – $V$ curve of the unknown MOS capacitor can then be done by simple deconvolution. No deskewing and/or leakage current correction is necessary, making it a very simple and quick measurement. Excellent agreement between the new fast $C$ – $V$ method and $C$ – $V$ measured conventionally by an LCR meter is achieved. The total time required for measurement and analysis is approximately 2 s, which is limited by our equipment.

One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown testing. Conventional screening methods have proved ineffective, because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted tunneling leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO2 DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions.

Despite the overwhelming effort to improve the efficacy of resistive random access memory (RRAM), the underlying physics governing RRAM operation have proven elusive. A survey of the recent literature almost universally indicates that the remaining glaring issues center around variability as well as endurance. The initial filamentary “forming” process is often linked to these problems. This work details our recent efforts to bring the forming process under control and the resulting improvements in RRAM viability in hafnia-based devices. We track the forming process via a “forming energy” metric that allows for filament optimization. By removal of all current compliance elements, and their associated parasitics, a targeted forming energy is achieved using ultrashort voltage pulses. By tailoring the forming energy, we show remarkable endurance window control.

In this paper we report TDDB results on SiO2/SiC MOS capacitors fabricated in a matured production environment. A key feature is the absence of early failure out of over 600 capacitors tested. The observed field accelerations and activation energies are higher than what is reported on SiO2/Si of similar oxide thickness. The great improvement in oxide reliability and the deviation from typical SiO2/SiC observations are explained by the quality of the oxide in this study.

We report multi-level MoTe 2 based resistive random-access memory (RRAM) devices with switching speeds of less than 5 ns due to an electric-field induced 2H to 2H d phase transition. Different from conventional RRAM devices based on ionic migration, the MoTe 2 -based RRAMs offer intrinsically better reliability and control. In comparison to phase change memory (PCM)-based devices that operate based on a change between an amorphous and a crystalline structure, our MoTe 2 -based RRAM devices allow faster switching due to a transition between two crystalline states. Moreover, utilization of atomically thin 2D materials allows for aggressive scaling and high-performance flexible electronics applications. Multi-level stable states and synaptic devices were realized in this work, and operation of the devices in their low-resistive, high-resistive and intrinsic states was quantitatively described by a novel model.

In this work, ultrafast pulses with pulse widths ranging from 100 ps to seconds were applied on the gate of Ge ferroelectric (FE) nanowire (NW) pFETs with FE Hf 0.5 Zr 0.5 O 2 (HZO) gate dielectric exhibiting steep subthreshold slope (SS) below 60 mV/dec bi-directionally. With applied gate bias pulses (V G = -1 to -10 V), high-mobility Ge drain current was monitored as a test vehicle to capture the polarization switching of HZO. It was found that HZO could switch its polarization directly by a single pulse with the minimum pulse width of 3.6 ns. The polarization switching triggered by pulse train with pulse width as short as 100 ps was demonstrated for the first time.

It has long been established that MOSFET random telegraph noise and the cumulative 1/f noise is the result of inversion charge tunneling in and out of bulk traps in the gate oxide near the interface. The tunneling nature is a key concept upon which the technique of trap profiling using 1/f noise is based on. In this work, we examine the tunneling pathways in SiC MOSFETs and show that the 1/f noise observed in SiC MOSFETs is likely of a completely different nature involving above band edge interface states that do not require tunneling to capture the inversion charge.

The self-heating effect (SHE) is a growing problem for decananometer CMOS and beyond with substantial efforts dedicated to mitigation. Here, we present a new memory concept which instead requires SHE exacerbation. As such, this memory concept is naturally suitable for extreme scaling. Preliminary result of this memory concept is demonstrated with an external heater as the SHE surrogates.

Charge pumping (CP) has proved itself to be one of the most utilitarian methods to quantify defects in MOS devices. In the presence of low-to-moderate gate leakage, CP quantification is most often implemented via a series of measurements at multiple frequencies. However, this approach is ill-equipped to handle excessive leakage currents common in advanced technologies. In this paper, we transform multifrequency CP from a quasi-dc measurement into a true ac measurement. This ac detection scheme, called frequency-modulated CP, is far better equipped to deal with high levels of leakage currents and thereby extends the usefulness of CP to current and future device technologies where excessive leakage is the norm. Additionally, we show that multifrequency CP has a long overlooked error that becomes significant in high-leakage situations. We discuss the origins of this error in detail and outline mitigation methodologies. Finally, we explore timing and voltage limitations of waveform generators and how these experimental boundary conditions impact on both frequency-dependent and FMCP.

There is an increasing number of reports on polar polymer-based Ferroelectric Field Effect Transistors (FeFETs), where the hysteresis of the drain current – gate voltage (I(d)-V(g)) curve is investigated as the result of the ferroelectric polarization effect. However, separating ferroelectric effect from many of the factors (such as charge injection/trapping and the presence of mobile ions in the polymer) that confound interpretation is still confusing and controversial. This work presents a methodology to reliably identify the confounding factors which obscure the polarization effect in FeFETs. Careful observation of the I(d)-V(g) curves, as well as monitoring the I(d)-V(g) hysteresis and flat band voltage shift as a function of temperature and sweep frequency identifies the dominant mechanism. This methodology is demonstrated using 15-nm thick high glass transition temperature polar polymer-based FeFETs. In these devices, room temperature hysteresis is largely a consequence of charge trapping and mobile ions, while ferroelectric polarization is observed at elevated temperatures. This methodology can be used to unambiguously prove the effect of ferroelectric polarization in FeFETs.

We report on a novel semiconductor reliability technique that merges electrically detected magnetic resonance (EDMR) with a conventional semiconductor wafer probing station. This union with a semiconductor probing station allows EDMR measurements to be performed at the wafer level. Our measurements forgo a microwave cavity or resonator for a very small non-resonant near field microwave probe [1]. Bipolar amplification effect (BAE) [4] and spin dependent charge pumping (SDCP) [5] were demonstrated on various SiC MOSFET structures. These measurements were made via frequency-swept EDMR. The elimination of the resonance cavity, and incorporation with a wafer probing station, greatly simplifies the EDMR detection scheme and offers promise for widespread EDMR adoption in semiconductor reliability laboratories.

In this work, we explore the effect of different defect profiles on the occurrence of early time-dependent-dielectric-breakdown (TDDB) to forecast the defect profile present in commercial grade SiC/SiO 2 DMOSFETs. Early failure simulations are performed using the recently developed “lucky defect” model. The model shows that the bulk defects in the gate oxide are the likely culprit for early TDDB failures through an increase in tunneling current via trap-assisted-tunneling (TAT). We show that an exponential distribution of “lucky defects” in the oxide bulk affects the failure distribution in a similar fashion to what we observe experimentally. We also identify the implications of under-sampling the population in these extrinsically dominated failure distributions. Armed with these tools, we show that, the speculated carbon rich transition layer at or near the interface is not likely present in the measured DMOSFETs.

The low processing temperature of polymeric materials and their wide range of applications make polar polymer based ferroelectric memory very promising and attractive. The typical configuration of the ferroelectric memory cell is the FeFET (Ferroelectric field-effect-transistor) with the polar polymer incorporated in the gate dielectric stack. The memory effect in these devices originates from the polarization of the ferroelectric polymer film and results in a hysteresis of the Id-Vg characteristics. In this study, we fabricated FeFETs based on ultrathin poly-Si channel and CP1- polymer (glass-transition temperature (Tg ~260 C) as the gate dielectric. We investigated the hysteresis of the Id-Vg curves over a wide range of temperatures and frequencies. We observed the effects of thermocycling on the device, such as the change of the hysteresis loop direction at temperatures close to Tg (associated with the change of the dominant hysteresis mechanism), and the simultaneous significant decrease in gate leakage current (which may indicate significant reduction of active defects in the polymer layer). The reversibility of the observed phenomena was also investigated through consecutive thermocycles. Soaking the chip in warm water (60 C) for 3 hours changes the magnitude of the hysteresis loop without changing the direction. The gate leakage current also remains very low. Thus, humidity may play some role in the hysteresis magnitude but not the loop direction, nor does it play any role in the leakage current. In this paper, we will discuss possible explanations of these observations.

We report a new technique for the rapid measurement of full capacitance-voltage (C-V) characteristic curves. The displacement current from a 100 MHz applied sine-wave, which swings from accumulation to strong inversion, is digitized directly using an oscilloscope from the metal-oxide-semiconductor (MOS) capacitor under test. A C-V curve can be constructed directly from this data but is severely distorted due to non-ideal behavior of real measurement systems. The key advance of this work is to extract the system response function using the same measurement set-up and a known MOS capacitor. The system response correction to the measured C-V curve of the unknown MOS capacitor can then be done by simple deconvolution. No de-skewing and/or leakage current correction is necessary, making it a very simple and quick measurement. Excellent agreement between the new fast C-V method and C-V measured conventionally by an LCR meter is achieved. The total time required for measurement and analysis is approximately 2 seconds, which is limited by our equipment.

Charge pumping is one of the most relied techniques used to quantify interface defects in metal-oxide-semiconductor devices. However, conventional charge pumping is easily hindered by excessive gate leakage currents, which render the technique unsuitable for advanced technology nodes. We demonstrate a new frequency-modulated charge pumping methodology in which we transform the quasi-dc charge pumping measurement into an ac measurement. The ac detection scheme is highly resistant to gate leakage currents and extends the usefulness of charge pumping as a defect monitoring tool for future technologies.

Accurate reliability predictions of real-world digital logic circuits rely heavily on the relevancy of device-level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device-level reliability data into a practical information for the real-world circuit implications. In this paper, we develop a methodology to bridge this gap by employing an eye diagram approach, which allows us to monitor, at circuit speed, device-level random jitter degradation in response to stress. By employing a variety of positive BTI gate voltage stress and sense bit sequences (including dc, ring oscillator (RO), and pseudorandom), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional RO-type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using RO structures as a proxy for real-random logic circuits. Only when a pseudorandom bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device-level reliability data to predict real-world digital logic circuit degradation.

The performance and reliability of highly scaled devices are becoming increasingly dominated by transient phenomena. Recently, fast capacitances versus voltage (CV) measurements have been gaining attention as a promising measurement tool to characterize the transient phenomena. However, fast CV has mainly been limited to monitoring stress-induced deviations in accumulation capacitance due, at least in part, to the inability to accurately measure the full CV. In this paper, we identify and mitigate the measurement considerations required to obtain a remarkably accurate correspondence between a complete fast CV measurement, from accumulation to inversion, and a conventional CV measurement on the same device. The results indicate that fast CV can be a potentially powerful tool for device characterization and reliability measurements.

In this paper we report an unexpected improvement in the SiC DMOSFET transistor characteristics after a long temperature treatment at 150 C. The evolution of the device characteristics during a TDDB stress is compared to that after an elevated temperature treatment. The improvement in characteristics after storage at high temperature is believed to be due to instabilities caused by the quality of the SiO2/SiC interface and its large density of defects.

The wide distribution of ON and OFF values and high SET current in resistive memory is attributed to the high current overshoot during the SET process. In this paper we show a circuit which is capable of precisely limiting the current during SET process. The circuit can achieve an overshoot free SET current as low as 20 µA within 500 ps. This results in less than 200 µA of device RESET current while maintaining a relatively large RON/ROFF ratio greater than 104.

Wave scattering by a potential step is a ubiquitous concept. Thus, it is surprising that theoretical treatments of ballistic transport in nanoscale devices, from quantum point contacts to ballistic transistors, assume no reflection even when the potential step is encountered upon exiting the device. Experiments so far seem to support this even if it is not clear why. Here we report clear evidence of coherent reflection when electron wave exits the channel of a nanoscale transistor and when the electron energy is low. The observed behavior is well described by a simple rectangular potential barrier model which the Schrodinger’s equation can be solved exactly. We can explain why reflection is not observed in most situations but cannot be ignored in some important situations. Our experiment also represents a direct measurement of electron injection velocity - a critical quantity in nanoscale transistors that is widely considered not measurable.

A methodology for the evaluation of ultra-fast interfacial traps, using jitter measurements as a probe, is developed. This methodology is applied to study the effect of PBTI stress on the density of ultra-fast electron traps (with 500 ps to 5 ns characteristic capture/emission times) in a high-k/Si nMOSFET. It is shown, that in spite of an observed increase of timing jitter after PBTI stress, this increase may not be correlated with an increasing density of interface traps. Rather, it is solely caused by a VT shift which simply decreases the output signal amplitude. The results indicate that ultra-fast (presumably interface) traps may not be affected by PBTI stress.

Frequency-dependent charge pumping (CP) (FD-CP) has emerged as a popular technique for studying the spatial and energetic distribution of defect centers in advanced high-k gate stacks. However, conflicting interpretations of the CP frequency-defect depth relationship has led to controversial and inconsistent findings between various groups. A key assumption is that most, if not all, bulk defect trapping/detrapping contributes to the CP current. In this paper, we show, experimentally using two independent measurements, that there is a large discrepancy between the total amount of bulk defect trapping/detrapping that occurs and the actual CP contribution due to these defects. We argue that the CP current due to bulk defects depends heavily upon the specific device geometry/technology, the minority-carrier lifetime, and FD-CP's general inability to function as a defect profiling tool.

The negative bias temperature instability (NBTI) is, arguably, the single most important reliability problem in present day metal-oxide-silicon field-effect transistor (MOSFET) technology. This paper presents a model for the NBTI which is radically different from the quite widely utilized reaction diffusion models which dominate the current day NBTI literature. The proposed model is relevant to technologically important nitrided oxide pMOSFETs. The model is clearly not, at least in its entirety, relevant to pure silicon dioxide gate pMOSFETs. The reaction diffusion models involve hydrogen/silicon bond breaking events at the silicon/silicon dioxide interface initiated by the presence of an interface hole, followed by the diffusion of a hydrogenic species from the interface as well as the potential rebonding of hydrogen and interface trap defect centers. This model does not invoke hydrogen in any form whatsoever but does simply account for the observed NBTI power law response with a reasonable, at least very plausible, assumption about defect distribution and provides a reasonably accurate value for this exponent. (Without making any assumption about defect distribution, the model still provides a time response semiquantitatively consistent with the observations, reasonable agreement considering the simplifying assumptions in the calculations.) The model also provides a reasonable explanation for the recovery which includes a simple explanation for the extremely rapid rate of recovery at short times. In addition, the model provides a very simple explanation why the introduction of nitrogen greatly enhances the NBTI. The model, as presented in this paper, should be viewed as a first-order approximation; it contains several simplifying assumptions. Finally, the model is consistent with recent electron paramagnetic resonance studies of NBTI defect chemistry in nitrided oxide pMOSFETs.

There is significant interest in the development of new dielectrics and new semiconductor/dielectric systems. Of particular interest are new materials for metal oxide field effect transistor systems and new materials for interlayer dielectrics. The electronic defects which limit the performance of these new material systems are largely unknown. Electron paramagnetic resonance (EPR) has unrivaled analytical power for the identification of the physical and chemical nature of trapping centers in semiconductors and insulators (1). However, the sensitivity of conventional EPR is orders of magnitude too low to make measurements in most present day solid state devices. Two electrically detected magnetic resonance (EDMR) techniques, spin dependent recombination (SDR) and spin dependent trap assisted tunneling (SDT) provide the same analytical power as conventional EPR but, in addition, offer a sensitivity many orders of magnitude higher. This enhanced sensitivity allows measurements to be made in essentially “state of the art” device structures and provide several other significant advantages. EDMR can, under some circumstances, provide information about the physical location and energy levels of deep level defects which play important roles in electronic devices. In this presentation, I’ll discuss EDMR results on low-K dielectric constant films (2), on high-K dielectric films on silicon (3), on near interface/interface traps in SiC MOSFET gate dielectrics (4), on defects which play dominating roles in stress induced leakage currents (5) and the negative bias temperature instability (6) in essentially “state of the art” plasma nitrided oxides in silicon based pMOSFETs. I will also show how energy resolved SDT can provide fairly precise measurements of dielectric defect energy levels and show how the SDR response as a function of gate voltage can provide qualitative information about the physical distribution of interface/near interface defects. ACKNOWLDEGEMENTS Work supported by Intel Corporation, U.S. Army Research Laboratory, GE Global Research, and NIST.

We report on a novel electron paramagnetic resonance (EPR) technique that merges electrically detected magnetic resonance (EDMR) with a conventional semiconductor wafer probing station. This union, which we refer to as wafer-level EDMR (WL- EDMR), allows EDMR measurements to be performed on an unaltered, fully processed semiconductor wafer. Our measurements replace the conventional EPR microwave cavity or resonator with a very small non-resonant near-field microwave probe. Bipolar amplification effect, spin dependent charge pumping, and spatially resolved EDMR are demonstrated on various planar 4H-silicon carbide metal-oxide-semiconductor field-effect transistor (4H-SiC MOSFET) structures. 4H-SiC is a wide bandgap semiconductor and the leading polytype for high-temperature and high-power MOSFET applications. These measurements are made via both “rapid scan” frequency-swept EDMR and “slow scan” frequency swept EDMR. The elimination of the resonance cavity and incorporation with a wafer probing station greatly simplifies the EDMR detection scheme and offers promise for widespread EDMR adoption in semiconductor reliability laboratories.

In this paper, a fast drain-current measurement methodology which supports the standard threshold voltage and transconductance extractions associated with the fast dynamic negative-bias temperature instability (NBTI) is presented. Using this methodology, we show that production quality transistors exhibit only minimal degradation after a brief stress at moderate to high dielectric fields (contrary to the excessive degradation reported in the recent literature). The degradation at stress conditions which are consistent with many recent NBTI studies is shown to be dominated by high-field stress, instead of NBTI. The ability to extract transconductance from fast drain-current measurements helps to identify the existence of a latent electron trapping/detrapping component which provides further support of a degradation mechanism dominated by high-field stress. This high-field-stress component, while dominating, has not been accounted for in most of the recent NBTI literature.

Current overshoot during forming/SET of RRAM devices is frequently considered one of the key factors contributing to variation of the formed filament [1,2,4,5]. It is generally believed that to minimize variation, the current overshoot should be controlled by minimizing the device parasitics [2,4,5]. On the other hand, there are reports suggesting that RRAM requires an optimum energy to form a robust filament [3,6,7]. In this paper, we show that for RRAM systems with compliance control, such as 1T-1R, this forming energy is linked to the current overshoot which in turn is linked to capacitance. In other words, blindly minimizing parasitics is a poor strategy. Instead, the device should be engineered for optimum (not minimum) parasitics. Previously, it has been shown that the duration of the overshoot current is determined by the parasitic capacitance [1]. A surprising consequence is that even with a long programming pulse, the actual current that flows through the RRAM can become very short when current compliance is used. For devices with extremely low parasitics, such as in actual production devices, it can lead to an effective programming pulse duration that is picoseconds or less. This unexpected ultra-short effective programming pulse means that an unexpectedly low amount of energy is dissipated into the filament and can lead to poor retention and endurance. Thus, it suggests that the common idea of minimizing the parasitics is counter-productive. In order to verify, high speed 1T-1R measurements were done with the experimental set up shown in Fig. 1. Five similar sized crossbar devices with different drain capacitances were measured. The details of the devices are given in Fig. 2. As shown in Fig. 1, we measure the current at the source side of the transistor by connecting it to the 50 Ω input of the oscilloscope (Fig. 3). This is not a direct measurement of the current going through the RRAM because only part of the charge of the parasitic capacitor flows through the transistor. The current paths are depicted in Fig. 4. Nevertheless, the measured current mirrors the current flowing through the RRAM and serves as a proxy. The current peaks (Fig. 3) for devices 1 to 3 decay in that order. These devices have similar capacitance but the post forming resistance decreases by the same order. For devices 4 and 5, that do not have a probe pad connected to the drain, the capacitances are much lower and thus an extremely short current peak is seen for device 4 and almost no current peak is observed for device 5. The missing current peak is due to finite sampling resolution (12.5 ps) of the oscilloscope and the current pulse being very short. To verify, we compare the results with spice modeling as shown in Fig. 4, including reflections of the fast pulse due to inevitable impedance mismatch of the device (not designed for RF measurements) and with a resolution of 12.5 ps to match that of the oscilloscope. For the simulations, the RRAM device was modeled as a variable resistor with resistance changing linearly from 20 MΩ to about 6 kΩ. Good agreement between the spice simulations and the measured current is achieved, as shown in Fig. 5. The simulated current waveforms, with 12.5 ps sampling resolution for all 5 devices are shown in Fig. 6. The peak is noticeable for device 5. In Fig. 7 we focus only on device 5; the sampling resolution is changed to 2 ps and the peak is clearly recovered. The agreement between simulation and experiment confirms our model prediction that (1) no matter how low the parasitic component is, current overshoot exists; (2) the magnitude of the current overshoot is determined by the applied voltage and the RRAM resistance, not the parasitic capacitance; (3) the parasitic capacitance determines the duration of the current overshoot. Fig. 8 shows the simulated current overshoot for devices of the same Rform and forming voltage but different parasitic capacitance. Clearly, both (2) and (3) affects the energy dissipated into the RRAM filament. With a targeted resistance, the only control available is the applied voltage and parasitic capacitance. When the parasitic capacitance is very low, the voltage must increase to provide optimum energy for a stable RRAM with long retention times and good endurance. However, high voltage tends to amplify the stochastic nature of the filament and can only go so far before losing control. Thus, the main avenue left for optimizing RRAM is to optimize the parasitics instead of minimizing it – a major departure from common wisdom. Figure 1

Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements overestimate the inversion charge for devices that have high level of defects. Mobility measured by the Hall effect is more accurate; however the conventional Hall mobility measurement is tedious. In this work, we demonstrate a wafer-level Hall measurement technique, which is simple and convenient to implement. With this method, extensive study of the mobility degradation is possible.