Device-level jitter as a probe of ultrafast traps in high-k MOSFETs

A methodology for the evaluation of ultra-fast interfacial traps, using jitter measurements as a probe, is developed. This methodology is applied to study the effect of PBTI stress on the density of ultra-fast electron traps (with 500 ps to 5 ns characteristic capture/emission times) in a high-k/Si nMOSFET. It is shown, that in spite of an observed increase of timing jitter after PBTI stress, this increase may not be correlated with an increasing density of interface traps. Rather, it is solely caused by a VT shift which simply decreases the output signal amplitude. The results indicate that ultra-fast (presumably interface) traps may not be affected by PBTI stress.