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In cavity quantum electrodynamics, optical emitters that are strongly coupled to cavities give rise to polaritons with characteristics of both the emitters and the cavity excitations. We show that carbon nanotubes can be crystallized into chip-scale, two-dimensionally ordered films and that this new material enables intrinsically ultrastrong emitter-cavity interactions: rather than interacting with external cavities, nanotube excitons couple to the near-infrared plasmon resonances of the nanotubes themselves. Our polycrystalline nanotube films have a hexagonal crystal structure, ~25 nm domains, and a 1.74 nm lattice constant. With this extremely high nanotube density and nearly ideal plasmon-exciton spatial overlap, plasmon-exciton coupling strengths reach 0.5 eV, which is 75% of the bare exciton energy and a near record for room-temperature ultrastrong coupling. Crystallized nanotube films represent a milestone in nanomaterials assembly and provide a compelling foundation for high-ampacity conductors, low-power optical switches, and tunable optical antennas., Comment: 35 pages, including supplementary information

Moore's law continues to prescribe ever smaller device dimensions with each new device node. While the new device nodes are scheduled at even pace, the innovation required to obtain commensurate device performance is greater with every device node. This increased complexity in the process, while maintaining the momentum of Moore's law, is increasing the pressure on the development teams to increase the learning rate on new processes and their interactions. There have been many publications on mix-and-match lithography to enable early learning. In this technique, one whole device level (often the gate definition) is replaced by a different technology (often e-beam), while all the other levels continue to be patterned using traditional optical lithography. Hybrid lithography, by contrast, is the use of different lithography technologies on a single resist level which enables the marriage of both technology's best properties. In this work, we present hybrid e-beam direct write and optical lithography, enabling high throughput (optical), high-resolution (EBDW), excellent overlay (EBDW) and fast prototyping (EBDW). We will show how IBM has used hybrid lithography to enable early learning on back end of the line (BEOL) processes and on extremely scaled SRAM cells ([email protected]^2) [D.M. Fried, et al., IEDM Proceedings (2004) 261-264].

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

An extremely low contact resistivity of 6-7 × 10-9 Ω·cm2 between Ni0.9Pt0.1Si and heavily doped Si is achieved through Schottky barrier engineering by dopant segregation. In this scheme, the implantation of B or As is performed into silicide followed by a low-temperature drive-in anneal. Reduction of effective Schottky barrier height is manifested in the elimination of nonlinearities in IV characteristics.

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

We report sub-20 nm sacrificial nanochannels that enable stretching and translocating single DNA molecules. Sacrificial silicon nano-structures were etched with XeF2 to form nanochannels. Translocations of linearized DNA single molecules were imaged by fluorescence microscopy. Our method offers a manufacturable wafer-scale approach for CMOS-compatible bio-chip platform.

A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant pat- terning in the sub-30-nm pitch regime using directed self-assembly (DSA) line-space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck tem- perature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal-oxide-semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node. © 2013 Society of Photo-Optical Instrumentation Engineers (SPIE) (DOI: 10.1117/1.JMM.12.4 .041305)

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.

This article describes an exploratory study of miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) to 100nm dimensions. The study has provided a first demonstration of MOSFETs which meet 100nm design rules for all critical device levels and the resulting devices have active areas which measure only 700nm by 150nm. Allowing for device isolation, this corresponds to an integration density of 4 devices per square micron. The peak transconductance of the devices, for 120nm gate lengths, is 410mS/mm at room temperature. This combination of extreme miniaturization and very high transconductance is achieved partly through conventional scaling and partly through use of a new ultracompact device configuration. This article describes design and fabrication of these devices, and follows with a discussion of their electrical properties.

In this work we present a potential solution for forming ultra-shallow junctions with extremely low contact resistivities in which dopants are implanted into silicides and diffused to the semiconductor interface using low temperature anneals. Conventional silicide process requires a fine tuning of silicide thickness and deep source/drain doping profile to achieve low contact resistance and low source/drain diffusion sheet resistance. With the silicide implantation approach, we show that they can be engineered independently, providing a larger design space for the reduction of total external resistance. We demonstrate that contact resistance for NiPt silicide can be significantly reduced down to 7×10−9 Ω-cm2 for p+ Si and 6×10−9 Ω-cm2 for n+ Si by using Schottky Barrier Height (SBH) tuning through the implantation of B/As into pre-formed NiPtSi followed by low-temperature drive-in annealing (see Fig. 1 for the process flow). Moreover, we find that the same low contact resistance can be achieved for both heavily and moderately doped junctions, which grants an additional degree of freedom in junction design to reduce series resistance. With this technology, the ultra-shallow junction process can be simplified to the formation of ultra-thin silicide followed by shallow implantation and low temperature RTA (

We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].

Sub-100 nm short-channel In0.7Ga0.3As MOSFETs are demonstrated for both depletion- and enhancement-mode devices. High current of 960 muA/mum and record transconductance of 793 muS/mum have been achieved. Scaling behavior is investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

In conclusion, we have demonstrated long and short-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation. Devices with alpha-Si show much higher transonductance and effective peak mobility of 3810 cm2/Vs. These results indicates that the alpha-Si layer has successfully passivated the III-V surface. Short-channel MOSFETs with gate length of 160 nm display record current of 825 mA/mm and peak transconductance of 683 mS/mm. These results are promising for realizing InGaAs-channel MOSFETs suitable for VLSI applications.

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1times10-8 Omega-cm2 for both n+ and p+ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node. To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond. In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the world's smallest working SRAM cell.

Critical lithographic dimensions will soon place particularly severe demands on the performance of chemically amplified (CA) resists. Although Extreme Ultraviolet (EUV) and 193 nm (immersion interferometric) lithographic results have demonstrated half pitch imaging down to 35 nm there is nonetheless a concern that image blur due to acid diffusion will begin to seriously impact the utility of CA photoresists. Previously we demonstrated that low activation energy resists and E-Beam lithography can be used to print line/space arrays with resolution approaching 20 nm. We described the factors impacting the reactivity of ketal/pHOST based resists and compared the attainable resolution under different processing conditions. In this report we describe studies on acid diffusion emphasizing the role of water in low Ea systems. We also discuss methods for the control of water absorption in low Ea resists.

A 0.143 /spl mu/m/sup 2/ 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (V/sub T/) and cell beta ratio (/spl beta/) are optimized for cell stability at these aggressive ground rules. The 0.143 /spl mu/m/sup 2/ 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at V/sup DD/=1.0 V.

In this work, we present very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide, suitable for low temperature operation. Saturation transconductances of 1380 mS/mm for nMOSFETs and 523 mS/mm for pMOSFETs are achieved at -200 /spl deg/C. At the same temperature, I/sub on/ for a 1.2 V supply is 1.2 mA//spl mu/m for nMOSFET, and 0.5 mA//spl mu/m for pMOSFET, respectively, with I/sub off/ of both devices on the order of 10 nA//spl mu/m. A delay of 6.4 ps per stage at 1.5 V is measured at -100 /spl deg/C for a 101-stage CMOS ring oscillator. The delay of the same ring oscillator at room temperature is 8.2 ps per stage. These represent the highest CMOS performance figures reported to date.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. >

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET. >

KRS-XE, a high performance chemically amplified photoresist designed specifically for e-beam mask making applications, has been enhanced to achieve reduced “footing” on chrome oxide surfaces while still maintaining the original lithographic characteristics that make KRS-XE a promising mask making candidate. These attributes include high resolution, superior bake latitudes, high vacuum stability, coated shelf life of greater than 2 months, and, most notably, the absence of a post exposure bake. In conjunction with the footing reduction the requisite sensitivity requirement of

Ultra-low power operation of 0.1 /spl mu/m CMOS is demonstrated at power supply voltages well below 1 V. Design trade-offs among gate delay, active power, and standby power are carried out in a power supply-threshold voltage design space. Experimental results show a ring oscillator delay of 106 ps at a power supply voltage of 0.5 V, and a minimum power-delay product of 0.03 fJ/stage (switching factor=0.01) at 0.4 V. A 20X reduction in power/circuit is achieved at the same performance level as 0.25 /spl mu/m CMOS. >

We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and passivation. We demonstrate double-gate FET operation with good transport at both interfaces, inverter action, and NOR logic.

Graphene is a very promising candidate for applications in flexible electronics due to its high carrier mobility and mechanical flexibility. In this paper, we present results on graphene RF devices fabricated on polyimide substrates with cutoff frequencies as high as 10 GHz. Excellent channel mobility and current saturation are observed in graphene long channel devices on polyimide. Graphene devices on polyimide also show very good temperature stability from 4.4 K to 400 K and excellent mechanical flexibility up to a bending radius of 1 mm. These demonstrated properties make graphene an excellent candidate for flexible wireless applications.

The ability to reduce device features to increasingly smaller dimensions offers the potential for remarkable circuit performance and low power consumption. CMOS (Complementary Metal-Oxide-Semiconductor) devices with 100 nm channel lengths offer a 2X performance gain over 0.25 μm technology at a reduced power supply as well as the potential for a 20X reduction in active power at comparable performance levels. Continued scaling of devices beyond 100 nm dimensions faces various fundamental limitations. Overcoming these limitations will require technological innovation in both device design and fabrication.

The authors demonstrate pattern transfer of 29-nm-pitch self-assembled line-space polystyrene-poly(methyl methacrylate) patterns generated by graphoepitaxy into three important materials for semiconductor device integration: silicon, silicon nitride, and silicon oxide. High fidelity plasma etch transfer with production-style reactors was achieved through co-optimization of multilayer masking film stacks and reactor conditions. The authors present a systematic study of the line edge roughness (LER) and line width roughness evolution during pattern transfer. Application of a postetch annealing process shows reduction of the LER of silicon features from around ∼3 nm to less than 1.5 nm. These results further demonstrate that directed self-assembly-based patterning may be a suitable technique for semiconductor device manufacturing.

We report on a study of the effects of dopant concentration and linewidth on the formation of TiSi2 on polysilicon. The transformation from the C49 phase to the C54 phase is inhibited by a high concentration of either phosphorus or arsenic in blanket polysilicon films. For sub-half-micron lines, patterned in polysilicon doped with As or P, agglomeration is the key factor in the inability to produce low resistance silicide. The result is a critically shrinking process window for the attainment of low resistance VLSI interconnects.

The authors report on a hybrid lithography process that integrates electron beam lithography (EBL) and optical photolithography. To maximize resolution and density, the EBL exposure is performed using a hydrogen silsesquioxane-based resist, while the photolithographic exposure is performed using standard positive or negative tone 248nm photoresists. Both exposures take place on a common underlayer consisting of an antireflective coating (ARC). During pattern transfer into the ARC layer, a composite image of the two lithographic exposures is formed creating a robust and versatile etch mask for further pattern transfer into the substrate. They demonstrate the utility of this technique by using it to pattern the active, gate, and wiring levels of complementary metal oxide semiconductor devices and circuits consisting of trigated Fin-based field effect transistors. These devices have a minimum active area pitch of 50nm, minimum gate pitch of 90nm, and achieve densities suitable for 15nm node static random acc...

Critical lithographic dimensions are rapidly approaching the sub-50nm regime where there is a concern that image blur due to acid diffusion will impose a practical limit to the resolution of chemically amplified (CA) resists. Although recent EUV and 193- and 157nm immersion interferometric experiments have reportedly resolved line-space arrays with individual dimensions on the order of ∼40nm, smaller nested features are likely to prove problematic. Numerous reports suggest that conventional photoresist performance degrades rapidly at half-pitch dimensions in this range. New approaches to processing and materials development of photoresists will likely be required if the concept of chemical amplification is to be extended to the 32nm node and beyond. In this article we show that through materials choice and proper processing, image blur can be controlled to an extent where dense features below 40nm can routinely be resolved in CA resists. We describe our studies on high-sensitivity resists of differing act...

Summary form only given. SISFETs in the InGaAs/InAlAs lattice-matched-to-InP material system with record transconductance have been fabricated. These devices use an InGaAs channel layer grown on an InAlAs buffer layer grown on (and lattice matched to) a semi-insulating InP substrate. Carriers are induced in the undoped channel layer by the action of a doped InGaAs gate layer acting across an undoped InAlAs insulating layer. The device is thus the analog of the GaAs/AlGaAs SISFET (or more broadly the silicon gate MOSFET) but provides the electron transport advantages of InGaAs. In addition, ion implantation and arsine overpressure rapid thermal annealing of shallow implants into InGaAs were studied, and it was found that shallow self-aligning implantation structures can be achieved with much lower resistance than in GaAs. >

We explore the fabrication of complementary metal–oxide–semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and below using a variety of lithographic, processing, materials, and device design innovations. Device design parameters tailored for high performance at low operating power include the use of bulk and silicon‐on‐insulator substrates, a steep retrograde channel doping scheme, ultrathin (∼3 nm) gate dielectric, shallow source, and drain extensions, and a metal‐over‐gate structure. Mix‐and‐match lithography, including the use of electron‐beam lithography for all critical levels, x‐ray lithography for gate level definition, and optical (deep ultraviolet) lithography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as for device and circuit metallization have been developed in conjunction with the lithographic processes in an effort to fa...

Ultracompact n‐channel silicon metal–oxide–semiconductor field effect transistors (MOSFETs) have been fabricated using electron beam nanolithography for all critical levels leading to a first demonstration of silicon MOSFETs which meet 100 nm ground rules. The smallest devices fabricated have active areas which measure only 700 nm×150 nm and are enclosed by a narrow trench isolation scheme. Devices of this size and with physical gate lengths of 120 nm and widths of 150 nm display an extrinsic transconductance of 410 mS/mm at room temperature. This level of miniaturization and performance arises in part from direct application of conventional scaling principles and in part from implementation of a novel device configuration. This article discusses the design of these devices as well as details of their electrical characteristics.

The fabrication of exploratory silicon metal–oxide–semiconductor field effect transistors in which all device levels meet 100 nm groundrules is reported. The device design incorporates several novel features which allow for an ultracompact structure. These features include shallow trench isolation, over‐the‐gate contacts, fully overlapped source, drain and gate contacts and shallow source and drain extensions. This article offers a detailed description of the fabrication process, with an emphasis on high resolution, high accuracy electron beam nanolithography and new reactive ion etching processes. Complete process integration is described which culminates in the successful fabrication of functional compact devices.

Preparation of cross-sectional TEM samples has been completed without use of the normal means of mechanical polishing and ion-milling. Instead, lithographic processing and reactive ion-etching (RIE) were used to define thin walls ranging from 100 to 1000 nm in width which protruded 1 μm from the substrate surface. The substrate was cut into pieces suitable for securing them into a standard double-tilt holder so that the etched walls were exposed to the electron beam and images could be formed. Samples have been made using both electron beam and optical lithography with different dry etching processes to define thin walls of composite layers of Si, Si 3 N 4 and SiO 2 and also a thin film of Al-Cu(2 wt%). The results present a promising new method for preparation of cross-sectional TEM samples that is less labor-intensive and more productive than mechanical polishing and ion-milling.

Presently available electron‐beam lithography systems for submicron lithography have minimum beam sizes or edge resolution on the order of 0.1–0.2 μm. Satisfactory proximity correction, linewidth control, and profile quality are critically dependent on beam size. Moreover, variations in beam size about the expected size can result in severe degradation of linewidth control. In this paper, we will examine the relationships between linewidth control, beam size, and proximity correction and show that it is possible, but difficult, to successfully use electron‐beam lithography under these conditions. High resolution vector scan electron‐beam systems with known Gaussian beam sizes are used to produce features down to 0.25 μm in single and multilayer resist. It is shown that the beam size and forward scattering must be included in the proximity correction of submicron patterns. The effects of varying the beam size are also investigated and it is shown, for example, that an increase in beam size of only 0.02 μm can significantly reduce the developed resist linewidth of sub‐half‐micron features in 1.0 μm thick resist.

While lithography tooling continues to advance to achieve the resolution and overlay requirements of most advanced devices, resist science, and technology proceed with material advancements and process enhancements to ultimately achieve the sensitivity and contrast required. In this paper, we report approaches of modifying a single layer resist system to achieve the characteristics of a bilayer resist system without the complexity of a multilayer process.The top surface of the single layer resist is made less sensitive to electron beam exposure and development effects. One of the methods used consists of desensitizing the top surface of a positive resist which operates on the chemical amplification principle, prior to exposure. The desensitization step is achieved by controlling the post‐apply bake condition during resist film preparation. Proper bake control of this resist provides the exposed regions with an initial dissolution rate which is three times slower than that in the resist bulk. This surface ...

We report on the integration of the lithography related issues necessary for the successful completion of 0.25 μm silicon and GaAs device programs: system configuration and modifications, electron beam/resist interactions, resist and process control, and proximity effect correction. In addition, extended device results will be presented for both device programs. We have successfully completed fully–scaled, all electron beam 0.25 μm NMOS and PMOS runs on silicon and mixed electron beam/optical runs on GaAs. Device performance parameters show linewidth control on silicon of 0.025 μm (3σ). GaAs devices with 0.15 μm gates and 0.25 μm ring oscillators with delays less than 17 ps/stage have been fabricated.