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Trigate 6T SRAM scaling to 0.06 µm2

Authors :
C.-H. Lin
Sebastian Engelmann
Vijay Narayanan
Isaac Lauer
A. Pyzyna
Chao Wang
Maxime Darnon
E. Sikorski
E. Kratschmer
Nicholas C. M. Fuller
Josephine B. Chang
John A. Ott
Martin M. Frank
Eric A. Joseph
J.J. Bucchignano
Y. Zhang
J. Newbury
W. Graham
B. To
Christian Lavoie
M. Guillorna
Lynne Gignac
D. Klaus
A. Bryant
Benjamin Joseph Fletcher
Cyril Cabral
S. Carter
Wilfried Haensch
Source :
2009 IEEE International Electron Devices Meeting (IEDM).
Publication Year :
2009
Publisher :
IEEE, 2009.

Abstract

We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 µm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated with planar devices [1].

Details

Database :
OpenAIRE
Journal :
2009 IEEE International Electron Devices Meeting (IEDM)
Accession number :
edsair.doi...........e0058c9ddbbe5f755174dd393948f999
Full Text :
https://doi.org/10.1109/iedm.2009.5424249