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This article deals with Si/Ge heterostucture manufacturing using covalent bonding, and its application to the layer transfer of a thin germanium film. At first, bow simulations of the heterostructure are discussed, in order to determine the temperature that should be used during bonding. Then, the covalent bonding process used to manufacture the heterostructure is described and characterized. At the end, a layer transfer process and observations of a thin germanium film are presented.

Background and aimsCatastrophic cervical spine injuries are rare in rugby union but require close monitoring. The aim of this study was to analyse the incidence of severe cervical spine injuries and determine the impact of a national prevention programme and new scrum rules implemented by the French Rugby Union.MethodsA prospective study was performed between 2006 and 2013 including all players affiliated to the French Rugby Union. All cervical spine injuries resulting in death, tetraplegia or a permanent neurological deficit were included. Prevention programmes were implemented from 2007 to 2013 and a change in scrum rules in 2010. To measure the impact of rule changes, results between 2006–2010 and 2010–2013 were compared using a Poisson regression.ResultsAltogether, 31 injuries were observed and the mean annual incidence was 1.6 per 100 000 players. There were significantly more injuries in senior players compared to junior players (3.5 vs 0.6 per 100 000 players; CI 95% (2.1 to 4.9) vs (0.1 to 1.0)). Incidence decreased from 1.8 in 2006 to 1.0 per 100 000 players in 2013 (pConclusionsThe incidence of catastrophic cervical spine injuries has declined in French Rugby Union. The implementation of specific prevention programmes and scrum law changes has notably resulted in a decrease in scrum injuries in forwards. This prospective study should be continued to monitor the future progression of injuries and adapt prevention programmes accordingly.

In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use of a hybrid Si-nc double-layer/SiN layer charge trapping stack. These devices show a good memory window in a Fowler-Nordheim (FN)/FN mode and a good retention (>; 3 V after ten years) with small activation energy (0.35 eV up to 200 °C), thus showing promise for future high-temperature memory applications. A model implying valence-band electron tunneling and a floating-gate-like approximation is used to explain the memory window improvement of the Si-nc double-layer memory devices.

The abundance of work on SiGe based devices demonstrates the importance of compositional characterization of such materials. However, SIMS characterization of SiGe layers often suffers from matrix effects due to non-linear variation of ionization yields with Ge content. Moreover, the presence of oxide in these layers would definitely increase the difficulty to obtain quantitative profiles by SIMS. We highlight here the improvements brought by the extended Full Spectrum protocol, presented in previous works and allowing minimization of matrix effects in SiGe matrices compared with more classic protocols. This results in more accurate depth profiles, and thus brings better comprehension of the behavior of intrinsic and doped layers under dry or wet oxidizing.

3D integration so far has often been investigated through a face to face point of view: the top die FEOL is in front of bottom die FEOL. This allows a dense connectivity between both dies, but TSV are mandatory on the bottom die for each external exchange. Another flow chart, which main application is identified as the Wide I/O, is “face to back”: the FEOL of the top die faces to the back side of the bottom dies. To communicate between top & bottom, interconnections then TSVs are needed. Advantage is that the bottom die, for Wide I/O the logic dies, faces directly to the board allowing a rapid communication with external. Also, the Wide I/O interface delivers high bandwidth at relatively low power consumption level. The objective of this paper is to show latest integration at Leti, both on 200mm & 300mm wafers, using face to back integration. If we compare both flow charts, using via middle technology, the main challenge consists of the temporary bonding. The temporary adhesive needs to be at least 50 μm thick, even more depending on staking technology on board, and in presence of the macro connection. The choice of the adhesive is crucial for the final stability of the stack during back side process and also during debonding, even more on 300mm wafers. Technical developments are introduced in the paper. A specific focus is done on temporary adhesive & the associated thermal stability of the stack. Impact of the temporary bonding on copper pillar is evaluated. Assembly of best processes for a full integration on daisy chain wafers, both 200 & 300 wafers is described. Finally, a comparison of electrical datas (resistance, capacitance, isolation) for both wafer diameters is given. Morphological characterization finalizes this first integration and leads to further potential improvements.

Three-dimensional (3-D) wafer stacking technologies are receiving an increasing interest, even if it poses forward new challenges in the development of through silicon vias (TSVs) and thin wafer handling technologies. Several approaches have been developed these years for wafer separation. Even if many examples can be found in literature of the slide-off debonding use for TSVs applications, the thermoplastic materials required for this technique could be limiting for future 3D backside processes. Therefore, innovative room temperature debonding process, including special carrier treatment, has been recently developed to enable a vertical carrier/device separation on a dicing frame at room temperature. The purpose of this paper is to demonstrate the feasibility of this innovative temporary bonding technique and associated equipments. In a first time we have compared 3 temporary materials stability in a short loop process representative of critical backside integration steps. From these results we identify ...

Electronic conduction through alumina used as a blocking layer for non-volatile memories is one of the fundamental limits for the downscaling of TANOS (TaN-Al"2O"3-Si"3N"4-SiO"2-Si) devices. Especially, it has been shown that the leakage current through Al"2O"3 that affects the memory retention characteristic is probably related to some trap assisted tunnelling. In this work we use atomistic calculations to find potential defects that could induce electronic levels inside the band gap of alumina.

Deals with (i) the growth and thermal stability of large number or periods SiGe/Si superlattices on bulk Si and (ii) the impact of B and P doping and of C alloying of SiGe on the growth kinetics of SiGe/Si superlattices.

In this paper, we evaluate the potentialities of hafnium-aluminates (HfAlO) materials as possible candidates for the interpoly dielectrics of future Flash memory devices. HfAlO layers of different thicknesses and compositions are integrated in single-layers and in Oxide/HfAlO/Oxide (OHO) triple-layer stacks, and analyzed in terms of coupling and insulating capabilities. We demonstrate that increasing the Hf content allows reducing the leakage current at high voltages but it results in a stronger leakage current at low voltages. We also show that once normalized in electric fields, the leakage current characteristics are independent of the high-k thickness. The electron conduction modes in these materials, at different temperatures, are also investigated. The activation energy increases with the Hf concentration in the HfAlO alloy, resulting in a higher leakage current at elevated temperatures. Finally, it is demonstrated that the conduction in triple-layer stacks is limited by a Poole–Frenkel conduction in the high-k layers, while the trap contribution in the case of single-layers becomes dominant when the HfAlO layer is thicker than 8 nm.

Thin (50 nm) erbium implanted silicon rich oxide films suitable for slot waveguides applications have been produced and studied by means of optical spectroscopy and structural characterisation techniques. Comparison between different deposition techniques in terms of light emitting properties of erbium ions is presented. Special attention is given to the efficiency improvement of the energy transfer from silicon nanoclusters to erbium ions where the type of annealing treatment is proven to be of crucial importance.

Optoelectronic properties of Er 3+ -doped slot waveguides electrically driven are presented. The active waveguides have been coupled to a Si photonic circuit for the on-chip distribution of the electroluminescence (EL) signal at 1.54 μm. The Si photonic circuit was composed by an adiabatic taper, a bus waveguide and a grating coupler for vertical light extraction. The EL intensity at 1.54 μm was detected and successfully guided throughout the Si photonic circuit. Different waveguide lengths were studied, finding no dependence between the waveguide length and the EL signal due to the high propagation losses measured. In addition, carrier injection losses have been observed and quantified by means of time-resolved measurements, obtaining variable optical attenuation of the probe signal as a function of the applied voltage in the waveguide electrodes. An electro-optical modulator could be envisaged if taking advantage of the carrier recombination time, as it is much faster than the Er emission lifetime.

An integrated erbium-based light emitting diode has been realized in a waveguide configuration allowing 1.54 μm light signal routing in silicon photonic circuits. This injection device is based on an asymmetric horizontal slot waveguide where the active slot material is Er3+ in SiO 2 or Er3+ in Si-rich oxide. The active horizontal slot waveguide allows optical confinement, guiding and lateral extraction of the light for on-chip distribution. Light is then coupled through a taper section to a passive Si waveguide terminated by a grating which extracts (or inserts) the light signal for measuring purposes. We measured an optical power density in the range of tens of μW/cm2 which follows a super-linear dependence on injected current density. When the device is biased at high current density, upon a voltage pulse (pump signal), free-carrier and space charge absorption losses become large, attenuating a probe signal by more than 60 dB/cm and thus behaving conceptually as an electro-optical modulator. The integrated device reported here is the first example, still to be optimized, of a fundamental block to realize an integrated silicon photonic circuit with monolithic integration of the light emitter. © 2013 IOP Publishing Ltd., This work was supported by the Spanish Ministry of Science through the project LASSI (TEC2009-08359), by the EC through the project ICT-FP7-224312 HELIOS and by Italy–Spain integrated actions. D N-U is grateful for the financial support of AGAUR through the Beatriu de Pinòs program.

This paper presents the prototype of a 3D circuit with Wide I/O interconnects in a 65nm CMOS node, assembled in a face-to-back integration and reported on a BGA. The process technology carried out for the realization of the bottom die will be presented in both 200mm and 300mm environment. Finally, the 3D assembly will be successfully assessed through electrical and reliability tests, concretising the realism of a 3D technology for future Wide I/O products.

International audience; In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows for the optimization of the compromise between high electron injection and limited consumption. Then, we show that scaling the dimensions of the select gate can induce a higher consumption, while scaling the memory gate leads to lower programming energy (

High quantum efficiency erbium doped silicon nanocluster (Si-NC:Er) light emitting diodes (LEDs) were grown by low-pressure chemical vapor deposition (LPCVD) in a complementary metal-oxide-semiconductor (CMOS) line. Erbium (Er) excitation mechanisms under direct current (DC) and bipolar pulsed electrical injection were studied in a broad range of excitation voltages and frequencies. Under DC excitation, Fowler-Nordheim tunneling of electrons is mediated by Er-related trap states and electroluminescence originates from impact excitation of Er ions. When the bipolar pulsed electrical injection is used, the electron transport and Er excitation mechanism change. Sequential injection of electrons and holes into silicon nanoclusters takes place and nonradiative energy transfer to Er ions is observed. This mechanism occurs in a range of lower driving voltages than those observed in DC and injection frequencies higher than the Er emission rate.

The electroluminescence (EL) at 1.54νm of metaloxidesemiconductor (MOS) devices with Er 3+ ions embedded in the silicon-rich silicon oxide (SRSO) layer has been investigated under different polarization conditions and compared with that of erbium doped SiO 2 layers. EL time-resolved measurements allowed us to distinguish between two different excitation mechanisms responsible for the Er 3+ emission under an alternate pulsed voltage signal (APV). Energy transfer from silicon nanoclusters (Si-ncs) to Er 3+ is clearly observed at low-field APV excitation. We demonstrate that sequential electron and hole injection at the edges of the pulses creates excited states in Si-ncs which upon recombination transfer their energy to Er 3+ ions. On the contrary, direct impact excitation of Er 3+ by hot injected carriers starts at the FowlerNordheim injection threshold (above 5MVcm 1) and dominates for high-field APV excitation.

International audience; In this work, split-gate charge trap memories with electrical gate length down to 20nm are presented for the 1 st time. Silicon nanocristals (Si-ncs), or silicon nitride (Si 3 N 4) and hybrid Si-nc/SiN based split-gate memories, with SiO 2 or Al 2 O 3 control dielectrics, are compared in terms of program erase and retention. Then, the scalability of split-gate charge trap memories is studied, investigating the impact of gate length reduction on the memory window, retention and consumption. The results are analyzed by means of TCAD simulations.

Thin erbium implanted silicon rich oxides films have been used as active layer in light emitting devices. Electroluminescence has been observed and analyses as a function of the silicon content.

We present the characterization of the nonlinear-dynamics of a CMOS-compatible horizontal-slot waveguide with silicon-nanocrystals, where the temporal behavior of the phase and amplitude of the nonlinear response are simultaneously monitored. These results are complemented with four-wave-mixing measurements.

The demand for optical circuits with integrated signal processing functions is pushing for the development of efficient and CMOS-compatible nonlinear optical elements.

In this work we investigate the correlation between hydrogen content and leakage current through the Al 2 O 3 layers of TANOS memories. We put in evidence that retention of TANOS memories is improved with the decrease of H concentration in the Al 2 O 3 layer. Using atomistic simulations consolidated by detailed Al 2 O 3 physico-chemical analyses, we find that interstitial H produces a midgap trap likely to participate to trap assisted conduction.

This paper presents the investigation of the electrical properties of charge-trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si 3 N 4 as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si 3 N 4 double layer, which shows reduced program/erase voltages, combined with 10 6 excellent endurance and good retention (Δ V T > 5 V after 10 years at 125 °C).

International audience; Alumina layers deposited by Atomic Layer Deposition followed by Rapid Thermal anneal were characterized. We found that the crystallization of alumina in γ-phase occurs between 700 and 850°C. Optical band gap, stress and density were found to increase upon crystallization Hydrogen content in alumina was characterized by ToF-SIMS and infrared spectroscopy. We found that annealing ambience has a strong influence on hydrogen concentration: oxygen favors hydrogen desorption from alumina. Finally, charge trapping in alumina was characterized by C(V) measurements. A strong correlation between hydrogen concentration and trapping was established.

Non-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges.Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2.In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM.

We studied the effect of RTP and furnace annealing on the transport properties and electroluminescence of Si-nc embedded in SiO2 layers, and of Er ions coupled to Si-nc. The light emitting devices have been fabricated in a CMOS line by implantation of Si and Er in SiO2. The results show that for the same annealing temperature, furnace annealing decreases electrical conductivity and increases probability of impact excitation, which leads to an improved external quantum efficiency. Correlations between phenomenological transport models, annealing regimes, and erbium electroluminescence are observed and discussed.

In this work, we use atomistic simulation, consolidated by a detailed Al 2 O 3 physico-chemical material analysis, to investigate the origin of traps in Al 2 O 3 (in particular, Al- or O-vacancies and H-interstitials). It is shown that the leakage currents through Al 2 O 3 layers, with different post-deposition anneals, are strictly correlated to the H content. Then, for the first time at our knowledge, the hydrogen-based trap features estimated by quantum simulations are introduced in a TANOS device simulator. A very good agreement is obtained between model and device experimental data, allowing for a clear understanding of the role of alumina H content on the retention characteristics of charge-trap memories.

This paper presents an in-depth investigation of the electrical properties of charge trap memories with AlN based storage layers. The memory performance and reliability are studied in details and compared with the ones of a reference device using standard Si 3 N 4 as storage layer. An engineered charge trapping layer is also proposed, made by an AlN/Si 3 N 4 double layer, which shows reduced program/erase voltages, combined with 106 excellent endurance and good retention (ΔV T ≫5V after 10 years at 125°C).

We report an ultrafast (

We present chemical vapor deposition of titanium nitride nanocrystals (ncs) on silicon nitride (SiN). Ncs are passivated in situ by a silicon shell and encapsulated in SiN. High density (3×1012 cm−2), crystalline and isolated ncs are observed by transmission electron microscopy and characterized by x-ray photoelectron spectroscopy. TiN ncs/SiN are integrated as charge trapping layer in a nonvolatile memory. Devices show large memory window (10 V) and fast erasing compared to devices using pure SiN trapping layer, explained by enhanced electrical field in SiN. Acceptable reliability in terms of cycling and data retention is also demonstrated.

Three different nitride-based trapping layers have been investigated: a standard silicon nitride, a Silicon-rich and an Oxygen-rich silicon nitride deposited by Low Pressure Chemical Vapor Deposition (LPCVD). First the physical properties of the films are studied. A gap of 5.3eV and a refractive index of 2.07 were found for the standard Silicon Nitride using spectroscopic ellipsometry. Excess silicon reduces the gap to 4.7eV and increases the refractive index to 2.24. Excess oxygen increases the gap to 5.8eV and reduces the refractive index to 1.84. Hydrogen content in the three layers was also investigated by infrared Multi Internal Reflection (MIR) Spectrometry and Time of Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Then electrical characterization was performed on the three different trapping layers in a SONOS structure. Program/Erase characteristics and data retention were tested in Fowler-Nordheim (FN) mode. Excess silicon improves erasing but degrades data retention while excess oxygen slows erasing characteristic but improves data retention.

In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics at high temperature is suggested.

Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard poly-Si floating gates, as improved data retention after endurance in particular at high temperatures [1][2], robustness toward oxide defects, two-bits per cell storage and full compatibility toward CMOS process. It has also been shown that coupling the Si-nc concept with high-k control dielectrics, by improving the gate coupling ratio, enables Fowler-Nordheim (FN) program/erase [3]. However, one of the key limitations of Si-nc memories is the limited memory window which is not suitable for multi-level memory applications. The use of two stacked Si-ncs layers to increase the number of trapping sites has been previously discussed in the literature with a SiO 2 control oxide [4]. In this work, we present memory devices with double stacked Si-nc layers and high-k (HfAlO-based) control dielectrics. We also propose to cover the 2nd Si-nc layer with a thin nitride layer (leading to an hybrid Si-nc / SiN memory structure [3][5]) in order to boost further the memory characteristics. We will show that these devices offer improved memory programming window both in FN regime [6] and in channel hot electron injection (CHE), which makes them compatible with NAND and NOR applications. Finally, a model involving valence band electrons from the top Si-ncs layer is proposed to explain the electrical results.

In this work, we explore the potential of Kelvin Force Microscopy (KFM) measurements to investigate the lateral charge transport in SiN layers with two different compositions (standard, std, and Silicon rich, Si–rich). The dynamics of the lateral spread of the trapped charge is analyzed with the help of three dimensional numerical device simulations.

In this paper, we have studied the charge trapping mechanisms of nitride-based non-volatile memories. The impact of different silicon-nitride (SiN) compositions (standard, std, and Si-rich) on the device characteristics has been investigated through material characterizations, electrical measurements, atomistic and electrical simulations. We found that the different physical nature of the dominant defects in the two SiN compositions is at the origin of the different device electrical behaviors. In particular, we argue that the different electron occupation number of the defect states of the two SiN materials explains the observed faster erasing speed and charge loss rate of Si-rich SiN devices, with respect to std SiN devices, in spite of comparable programming behavior. A simple trap model is proposed to improve state of the art simulators of SiN based memories.

We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called φ-Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The φ-Flash exhibits up to 1.8V ΔV Th between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.

International audience; In this work, we present an experimental and theoretical study of nitride-trap devices with a HTO/Al$_2$O$_3$ bi-layer blocking oxide. Such (Silicon/Alumina/HTO/Nitride/Oxide/Silicon) SAONOS devices are compared with standard (Silicon/HTO/Nitride/Oxide/Silicon) SONOS and (Silicon/Alumina/Nitride/Oxide/Silicon) SANOS memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed , which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.

In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid Si-nc double layer/SiN layer charge trapping media. These devices show a good memory window and good retention (>3 V after 10 years) with small activation energy (0.35 eV up to 200degC), thus being promising for future high-temperature memory applications.

The goal of this work is to give a clear physical comprehension of the charge loss mechanisms of SANOS (Si/Al 2 O 3 /Si 3 N 4 /SiO 2 /Si) memories. Retention at room and high temperature is investigated on different samples through experiments and theoretical modeling. We argue that at room temperature, the charge loss essentially results from the tunneling of the electrons trapped at the nitride interface, and the retention life time increases with the nitride thickness. On the contrary, at high temperature, the trapped charges in the nitride volume quickly redistribute, thanks to the thermal emission process, and they migrate to the nitride interface. Indeed, this result suggests that thin-nitride thicknesses in SANOS devices allow keeping a fast program/erase speed without degrading the retention at high temperature.

In this paper, we evaluate the potentiality of high-k materials (Al"2O"3, HfO"2 and HfAlO) for interpoly application in non-volatile memories. A study of the leakage currents of high-k based capacitors allowed to discuss the retention performances at room and high temperatures of high-k interpoly dielectrics. High-k materials are then integrated as control dielectrics in silicon nanocrystal and SONOS (Si/SiO"2/Si"3N"4/SiO"2/Si) memories. The role of the high-k layer on the memory performances is discussed; a particular attention being devoted to the retention characteristics. Analytical models, combined with experimental results obtained on various structures allowed to analyze the mechanisms involved during retention.

For the first time, we report a 3D stacked sub-15 nm diameter NanoWire FinFET-like CMOS technology (3D-NWFET) with a new optional independent gate nanowire structure named PhiFET. Extremely high driving currents for 3D-NWFET (6.5 mA/mum for NMOS and 3.3 mA/mum for PMOS) are demonstrated thanks to the 3D configuration using a high-k/metal gate stack. Co-processed reference FinFETs with fin widths down to 6 nm are achieved with record aspect ratios of 23. We show experimentally that the 3D-NWFET, compared to a co-processed FinFET, relaxes by a factor of 2.5 the channel width requirement for a targeted DIBL and improves transport properties. PhiFET exhibits significant performance boosts compared to Independent-Gate FinFET (IG-FinFET): a 2-decade smaller IOFF current and a lower subthreshold slope (82 mV/dec. instead of 95 mV/dec.). This highlights the better scalability of 3D-NWFET and PhiFET compared to FinFET and IG-FinFET, respectively.

In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed, focusing on their impact on memory performance and reliability. Then, a semi-analytical model is developed, which provides a good understanding of the physical mechanisms at the origin of program/erase characteristics.

The integration of silicon nanocrystal (Si-nc) nonvolatile memory (NVM) arrays with HfAlOx based interpoly dielectric (IPD) is presented for the first time. The data obtained on array vehicles programmed in Fowler-Nordheim operation regime are in excellent agreement with previously presented results on single cells, as well as theoretical data and allow the evaluation of the scalability of the Si-nc concept.

In this paper, we evaluate the potentiality of hafnium aluminium oxide (HfAlO) high-k materials for control dielectric application in non-volatile memories. We analyze the electrical properties (conduction and parasitic trapping) of HfAlO single layers and SiO"2/HfAlO/SiO"2 triple layer stacks as a function of the HfAlO thickness and Hf:Al ratio. A particular attention is given to the electrical behaviour of the samples at high temperature, up to 250^oC. Experimental results obtained on silicon nanocrystal memories demonstrate the high advantage of HfAlO based control dielectrics on the memory performances for Fowler-Nordheim operation. Then an analytical model is presented, to simulate the program erase characteristics in the transient regime and at saturation, depending on the high-k control dielectric properties. A very good agreement is obtained between the experimental data and the simulation results.

In this paper, we demonstrate the first successful integration of "localized SOI" devices integrated with HfO2/TiN gate stack on dedicated areas of bulk CMOS substrates. We propose a low cost innovative approach based on the SON technology, where the buried sacrificial SiGe layer can be removed directly from the edges of the active area in a self-aligned process, to form an entire fully-depleted structure isolated from the substrate. NMOS devices with gate length down to 32 nm are demonstrated on 6 nm Si-films, allowing the control of Ioff current down to 0.1 nA/mum for 440 muA/mum Ion @Vdd=1.1 V. We also demonstrated the impact of the TiN (as metal gate) thickness and compressive CESL (contact etch stop layer) boosters for ultra-thin film PMOS, allowing +15% and +22% additional improvement in performances, respectively. This localized-SOI approach is dedicated to low power devices where the leakage reduction is crucial. The possibility for power management is also demonstrated thank to the very thin buried dielectric and to the ground-plane implantations, allowing body factor as high as 80 mV/Von short devices.

International audience; In this paper we show for the 1 st time that Silicon nanocrystal (Si-ncs) memories with high-k (HfO2, Al2O3 and HfAlO) interpoly dielectrics (IPD) can offer excellent behaviour in the Fowler-Nordheim regime, with great relevance for future sub-45nm NAND memory generations. We significantly advance the state-of-the-art by showing a strict correlation between the different IPD properties (high-k dielectric constants, leakage currents) and the performance obtained on memory transistors down to 90nm gate lengths. In particular the results demonstrate that HfAlO IPDs combine the fast p/e and good 10 5 cycles endurance behaviour of HfO2 and the long retention of Al2O3 with no activation up to 125°C. Then, in order to boost the memory window, we also integrated a hybrid Si-nc/SiN layer floating gate, with a HfAlO based IPD. It is shown that a 6V Vth can be achieved, with good retention and cycling behaviours. Finally, a physical model of Si-nc memories is introduced which explains the impacts of IPD characteristics on memory performance. Introduction The large success of mobile equipment is leading to a dramatic increase of the market for NAND Flash, key devices for mass data storage [1]. Discrete trap memories, such as TANOS [2] and Si-nc memories [3,4] are one of the most suitable candidates to push integration density further beyond the 45nm node, because of their good scalability, robustness against SILC and low floating gate (FG) to floating gate coupling. In particular, Si-nc memories offer the potential of better data-retention at high temperature (the stored electrons being trapped in the Si-nc energy conduction band, rather than in temperature-activated deep traps of nitride), as well as mitigated lateral charge migration (the Si-ncs being isolated from one to the other by silicon dioxide rather than nitride). However, up to now, Si-nc memories have always shown poor FN program/erase characteristics, due to the small Si-nc/control gate coupling. In order to overcome this issue, engineering of the tunnel dielectric and/or IPD [5, 6] is necessary. In particular, in this paper, we present for the 1 st time to our knowledge an exhaustive experimental and theoretical study of Si-nc memories where the conventional HTO or oxide/nitride/oxide (ONO) interpoly dielectric is replaced by HfO2, Al2O3 or HfAlO based IPD. Excellent performance and clear correlations between the device electrical results and the IPD material properties are shown. We also suggest how to solve another issue of Si-nc devices, which makes them poorly interesting for multi-level NAND applications, i.e. the relatively small programming window. As a possible solution we propose the addition of a thin SiN layer over the Si-ncs, which allows for a significant increase of the memory window. Our approach is widely validated through in-depth analysis of Si-nc memories with HfO2, Al2O3 or HfAlO IPD, based on several material results, electrical data on memory transistors, physical modelling and TCAD three-dimensional simulations.

Complementary Metal Oxide Semiconductor (CMOS) down‐scaling leads to a dramatic reduction of the gate dielectric thickness for the isolation efficiency. The properties of hafnium aluminium oxide (HfAlO) are investigated as an alternative to conventional SiO2 as it exhibits the desirable characteristics of a high dielectric constant, a wide bandgap and good thermal stability with silicon. In this study, we show that complementary characterization techniques can be used to tune the deposition parameters to get optimized high‐κ dielectrics since the advanced capabilities of the characterization protocols and configurations allow analysis of few nanometer thick layers.

Slot and sandwiched waveguides with silicon nanocrystals were fabricated by means of industrial microelectronic tools, including DUV lithography. Low loss of 4 dB/cm will pave the way to compact all-optical NOR logic gates.

In this work, the authors evaluate the potentialities of HfAlO materials as possible candidates for the interpoly dielectrics of future flash memory devices. HfAlO single-layer and oxide/HfAlO/oxide triple-layer stacks were processed and analyzed in terms of coupling and insulating capabilities. The electron conduction modes in these materials, at different temperatures, were also investigated. Finally, by means of analytical models matched with experimental data, the authors extrapolate the programming characteristics of future flash memory nodes integrating HfAlO as interpoly dielectrics

In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the storage layer and the memory performances. The obtained results clearly demonstrate the high interest of HfO2 dielectric as possible storage layer of future NROM-like memory devices.