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Although advances have been made in modulation of host inflammatory response in periodontal therapy, it is important to control the bacterial challenge to the host immune system through conventional therapy and improvement of personal oral hygiene. Although toothbrushing is generally performed, interdental cleaning is not as common. This study compared the use of dental floss to a toothpick holder in the improvement of gingival health.Participants were examined and those with clinical gingivitis or slight chronic periodontitis were included in the study. O'Leary plaque, interproximal plaque index (IPI), and Eastman interdental bleeding index scores (EIBI) were recorded at baseline and following appointments. Forty-two females and 13 males ranging from 18 to 50 years in age were randomly divided into either a dental flossing group or toothpick holder using group. Each was given instructions in the use of the oral hygiene device and examined 2, 6, and 12 weeks following baseline. At 12 weeks, 27 floss users and 20 toothpick-holder users completed the study.Plaque scores were reduced in both groups as the study progressed. Mean O'Leary plaque scores decreased significantly for both methods from baseline to week 12 (P0.05). The EIBI and IPI scores decreased in mean scores over time for each method (P0.05). A correlation was found between the O'Leary plaque index and the IPI scores (P0.05).The results of this study found that the use of dental floss or toothpick holder resulted in no significantly different effect in the improvement of gingival health.

A method of simultaneously fabricating MESFETs with a maximum frequency of oscillation (f/sub max/) of 70 GHz and Schottky diodes with a gain-bandwidth product (f/sub T/) of approximately=2300 GHz to produce a 60-GHz mixer is given. A deep selective n/sup +/ implantation for a buried n/sup +/ zone under the mixer diode was used. Metalorganic chemical vapor deposition (MOCVD) was used for the growth of the active n layer and an n/sup +/ surface contact layer. The MESFETs and the diodes were both fabricated with a recessed Schottky contact structure using Ti-Pt-Au metallization. Arrays of 30 different diodes and 55 different MESFETs were fabricated to study the process technology and to get optimum devices for a receiver chip containing a diode balanced mixer plus a low-noise intermediate-frequency (IF) amplifier. The conversion loss and noise figures of the diodes were measured and compared with those obtained from computer simulations. Both large- and small-signal analysis are included. The 60-GHz balanced mixer chip shows a conversion loss of 6.0 dB and a double-sideband noise figure of 3.3 dB. >

On the basis of a recently developed GaAs technology that allows the realization of millimeter-wave Schottky mixer diodes and MESFETs on the same monolithic chip, 94-GHz monolithic mixers have been fabricated. The Schottky diodes show cutoff frequencies of up to 2.3 THz, whereas MESFETs with typical F/sub max/ (MAG=1) of about 90 GHz have been measured. The mixer chips show conversion losses of less than 8 dB combined with noise figures below 6 dB (DSB); the best values are a conversion loss of 7.5 dB with an associated noise figure of 4.0 dB (DSB) in self bias operation. The associated LO power consumption was 5 dBm. The technology allows the integration and mass production of several key components on one chip, which are necessary for millimeter-wave receiver frontends. >

Be and Cd ions were implanted into n-Ga0.47In0.53As. SIMS profiles show in both cases a high diffusion towards the surface during the annealing procedure. In addition, Be exhibits a significant diffusion into the bulk crystal which depends on the capping layer. A Si3N4 cap leads to a higher residual Be concentration in the implanted region. Damage caused by As implantation reduces the indiffusion remarkably. An electrical activation of about 50% of the implanted Be atoms could be achieved, whereas even annealing temperatures of 800°C activated only a small part of the Cd atoms. I–V characteristics of Be p-n diodes showed abrupt junctions with ideality factors of about 1.6. Cd diodes exhibited a soft breakdown and ideality factors of 2.

A technology is described which allows the monolithic integration of millimeter-wave Schottky diodes and MESFETs on one chip. The Schottky diodes have a cutoff frequency f/sub T/ of 2300 GHz. A monolithic 60-GHz mixer chip using these diodes shows a conversion loss of 6 dB and a noise figure (DSB) of 3.3 dB. The MESFETs have an f/sub max/ up to 70 GHz. A two-stage IF amplifier realized with this technology shows a gain of 20.6 dB and a noise figure of 1.7 dB at 4 GHz. >

On p-type Ga 0.47 In 0.53 As LPE-grown layers, Schottky diodes were fabricated with different metals and surface preparations. On chemically etched surfaces, diodes with ideality factors near unity but rather low breakdown voltages with soft breakdown were achieved. The barrier heights were between 0.4 and 0.7 eV depending on the work function of the metal. On sputter-cleaned surfaces the diodes exhibited high breakdown voltages and barrier heights of about 0.7 eV independent of the metal. Annealing of the diodes at 320°C resulted in reduced series resistances and barrier heights in the case of sputteretched surfaces. The junction seems to consist of two different barriers; the lower one is determined by an As segregation at the interface, whereas the higher one is caused by traps which are induced by the sputter process.

Optical, crystallographic, and transport properties of nominally undoped n‐type and Zn doped p‐type Gax In1−xAs /InP (0.44

Ohmic contacts of Au and Ag based Zn containing alloys on p -type Ga 0.47 In 0.53 As have been studied using intermediate layers of Ti and Ni, respectively. Low specific contact resistance in the order of 10 −5 Ωcm 2 are achieved. In case of AuZn alloy, the Ti intermediate metal layer causes higher contact resistances together with a worse contact morphology in contrast to Ni intermediate layers. However for AgZn contacts Ti adherent layers improve the contact resistances, especially for lower alloying temperatures. Moreover these contacts exhibit significant smoother interfaces as revealed by TEM micrographs. Thus AgZn contacts apply best to low resistive contacting of very thin p -layers forming e.g. the base of a ballistic device.

Two topics in the liquid-phase epitaxy of lattice-matched Ga 0.47 In 0.53 As layers on InP were studied. First, the addition of PH 3 to the H 2 ambient to prevent thermal decomposition of the substrates can be optimized to obviate the incorporation of P into the ternary layers. Secondly, Mg was used as an acceptor in both InP and GaInAs which was found to exhibit a smaller diffusion coefficient and activation energy, as well, as compared to Zn.

The activation efficiency of conventional furnace annealing (550–750 °C, 30 min, capless, AsH3/H2 ambient) and rapid thermal annealing (800 °C,∼1 s, SiO2 cap, N2 ambient) has been compared in Be‐doped Ga0.47In0.53As by investigating the carrier profiles and the atomic profiles. Nearly complete activation (100%) occurs during both 750 °C furnace annealing and rapid thermal annealing for an implanted fluence of 6×1013 Be ions/cm2. At a fluence of 6×1014 Be ions/cm2 a significantly higher activation (>50%) is found after rapid thermal annealing as compared with furnace annealing (30%) mainly due to out‐diffusion of Be during furnace annealing. Low‐temperature photoluminescence (2 K) revealed that comparable recrystallization is achieved in both methods. A high diffusivity of Be is apparent in the atomic depth profiles after furnace annealing. However, only insignificant redistribution is noticeable after rapid thermal annealing, probably due to gettering of the diffusing Be by defects.

The specific contact resistance ρ c of Ni/Au-Ge/Ni and Ni/Au-Sn/Ni layers on n-GaInAs and Ni/Au-Mg/Ni and Ni/Au-Zu/Ni on p-GaInAs are measured for different alloying temperatures and times using an extended transmission line model. Specific contact resistances of 4.10-8Ω cm2for Ni/Au-Sn/Ni on n-GaInAs (n = 1018cm-3) and 2.10-5Ω. cm2for Ni/Au-Zn/Ni on p-GaInAs (p = 1018cm-3) are obtained. After deposition at room temperature, the barrier height of the metal-n-GaInAs system was determined to be 0.16 eV, decreasing below 20 meV after heat treatment. Interdiffusion of metal and semiconductor was investigated by SIMS/Auger measurements. At alloying temperature of 300°C the contacts show fast diffusion of Au relative to the dopants, effecting an increase of the specific contact resistance.

A DLTS-system with largely improved performance has been realized: dC min = 13·10 -18 F >, reponse time = 5 μ s, dC/C o = 3·10 -8 . The influence of different s.i. GaAs substrate materials on the quality of epitaxial layers is assesses. Depth profiles of deep levels in GaAs Schottky diodes caused by the gate metallization are measured with a depth resolution better than 10nm. A deep acceptorlike trap at E y +150meV is discovered in thin In 0.53 Ga 0.47 As layers grown on Fe-doped InP. The trap is most probably caused by outdiffusion of Fe from the substrate.

Ga0.47In0.53As JFETs and MESFETs have been fabricated with a lattice-mismatched GaAs layer under the gate. The GaAs could be grown with good electrical and crystallo-graphic quality in spite of the large lattice mismatch by an OM-VPE process. Pn, Np and Schottky diodes were fabricated and applied to n-GaInAs FET channels. Both types of devices exhibited high transconductances of about 100 mS/mm.

Two deep traps in Ga0.47In0.53As/InP:Fe at a depth of 110 meV and 150 meV, respectively, are observed for the first time using low‐temperature photoluminescence and deep level transient spectroscopy. The dependence of luminescence intensity on the growth process itself (liquid phase epitaxy, vapor phase epitaxy, and metalorganic chemical vapor deposition) and its parameters (growth temperature, layer thickness) and the substrate doping is reported and leads to the unambigous identification of the 150‐meV acceptorlike trap as being caused by Fe impurities. Fe diffuses from the substrate to the epitaxial layer during the growth process. This outdiffusion is less pronounced for layers grown at lower temperature. The level at 110 meV which is also observed in layers grown on InP:S substrate is tentatively assigned to an intrinsic defect of Ga0.47In0.53As.

CVD SiO 2 has been used as gate insulator for GaInAs n-channel inversion-mode MISFET's. By applying a rapid thermal annealing cycle with a maximum temperature of 700°C, the number of fast interface states could be strongly reduced, thus leading to stable device performance in the time range between 10-6and 10 s. The drain current drift for longer times, however, is not affected by the annealing step. A reduction of the dielectric deposition temperature down to 250°C, however, results in improved long-term stability with a drain current decrease of only 5 percent after 104s of operation at room temperature.

The fabrication of Be-implanated Ga0.47In0.53As p-n diodes is described. After annealing the diodes exhibit saturation current densities of 1.5×10−4 A/cm−2 and an ideality factor of 1.6. The built-in voltage of 0.7 V demonstrates the feasibility of their application to electronic devices. SIMS and C/V measurements are consistent with theoretical data.

GaInAs JFETs were fabricated on VPE-grown GaInAs layers. The pn junctions have been realised with Be ion implantation and rapid thermal annealing. The devices show a high transconductance of 130 mS/mm and an electron saturation velocity of 1.8 × 107 cm/s. Channel mobilities measured at the complete device are as high as 6800 cm2/Vs. These excellent device properties are due to the use of an undoped InP buffer layer which avoids the diffusion of Fe from the substrate into the active layer. The data were supported by S-parameter measurements which gave a frequency limit of 20 GHz for gate dimensions of 1.6 by 200 ?m2.