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In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

International audience; A new protocol based on Y-function is used for accurate statistical extraction of electrical parameters of High Electron Mobility Transistor (HEMT) devices for GaN technology. This protocol presented here is used for extraction of relevant electrical parameters such as oxide capacitance, threshold voltage, effective mobilities and access resistance. This study has been verified over a large range of channel lengths for two normally-off HEMT GaN wafers having different levels of access resistances.

Device aging induced variability remains a major hurdle to microelectronics. To limit its impact circuit designers need effective & accurate degradation models to be implemented in the industry-grade reliability simulators. Despite remarkable efforts in characterizing and modelling Bias Temperature Instabilities, the devices are scarcely tested under realistic stresses actually endured by the device inside a functioning circuit, as done in this work. Besides, we propose an original approach to calibrate the Capture/Emission Times map given as an entry to the RC model of BTI degradation. Simulated degradations are in good agreement with measurement not only for AC and DC stresses but also for arbitrary patterns.

In this study, we investigate the difference between I D (V G ) and C(V G ) pBTI shifts on GaN-on-Si E-mode MOS-channel HEMTs, under various gate voltage stresses (V GStress ) and temperatures (T). A new experimental setup using ultra-fast and simultaneous I D (V G ) and C(V G ) measurements enables to monitor the threshold voltage V TH drift through two metrics, $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ . Experimental pBTI results depict a difference between $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ , such as $\mathrm{\Delta}\mathrm{V}_{\text{THI}} . TCAD simulations support that ID(V G ) shift ( $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ ) is related to charge trapping in Al 2 O 3 gate oxide defects at the gate corners regions while C(V G ) shift ( $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ ) is mainly ascribed to the gate bottom, due to the presence of a back-barrier layer in the epitaxy. These previous results enable to deduce that the Al 2 O 3 defects density is more important at the gate corners than at the gate bottom.

In this paper, threshold voltage V TH instabilities under positive gate voltage stress (V GStress ) are thoroughly investigated on GaN-on-Si Enhancement-mode MOS-channel HEMTs. An analysis of pBTI transients performed at several V GStress and temperatures (T) reveals two trap populations close to the Al 2 O 3 /GaN interface namely (1) C N acceptors in the GaN substrate, and (2) defects in the Al 2 O 3 gate oxide. Both trap populations lead to V TH instabilities via different underlying mechanisms as evidenced by TCAD simulations. At V GStress TH drifts are ascribed to C N traps ionization localized at 0.8-0.9eV above the valence band (E v ). At higher VGstress, electron trapping also occurs in Al 2 O 3 defects leading to stronger V TH degradation. DC & AC pBTI transients have been modeled using Capture Emission Time (CET) map approach, which allowed the identification of both trap populations. Temperature-dependent CET maps extraction reveals a strong activation of C N traps with temperature, and confirms Arrhenius analysis consistency. This study provides a deep understanding of BTI reliability in GaN-HEMT technologies.

We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m matching, $A_{v0}=62dB$ gain (L=200nm), $f_{T}=126GHz$ cut-off frequency and $f_{MAX}=182GHz$ maximum operating frequency (L=35nm). Junction Less transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hotcarrier degradation and fMAX. This is explained by junction less physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split- CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

A robust and low cost Si RFSOI Power Transistor which can deliver +31dBm output power with 74% of Power Added Efficiency (PAE) and 18dB of Gain has been optimized for 4G & 5G sub-6GHz Power Amplifier (PA). By means of innovative characterizations combining RF aging tests and modeling, it is proved that this great performance can be achieved while maintaining a very high level of reliability of the PA transistor.

This paper presents a study of the physicochemical and the dielectric characteristics of capacitor structures, with an organosilicate polymer fabricated by initiated chemical vapor deposition as dielectric. The polymer evaluated is the poly(trivinyltrimethylcyclotrisiloxane), and a comparative study on different bottom electrodes was performed. Preliminary results demonstrate that iCVD technique permits the deposition of low roughness, low defect and uniform polymer films, and the dielectric fabricated exhibits a high breakdown field and an original dielectric behaviour, which makes it a prominent candidate for high voltage 3D capacitors.

International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a 50mV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) $0.078\mu \mathrm{m}^{2}$ SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at $V_{DD}=0.8\mathrm{V}$ and a reduction of minimum operating voltage $V_{min}$ by 60mV at $6\sigma$ w.r.t. planar SRAMs.

Thermal conductivity (kth) of Ge-rich Ge-Sb-Te phase-change material (GGST) is here investigated at temperatures up to $400\ ^{\circ}\mathrm{C}$ through “3ω method”. We present the engineering of the test vehicle, with the optimization of the metal-based heater to achieve a reliable measurement even at high temperature. Finally, we compare the results from four different approaches, showing which method is more accurate for the kth evaluation in phase-change materials.

In this paper, we investigate the influence of negative gate stress on threshold voltage V TH instabilities in GaN-on-Si devices. This study has been carried out by using ultra-fast Measurement-Stress-Measurement (MSM) procedure on GaN-on-Si E-mode MOSc-HEMTs (Enhancement-mode MOS-channel HEMTs) for different gate lengths L G . NBTI transients at different temperatures and complementary ToF-SIMS analysis reveal the influence of two trap populations involved on V TH instabilities, both of them are related to the C N acceptor traps. The first one is close to the interface between GaN and Al 2 O 3 gate oxide due to N-vacancies induced by the dry etching process, the second one is likely to be related to GaN:C layer. NBTI transients also exhibit a dependence with L G , which is consistent with the E-field distribution of the gate region obtained by TCAD simulations at different gate stress voltages, and confirm the proximity of a C N trap population to the gate oxide.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage Vmin by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs.

International audience; In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).

This paper presents a review of interconnect challenges for sub 65 nm node. From this generation, porous ultra low K (ULK) dielectric materials (dielectric constant k < 2.1) are required. Their porosity makes integration very difficult, due to the mechanical weakness and process interaction issues (especially during stripping, CVD metal barrier deposition...). To overcome these process incompatibilities and keep the 'effective dielectric constant' low, dual damascene architecture becomes more and more complex and requires additional steps (porosity sealing treatment, degas steps, supercritical CO2 clean, low k dielectric barrier, self aligned barrier...). Possible contamination trapped in the porosity (moisture, metallic residues...), and lower thermo-mechanical properties of ULK will probably impede reliability. Copper resistivity increase with dimension shrinkage will also be an extra issue.

In this work, we present a new memory device concept, named the multi-tunnel-junction (MTJ) memory, which uses a thin silicon nanocrystals layer embedded between two ultra-thin oxides as charge injector medium. We show that this device offers low programming voltages and fast writing/erasing characteristics. A simple characterization method, suitable for nanosecond range phenomena characterization and overcoming the limitation of the classical electrical characterization tools, has been also developed. This method allows us to characterize the dynamic behaviors of the MTJ devices.

Today, copper and low-k dielectric are required to reduce interconnect delay and decrease parasitic capacitance. This paper presents the integration of copper with an organic low-k dielectric (k = 2.7) and is focused on the adaptation of the processes required when switching from SiO2 to this pure organic dielectric. After integration in a dual metal level interconnect for 0.12-µm generation, it is shown that good electrical results are obtained (100% yield for 0.4-µm pitch, via resistance > 1 Ω, capacitance reduction of 40% compared to Cu/SiO2 structures), but care must be taken when integrating this low-k material due to its low thermo-mechanical property and sensibility to moisture absorption.

An easy-to-fabricate, low-cost, sidewall TiN/HfO 2 /Ti vertical resistive RAM (VRRAM) device is proposed. Devices with bottom electrode thickness down to 10nm were fabricated and characterized. Forming, SET and RESET voltages of respectively 2V, 0.5V and −0.5V were measured. A stable memory window of one decade was maintained after 105s at 200°C. The impact of scaling on the operating voltages and memory resistance levels was evaluated, showing a SET and RESET voltage reduction as the cell diameter is reduced. Finally the cycle-to-cycle resistance variability was addressed.

session 5D: circuit aging simulation/circuits reliability; International audience; In this paper, we develop a new “recovery free” measurement technique able to apply arbitrary NBTI stress patterns of `1' & `0' on the gate of the transistor. This technique is very useful to evaluate the BTI degradation seen by the device in circuit conditions. With this method, it is shown that the NBTI shift does not depend on the bit arrangement within a sequence for bit length

In this paper, we investigate the high temperature behavior of oxide-based conductive bridge memories. A methodology to optimize both high and low resistance states stability is presented. A numerical model is developed able to simulate the filament dissolution over time. This allows us to establish a clear correlation between the filament morphology and the ON/OFF states stability. It is shown that the optimization of the memory programming conditions leads to a stable memory window up to 250°C.

In this work, we present an experimental and theoretical analysis of scaled (down to 10nm) Al2O3/CuTeGe based CBRAM. We focus on the understanding of the physical mechanisms responsible for the failure of high and low resistance states at high temperature. Using a numerical model combined with ab-initio calculations, we elucidate for the 1st time at our knowledge the role of the filament morphology on the resistance instability. We demonstrate that an optimized filament shape (tuned by adjusting the operating conditions) significantly improves the memory window stability at high temperatures.

The ever increasing demand for high performance integrated devices results in more and more low dielectric constant materials being proposed to replace silica for interconnects insulation. We present results concerning two organic materials (Flare and SiLK) and one mineral (porous silica). These materials present good dielectric characteristics when dry, i.e. they have a very low leakage current and a long breakdown time to failure. However, moisture uptake weakens their characteristics. The leakage current is increased, but generally not in a crucial manner. More critical is the drastic decrease of the breakdown time to failure. This sensitivity must be taken into account both in wafer encapsulation design and during the process of eliminating residual moisture before encapsulation of each low- k material layer.

Resume Les phages sont reconnus depuis longtemps comme la principale cause de ralentissement de la croissance des lactocoques composant les levains de fromagerie. La selection de souches naturelles ou mutantes particulierement resistantes aux phages ne permettant pas un controle optimum des fabrications, une nouvelle approche a ete envisagee apres analyse des mecanismes de resistance aux phages naturellement presents dans les souches. Il s'agit de construire des souches plus resistantes aux phages par accumulation de plusieurs mecanismes de resistance dont les effets s'additionnent. Une telle approche necessite l'isolement et la caracterisation de mecanismes varies de resistance aux phages. Nous resumons ici le clonage et la caracterisation des genes codant pour 3 mecanismes d'infection abortive. Les cibles de ces 3 mecanismes ont ete localisees sur l'ADN d'un phage. Deux d'entre elles ont ete clonees et sont en cours de caracterisation. L'etude de l'interaction entre les genes codant pour ces mecanismes de resistance et leur cible sur le phage devrait nous apporter les connaissances necessaires pour un choix rationnel des mecanismes a utiliser.

International audience

We hereby present for the first time a successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGe pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells. Various Ge contents and growth templates (unstrained or strained SOI) were screened in order to optimize the trade-off between threshold voltage adjustment with a single metal gate and strain-induced mobility enhancement. In particular, we reach 106% mobility boost for nFETs on sSOI and 70% for co-integrated pFETs on Si 0.6 Ge 0.4 /sSOI, compared to SOI (E eff =0.6MV/cm). Moreover, the symmetrically low V th,n and V th,p result in −39% propagation delays improvement compared to SOI at 0.9V supply voltage.

4µm wide copper Through Silicon Vias (TSV) were processed on underlying 65nm CMOS devices and circuits in order to evaluate the impact of the three-dimensional (3D) integration process. Electrical tests on isolated MOSFET and ring oscillators in the presence of TSVs are compared to modeling results. Beside TSV mechanical impact, an electrical coupling between TSV and MOSFET is experimentally quantified and reported for the first time. This coupling induces a spike variation up to 7µA/µm on the static NMOS drain current. However, the ring oscillators response is not impacted.

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V T -variability performances are obtained (A VT =1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V DD =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ SNM DD =0.7V. We also demonstrate ultra-low leakage ( G = 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

We investigate for the first time the experimental performance of strained silicon directly on insulator (sSOI) for short and narrow FDSOI NMOS transistors integrated with a TiN/HfO2 gate stack. A +16% drive current improvement is reported for a 25nm gate length (among the best ever reported for short substrate-induced strained devices). Through in-depth electrical characterization and mechanical simulations, transition from bi-axial to uni-axial strain is evidenced in extremely narrow sSOI channels, with a 40% mobility enhancement for 35nm wide devices. This highlights that the strain is not lost at sub-40nm dimensions

International audience; The cross-plane thermal conductivity of Ge$_2$Sb$_2$Te$_5$, either in its amorphous state or fcc crystallized state, and titanium nitride (TiN) thin films has been measured at room temperature by the 3 omega method. These materials are involved in the fabrication of phase change random access memory (PC -RAM) Ge$_2$Sb$_2$Te$_5$ and TiN being the PC and pseudoelectrode materials, respectively. The thermal conductivity of insulating SiO$_2$ and ZnS:SiO$_2$ layers was determined too. Each thermal conductivity measurement was performed by the means of at least two strip widths in order to check both the measurement self-consistency and the measurement accuracy. The performance of PC-RAM cells, i.e., the time needed to reach the melting temperature of the PC material and the cooling speed, has been evaluated as a function of both the measured thermal conductivity of the PC material and the reset current intensity independently of the thermal properties of the pseudoelectrodes by the way of analytical formula. The influence of the thickness and the thermal properties of the pseudoelectrodes on the performances have been determined by numerical simulations.

The beneficial effect of double SiGe:C diffusion barriers for CMOS device downscaling is clearly demonstrated. The diffusion barriers enable to finely tailor the doping profile both in the channel and S/D regions. A drastic reduction of short channel effects down to 35nm gate length and improved I/sub on//I/sub off/ compromise have been achieved with a double carbonated barrier architecture for both nMOS and pMOS. For pMOS, reduced junction depth and lower S/D region sheet resistance are achieved with highly LDD and HDD retrograde doping profiles thanks to limited boron diffusion. For nMOS, we evidence that carbonated epi multi-layers suppress the boron pockets diffusion and therefore the roll-off effect in short gate length devices due to localised over-doping.

The combination of porous ultra low k dielectric and copper metallization is an attractive alternative to meet the requirements of ITRS roadmap concerning the 65 nm interconnection technology, but very little is known about the reliability of such an approach. Porous materials are usually unstable and sensitive to moisture, but pore sealing is a possible strategy to overcome these detrimental effects. In this paper, we have studied the effect of pore sealing on the electrical performance and long-term reliability of ULK/Cu interconnects. The best pore sealing efficiency is obtained for a nominal thickness of 10 nm of a SiC:H sealing layer. With these conditions, the dielectric constant of the ULK is kept at 2.2 even after integration and an electromigration activation energy of 1.2 eV is obtained. The failures mechanisms have been correlated to SEM and FIB analysis.

We investigated the capacity of Royal College of Surgeons (RCS) rat retinal pigment epithelial (RPE) cells to take up all-trans-retinol (ROL) (vitamin A) and to metabolize it into retinyl esters (RE). Cultures of RPE cells were established from RCS and control newborn rats. All-trans-ROL was delivered to the apical surface of the RPE monolayer. Retinoids were analyzed by high-performance liquid chromatography. The cellular retinol-binding protein type I (CRBP-I) was assessed by Western blotting. Before supplementation with ROL, RE were lower in RCS rats. After ROL supplementation, esters increased and reached values that were similar in the two strains, but the increase, expressed relative to the initial value, was higher in RCS rats. The uptake of ROL and the level of CRBP-I were greater in RCS rats. Our results provide evidence of a functional retinol esterifying enzyme in cultured RCS RPE cells and suggest that CRBP-I could play a role in the uptake and esterification of ROL in the RPE cells.

Understanding of electrical and physical copper behavior in dielectric materials is required for efficient analysis of copper contamination reliability issues. This work is based on temperature and bias-temperature stressing of copper-gate MOS capacitors, which allow both capacitance-voltage and leakage current analysis. Electrical results are consistent with SIMS analysis and provide a physical basis for studying interconnect reliability with respect to copper contamination.

In this paper a new interconnect capacitance measurement method with a sub-attoFarad (

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS has been demonstrated for partially-depleted (PD) devices (Leobandung et al., 1998). Propagation delay versus active power can be greatly reduced by using fully-depleted (FD) devices, because threshold voltage (V/sub t/) and junction capacitance (increased by halo implant in case of bulk and PD devices) are lower. However, this advantage is possible only if transconductance is not degraded by high S/D resistance and if SCE and DIBL are well controlled, essentially by reducing silicon thickness. Furthermore, sensitivity of electrical parameters to silicon thickness (tsi) for FD devices is often mentioned as a critical process issue due to SOI substrate thickness nonuniformity. In this paper, we show (with both 2D simulations and measurements) that V/sub t/ control can be improved by a low energy S/D implant for enhancement-mode (EM) devices. S/D resistance can also be maintained at a low enough level by using a recessed-channel process, which allows the proper reduction of tsi exactly under the gate (Raynaud et al., 1998). Using a TiSi/sub 2/ salicide process on gate and elevated S/D regions, we have measured a maximum oscillation frequency f/sub max/ of 48 GHz at 0.9 V for 0.25 /spl mu/m NMOS. Finally, we show that, due to a balance between different physical effects, the distribution of critical parameters for digital applications (saturation and off currents, propagation delay and power consumption) is not degraded by silicon thickness nonuniformity.

In this paper, a new method (ARPIC: automatic representation of patterns for interconnect characterization) of interconnect capacitance characterization is shown. ARPIC is a matrix of 1606 patterns containing the most frequent capacitive loads existing in a design. Its main purpose is to calibrate a simulator. A very good fit is obtained between measurements and simulation for a state-of-the-art 0.18 /spl mu/m CMOS process with low-k dielectric, and we demonstrate that the ARPIC method can characterize interconnect capacitance with 0.1 fF resolution.

Silicon Charge Couple Devices are the main components for visible and infrared imaging. The behaviour of these components has been studied under photon radiations (total dose and dose rate radiations) and neutron radiation. Infrared readout circuits have been tested in storage condition at 300 K and in operating condition at 77 K. The different simulation facilities, test facilities and main results are presented. This evaluation is the first step to hardening. >

To investigate the functional protective effect of a synthetic (dimethylthiourea, DMTU) and a natural antioxidant (Ginkgo biloba extract, EGb 761) against light-induced retinal degeneration.Wistar rats were exposed for 24 hours to 1700-lux light after treatment with DMTU or EGb 761. Electroretinograms were recorded before and on day (D)1, D3, D8, D15, D22, and D29 after light exposure. The b-wave amplitude was plotted against log L (ganzfeld luminance), providing the b-wave sensitivity curve. The Naka-Rushton function fitted to the sensitivity curve enabled derivation of the parameters Bmax (saturated amplitude) and K (luminance-inducing Bmax/2). In addition, rats from each group were killed for retinal morphometric analyses.In the untreated group, light exposure caused collapse of the b-wave sensitivity curves. Bmax was reduced by 51% at D1 without subsequent recovery. K increased temporarily, reverting to normal values 8 days later. The outer nuclear layer thicknesses decreased markedly in the superior retina. In the treated groups, light exposure had a weaker effect on sensitivity curves. The values of Bmax were not significantly different from those in the unexposed-untreated group, although K increased temporarily. Retinal morphometry was preserved.Dimethylthiourea and EGb 761 afford functional protection against light-induced retinal damage.

ERG responses were measured as a function of Ganzfeld luminance to evaluate functional damage induced by light on rat retinas.Wistar rats were exposed to a fluorescent light of 1700 lux for 12 h, 24 h, 48 h and 72 h. We recorded ERGs before and one night after exposure, then 3, 8, 15, 22 and 29 days later. The b- and PIII-wave amplitudes were plotted against luminance for each group at each recovery time.The retinal damage induced by a pupillary illuminance of 1700 lux ranged from low to severe as exposure duration increased from 12 h to 72 h, respectively. We observed an effect immediately after light exposure but no improvement during the recovery period. The b-wave amplitude was reduced by 40, 60, 80 and 90 percent after 12, 24, 48 and 72 h of light exposure, respectively; the PIII-wave amplitude was reduced by 30, 40, 70 and 90 percent after these respective exposures. The Ganzfeld luminance eliciting a 50 microV b-wave amplitude increased significantly with exposure duration, but the luminance eliciting the maximal b-wave amplitude was not dependent on this duration. Hence we suggest that the ERG decrease is due to a reduction in photoreceptor number.We present a full analysis of the electrophysiological parameters recorded from light-exposed or non-exposed rats. This model is a useful tool to study in vivo retinal degeneration.

Several investigations have recently shown that the retina is very sensitive to oxygenated free radicals (O2-, OH.) at the origin of the membrane phospholipids peroxidation. Peroxy radical (ROO.) release is responsible for the induction of electrophysiological disturbances leading to retinopathy development. As Ginkgo biloba extract (EGb 761, IPSEN, France) was reported to scavenge primary (O2-, OH.) and secondary (ROO.) free radicals, we evaluated its antioxidant effect on retinas of albino rats submitted to different types of aggressors. On isolated rat retina, EGb 761 given orally significantly protected against lipoperoxidation induced by a mixture of ferrous sulfate and sodium ascorbate added to the perfusion solution. With EGb 761, the decrease of the b-wave ERG amplitude was less pronounced and the retina survival was increased. EGb 761 was also effective against ischaemia-reperfusion disorders due to occlusion of the central retinal artery or by intraocular hypertony. Like other antioxidants such as superoxide dismutase tested on these models, EGb 761 significantly attenuated, according to a dose-response effect, the free-radical injury. EGb 761 reduces the decrease of the b-wave amplitude, the oedema, necrosis and ion homeostasis disturbances. Xenobiotics are also responsible for the retinotoxicity partly due to free radicals and PAF release. We noted an EGb 761 dose-dependent protective effect against acute and chronic chloroquine toxicity to the retina. The deleterious effect of chloroquine was characterized by a delayed b-wave and an asymmetry of the signal with slow declining b-wave. After EGb 761 treatment, the ERG aspect was partially normal. In conclusion, EGb 761, by its general free-radical scavenger properties, is an antioxidant that inhibits or reduces the functional and morphological retina impairments observed after lipoperoxide release.

A 5-kb DNA fragment conferring a phage abortive infection phenotype (Abi+) has been cloned from Lactococcus lactis subsp. lactis IL416. The Abi+ determinant was subcloned on a 2-kb fragment which carried an Iso-ISS1 element and an open reading frame of 753 bp designated ORFX. Deletion within ORFX entailed the loss of the Abi+ phenotype, establishing that ORFX is the structural abi-416 gene. The expression of abi-416 was shown to be mediated by the Iso-ISS1 element, which contains a sequence fitting the consensus sequence for gram-positive promoters.

The circuit presented in this paper associates the classical direct injection and integration for each pixel with a random access scanning for the array. This focal plane implementation has two major advantages : i - the design of the pixel allows a larger integration capacitance in the 70 m pitch. ii - in the large arrays, the random access addressing mode allows the selection of sub-pictures for signal processing. The device is described. Performances of 32*32 pixels 70 m pitch circuits hybridized to CMT diodes arrays (cut-off wavelength : 5.5 and 10.1 m) are presented.

Infrared systems for the future include a variety of device configurations. The most studied system is the hybrid focal plane array consisting of a photovoltaic CdHgTe (PV CMT) matrix interconnected by metallic bumps to a CCD silicon chip.CCD devices are more versatile than other silicon circuits, they can be operated in Time, Delay, and Integration mode (TDI) for scanned imaging or in staring mode. But CCD requires high impedance PV detector for direct injection in CCD wells with high coupling efficiency. An other critical performance needed for detectors is low l/f noise for high detectivity at low frequencies. The present work describes recent results obtained on PV CMT detectors and their coupling to CCD circuits.