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Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS

We studied the temperature-dependent transport properties of ultrathin black phosphorus (BP). We present measurements of BP Schottky barrier (SB) metal-oxide-semiconductor field-effect-transistors (MOSFETs) with various channel lengths, constructed from a single BP sample with nanoscale uniformity in thickness and width. The electrical characterization reveals a reversal in the temperature dependence of drain current as a function of gate voltage. This reversal indicates a transition in the charge conduction limiting mechanisms as the device is swept from the off-state into the on-state. In the off-state, charge transport is limited by thermionic emission over the energy barriers at the source/drain SB contacts, and drain current increases with temperature. In the on-state, carriers can easily tunnel across the SB at the contacts, and charge transport is limited by scattering in the channel. As a result, drain current decreases with temperature in the on-state, as scattering increases with temperature. Using Landauer transport theory, we derive a closed-form expression for thermionic emission current in SB-MOSFETs with two-dimensional channels. We use this expression to extract the SB height at metal contact interface with BP and demonstrate the impact of scattering on the extraction. We then use a comprehensive BP SB-MOSFET model to analyze on-state current as a function of temperature and demonstrate the effects of charged impurity and phonon scattering on the transport properties of BP through extractions of mobility at fixed carrier density.

Chemical vapor deposition (CVD)-grown monolayer (ML) molybdenum disulfide (MoS2) is a promising material for next-generation integrated electronic systems due to its capability of high-throughput synthesis and compatibility with wafer-scale fabrication. Several studies have described the importance of Schottky barriers in analyzing the transport properties and electrical characteristics of MoS2 field-effect-transistors (FETs) with metal contacts. However, the analysis is typically limited to single devices constructed from exfoliated flakes and should be verified for large-area fabrication methods. In this paper, CVD-grown ML MoS2 was utilized to fabricate large-area (1 cm × 1 cm) FET arrays. Two different types of metal contacts (i.e. Cr/Au and Ti/Au) were used to analyze the temperature-dependent electrical characteristics of ML MoS2 FETs and their corresponding Schottky barrier characteristics. Statistical analysis provides new insight about the properties of metal contacts on CVD-grown MoS2 compared to exfoliated samples. Reduced Schottky barrier heights (SBH) are obtained compared to exfoliated flakes, attributed to a defect-induced enhancement in metallization of CVD-grown samples. Moreover, the dependence of SBH on metal work function indicates a reduction in Fermi level pinning compared to exfoliated flakes, moving towards the Schottky–Mott limit. Optical characterization reveals higher defect concentrations in CVD-grown samples supporting a defect-induced metallization enhancement effect consistent with the electrical SBH experiments.

We present analytical models for calculating surface potential for both undoped (intrinsic) and doped (extrinsic) long channel symmetric double-gate MOSFETs. Starting with Poisson’s equation, we derive the implicit surface potential equation(s) for the symmetric double-gate MOSFET in the accumulation and depletion/inversion regions of operation. This results in a continuous surface potential curve throughout all operating regions of the device. By introducing a defect potential to surface potential equations for the symmetric double-gate MOSFET, the models add the effects of oxide-trapped charge and interface traps (both uniform and non-uniform distributions) that can build up in the gate dielectric of the device. A drain current model is presented for both the undoped and doped cases of the SDG MOSFET. The accuracy of the surface potential analytical models and drain current models are validated by comparing to numerical results from two dimensional TCAD simulations.

The characterization of impact-ionization (II) and stress-induced damage in 28-nm bulk n-channel MOSFETs is used to identify the mechanisms for carrier-induced interface trap generation (ITG) from 300 K to 77 K. The energy-driven paradigm of hot carrier effects is used to study carrier-induced ITG and its temperature dependence, and to analyze the influence of electron-electron scattering (EES) on carrier-induced degradation of ultra-short channel devices. The analysis clearly illustrates the significant role of EES in the hot (i.e., high-energy) carriers single particle mechanism of ITG, as well as its contribution to the cold (i.e., low-energy) carriers multiple particle mechanism of ITG. This is evidenced through extractions of ITG lifetime as a function of temperature and stress current from measurements of 28 nm n-channel devices. We apply a simple model to discuss the impact of EES on the experimentally observed trends for II and ITG rates.

This paper presents aligned carbon nanotube (CNT) synaptic transistors for large-scale neuromorphic computing systems. The synaptic behavior of these devices is achieved via charge-trapping effects, commonly observed in carbon-based nanoelectronics. In this work, charge trapping in the high- k dielectric layer of top-gated CNT field-effect transistors (FETs) enables the gradual analog programmability of the CNT channel conductance with a large dynamic range ( i. e., large on/off ratio). Aligned CNT synaptic devices present significant improvements over conventional memristor technologies ( e. g., RRAM), which suffer from abrupt transitions in the conductance modulation and/or a small dynamic range. Here, we demonstrate exceptional uniformity of aligned CNT FET synaptic behavior, as well as significant robustness and nonvolatility via pulsed experiments, establishing their suitability for neural network implementations. Additionally, this technology is based on a wafer-level technique for constructing highly aligned arrays of CNTs with high semiconducting purity and is fully CMOS compatible, ensuring the practicality of large-scale CNT+CMOS neuromorphic systems. We also demonstrate fine-tunability of the aligned CNT synaptic behavior and discuss its application to adaptive online learning schemes and to homeostatic regulation of artificial neuron firing rates. We simulate the implementation of unsupervised learning for pattern recognition using a spike-timing-dependent-plasticity scheme, indicate system-level performance (as indicated by the recognition accuracy), and demonstrate improvements in the learning rate resulting from tuning the synaptic characteristics of aligned CNT devices.

Black phosphorus (BP) has re-emerged as a promising layered material with significant potential for future nanoelectronic applications. Several recent studies have demonstrated an improvement in the transport properties of BP channels when insulated from SiO2 substrates using hexagonal boron nitride (hBN) (or when fully encapsulated). This improvement is typically characterized using extractions of mobility based on the empirical relationship between conductivity and carrier density. However, this does not provide insight into the transport mechanisms, nor it allows accounting for differences in intrinsic (e.g., bandgap and effective mass) and extrinsic (e.g., trap density/distribution and Schottky barrier heights) properties in the analysis. Here, we present a modeling approach for Schottky-barrier MOSFETs with low-dimensional channel materials based on the Landauer theory. To analyze transport improvement in hBN-insulated BP channels we fabricate and measure BP Schottky-barrier-MOSFETs with and without the hBN insulating layer. Our analysis demonstrates ~80% improvement in low-field effective channel mobility and an (energy averaged) scattering mean free path that is >5 times larger for BP devices with an underlying hBN layer compared to devices with BP directly on SiO2.

This letter demonstrates the impact of carrier confinement on the radiation response of Si-based SOI finFETS toward the scaling limit. A comparison between the semi-classical and quantum (i.e., self-consistent Schrodinger–Poisson) calculations establishes the significance of confinement effects in determining the experimentally observed radiation response as fin width is scaled to a few nanometers. This letter reveals that reduction in ionizing radiation sensitivity as a function of scaling is not only due to improved electrostatic control, but also due to reduced oxide fields resulting from size quantization and carrier confinement inside the channel of the device.

Soaked-hydrogen irradiations show the H 2 limits for the total-dose and dose-rate response of bipolar technologies. We use an analytical model to extrapolate experimental observations and generate an H 2 limits/dose-rate safe-operating-area for various total-dose conditions. Results indicate that 0.1% is the H 2 limit that can impact device degradation. We also show that the impact is larger for higher dose levels and that extra care needs to be taken when qualifying electronics for specific missions.

Janus crystals represent an exciting class of 2D materials with different atomic species on their upper and lower facets. Theories have predicted that this symmetry breaking induces an electric field and leads to a wealth of novel properties, such as large Rashba spin-orbit coupling and formation of strongly correlated electronic states. Monolayer MoSSe Janus crystals have been synthesized by two methods, via controlled sulfurization of monolayer MoSe2 and via plasma stripping followed thermal annealing of MoS2 . However, the high processing temperatures prevent growth of other Janus materials and their heterostructures. Here, a room-temperature technique for the synthesis of a variety of Janus monolayers with high structural and optical quality is reported. This process involves low-energy reactive radical precursors, which enables selective removal and replacement of the uppermost chalcogen layer, thus transforming classical transition metal dichalcogenides into a Janus structure. The resulting materials show clear mixed character for their excitonic transitions, and more importantly, the presented room-temperature method enables the demonstration of first vertical and lateral heterojunctions of 2D Janus TMDs. The results present significant and pioneering advances in the synthesis of new classes of 2D materials, and pave the way for the creation of heterostructures from 2D Janus layers.

The January 2020 special issue of the IEEE Transactions on Nuclear Science (TNS) contains selected articles from the 56th Annual IEEE International Nuclear and Space Radiation Effects Conference (NSREC) held on July 8–12, 2019, in San Antonio, TX, USA. The 2019 IEEE NSREC was sponsored by the IEEE Nuclear and Plasma Sciences Society; 69 of the 82 articles presented at the 2019 IEEE NSREC were submitted for consideration for this year’s special issue. This issue is neither a conference proceedings nor a conference record. The articles that appear in this special issue successfully completed the regular journal review process before the special issue deadline. Several more articles presented at the conference are likely to appear in subsequent issues of the transactions.

This paper investigates the influence of stress-induced oxide-trapped charge and interface traps on the electrostatics of metal–oxide–semiconductor (MOS) devices and its relation to short-channel effects (SCE). Interface trap and oxide-trapped charge densities are included in the derivation of scaling models that are based on solving Poisson’s equation in the depletion approximation (i.e., in weak inversion) using analytical approximations for the electrostatic potential. The impact of interface traps and oxide-trapped charge on the electrostatic potential profile, scaling, and short-channel effects are modeled analytically and verified with TCAD simulations. The theory and modeling approach is validated through comparisons with the experimental extraction of SCE in n-channel MOS field-effect transistors (MOSFETs) measured before and after hot-carrier stress.

Reliability simulations are critical for lifetime prediction and verification of long-term performance of integrated circuits designed in advanced CMOS technologies. The existing techniques for reliability simulation model aging effects using threshold voltage ( V th ) shifts that do not reflect the bias-dependence of stress-induced defects. In this work we present a defect-based modeling approach that captures the dynamic effects of both oxide-trapped charge and interface traps through calculations of surface potential. Such defects are attributed to aging effects and to ionizing–radiation damage in advanced CMOS technologies. The approach provides a connection between physics-based reliability models and integrated circuit simulation. The model is implemented as a Verilog-A sub-circuit module and is compatible with standard EDA tools and MOSFET compact models. The model formulation is verified using two-dimensional TCAD simulations. Demonstrations with digital integrated circuit simulations in SPICE and comparisons with calculations using V th -based models are also presented.

Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

In this work we are first to report an explicit solution to the SPE for a dynamically-depleted DD-SOI MOSFET that captures the effects of both oxide-trapped charge and interface traps on the device characteristics. Derivations for both the implicit (iterative) and explicit (non-iterative) solutions to the surface potential equation are presented for the DD-SOI MOSFET device. The explicit or closed form approximation was solved using non-iterative techniques that have been developed for the PSP MOSFET compact modeling framework (Wu, 2007; Chen and Gildenblat, 2001, 2005). The non-iterative model can be implemented as a Verilog-A sub-circuit module using a VCVS in series with the gate of the SOI MOSFET that is compatible with standard circuit level simulation tools. We demonstrate the accuracy of the implicit and explicit surface potential-based derivations using two dimensional TCAD simulations as a comparison. Finally, we present the symmetric linearization method for computing the drain current of the DD-SOI MOSFET.

The 2018 RADECS Workshop and 2nd International Conference on Radiation Effects of Electronic Devices (ICREED) were held on May 16–18, 2018, at the Fengda International Hotel, Beijing, China. The workshop and conference were hosted by the China Academy of Aerospace Electronics Technology, organized by the Beijing Microelectronics Technology Institute and the Harbin Institute of Technology, and attended by more than 260 researchers from 15 countries and more than 70 institutions. Six papers presented at ICREED are included in the June 2019 issue of the IEEE Transactions on Nuclear Science. These papers highlight active research on radiation effects on microelectronics in China. Additional papers based on work presented at ICREED appear in other issues of the transactions.

The January 2019 special issue of the IEEE Transactions on Nuclear Science (TNS) contains selected papers from the 55th annual IEEE International Nuclear and Space Radiation Effects Conference (NSREC) held on July 16–20, 2018, in Kona, Hawaii. The 2018 IEEE NSREC was sponsored by the IEEE Nuclear and Plasma Sciences Society. Eighty-three of the 102 papers presented at the 2018 IEEE NSREC were submitted for consideration for this year’s special issue. This issue is neither a conference proceeding nor a conference record. The papers that appear in this special issue successfully completed the regular journal review process before the special issue deadline. Several more papers presented at the Conference are likely to appear in subsequent issues of the Transactions.

We present data on radiation-induced effects in chalcogenide glasses that also trigger radiation induced structural reorganization contributing to silver (Ag) diffusion. To study these effects and silver diffusion, depending on the radiation dose, films were prepared and analyzed using Raman spectroscopy, X-ray diffraction and Energy Dispersion X-ray Spectroscopy. The results show a structural development occurring in films containing 45.4 at.% Ge with increasing radiation dose defined by increase in the edge-sharing/corner-sharing ratio, higher ethane-like unit values and rise of the amount of Ag diffused within the system. Utilizing these effects, a resistance based radiation sensing device has been created. The I–V curves characterizing the sensor operation demonstrate decreased device resistance as a result of the radiation.

We investigate total ionizing dose (TID) effects in graphene field effect transistors comprised of chemical vapor deposition grown graphene transferred onto trimethylsiloxy(TMS)-passivated SiO2 Si substrates. TID exposure with a positive gate bias increases the concentration of positive oxide trapped charges near the SiO2/TMS/graphene interface making Coulomb-potential scatterer limited mobility more apparent. In particular, we observe asymmetric degradation in electron and hole mobility, the former degrading more rapidly. Consistent with the electron-hole puddle description, we observe an increase in intrinsic electron carrier density that varies linearly with the oxide trapped charge density, while the hole carrier density remains largely unaltered. These effects give rise to an increasing minimum conductivity.

Total ionizing dose characteristics and dose rate dependence are evaluated under low temperature conditions for gated lateral PNP bipolar junction transistors. The results show that the dose rate sensitivity of the examined linear bipolar circuit technology is reduced when irradiations are performed at low temperature. The results are supported by numerical simulations that model low temperature behaviors through the suppression of hole and proton transport in the irradiated oxide. These findings agree well with previous studies of CMOS technologies, which reported on the time and bias dependence of defect buildup in MOS capacitors and transistors. This study of temperature effects on the total dose and dose rate response of PNP BJTs expands upon these works by examining the impact of low temperature on ELDRS in bipolar technologies.

Characterization and modeling of bias temperature instability (BTI) is conventionally based on time-dependent shifts in threshold voltage (Vth) resulting from stress and relaxation conditions. Contributions of oxide near-interfacial (i.e., border) and interface traps are not independently captured in these conventional methods. By considering the effects of charge trapping dynamics on MOSFET operation, we present new techniques for characterizing and modeling the contributions of oxide and interface traps. Characterization is based on the rapid response of interface traps to high-frequency measurements of inverse subthreshold slope (S), for which slower oxide traps do not contribute, as their occupancy does not change at high frequencies. The modeling approach uses calculations of surface potential (ψs) to describe the distinct contributions of oxide and interface traps on BTI. Combined with capture/emission time maps, this approach describes BTI-induced ΔS, and Δ Vth stress/recovery characteristics.

The effects of hydrogen on dose-rate sensitivity are simulated using a one-dimensional (1-D) model that incorporates the physical mechanisms contributing to dose-rate effects in the metal-oxide-semiconductor (MOS) system of gated lateral pnp (GLPNP) bipolar transistors. Calculations show that molecular hydrogen cracking at positively charged defects may be a key reaction relating hydrogen and dose rate response. Comparison to experimental data on bipolar devices is in good agreement with the dose rate calculations of interface trap buildup.

The incorporation of total ionizing dose (TID) effects into surface-potential-based compact models requires calculating the dependence of surface potential $({\psi}_{s})$ on radiation-induced defect densities. This dependence is obtained through the introduction of the oxide trapped charge $(N_{ot})$ and the interface trap $(N_{it})$ areal densities into the surface potential equation (SPE). In this work we present an approach for introducing a non-uniform energy distribution of interface traps into calculations of ${\psi}_{s}$ . The approach is verified experimentally through comparisons with capacitance vs. voltage ( $C$ - $V$ ) characteristics of metal-oxide-semiconductor (MOS) capacitors exposed to ionizing radiation.

Low dose rate experiments on field-oxide-field-effect-transistors (FOXFETs) fabricated in a 90 nm CMOS technology indicate that there is a dose rate enhancement factor (EF) associated with radiation-induced degradation. One dimensional (1-D) numerical calculations are used to investigate the key mechanisms responsible for the dose rate dependent buildup of radiation-induced defects in shallow trench isolation (STI) oxides. Calculations of damage EF indicate that oxide thickness, distribution of hole traps and hole capture cross-section affect dose rate sensitivity. The dose rate sensitivity of STI oxides is compared with the sensitivity of bipolar base oxides using model calculations.

We demonstrate an analytical modeling approach that captures the effects of total ionizing dose (TID) on the Id -Vgs characteristics of field-oxide-field-effect-transistors (FOXFETs) fabricated in a low-standby power commercial bulk CMOS technology. Radiation-enabled technology computer aided design (TCAD) simulations and experimental data allow validating the model against technological parameters such as doping concentration, field-oxide thickness, and geometry. When used in conjunction with the closed-form expressions for the surface potential, the analytical models for fixed oxide charge and interface trap density enables accurate modeling of radiation-induced degradation of the FOXFET Id -Vgs characteristics allowing the incorporation of TID into surface potential based compact models.

The radiation response of advanced non-planar multiple gate field effect transistors (MuGFETs) has been shown to have a strong dependence on fin width (W). The incorporation of total ionizing dose (TID) effects into a physics-based surface-potential compact model allows for the effects of radiation-induced degradation in MuGFET devices to be modeled in circuit simulators, e.g., SPICE. A set of extracted parameters are used in conjunction with closed-form expressions for the surface potential, thereby enabling accurate modeling of the radiation-response and its dependence on W . Total ionizing dose (TID) experiments and two-dimensional (2D) TCAD simulations are used to validate the compact modeling approach presented in this paper.

Accurate and efficient synaptic weight programming and vector-matrix multiplication are demonstrated using compound synapses constructed with ultralow power binary memristive devices having oxidized atomically thin two-dimensional hexagonal boron nitride (BNOx) filament formation layers. Experimental data of the resistive-switching current-voltage characteristics of BNOx memristors are used to formulate variation-aware models that enable statistically analyzing the trade-off between efficiency and accuracy as a function of the synaptic resolution (i.e., levels of synaptic weight programming). Results are compared with commonly reported oxide-based memristors indicating orders of magnitude (i.e., ∼105) improvements in power efficiency and ∼2-5× improvements in accuracy.

This paper describes a new approach for modeling bias-temperature instability (BTI) in nanoscale transistors. The model uses non-iterative surface potential solvers enhanced with dynamic defect potential equations to enable accurate, physics-based circuit level simulations that incorporate BTI effects. Defect maps constructed from experimental data reported on high-k-metal-gate bulk complementary metal-oxide-semiconductor devices are used to parameterize the defect potential equation. By implementing the enhanced surface potential model in Verilog-A, both DC and AC BTI aging effects in combinational circuits are simulated and the results compared conventional threshold voltage shift methods for BTI modeling.

In this work, we study the high critical breakdown field in β-Ga2O3 perpendicular to its (100) crystal plane using a β-Ga2O3/graphene vertical heterostructure. Measurements indicate a record breakdown field of 5.2 MV/cm perpendicular to the (100) plane that is significantly larger than the previously reported values on lateral β-Ga2O3 field-effect-transistors (FETs). This result is compared with the critical field typically measured within the (100) crystal plane, and the observed anisotropy is explained through a combined theoretical and experimental analysis.

The January 2018 special issue of the IEEE Transactions on Nuclear Science (TNS) contains selected papers from the 54th annual IEEE International Nuclear and Space Radiation Effects Conference (NSREC) held on July 17–21, 2017 in New Orleans, LA, USA. The 2017 IEEE NSREC was sponsored by the IEEE Nuclear and Plasma Sciences Society. Eighty four of the ninety three papers presented in New Orleans were submitted for consideration for this year’s special issue. The papers that appear in this special issue successfully completed the review process before the deadline. Several more papers presented in New Orleans are likely to appear in subsequent issues of the Transactions.

A comprehensive model is presented which enables the effects of ionizing radiation on bulk CMOS devices and integrated circuits to be simulated with closed form functions. The model adapts general equations for defect formation in uniform SiO2 films to facilitate analytical calculations of trapped charge and interface trap buildup in structurally irregular and radiation sensitive shallow trench isolation (STI) oxides. A new approach whereby non-uniform defect distributions along the STI sidewall are calculated, integrated into implicit surface potential equations, and ultimately used to model radiation-induced ldquoedgerdquo leakage currents in n-channel MOSFETs is described. The results of the modeling approach are compared to experimental data obtained on 130 nm and 90 nm devices. The features having the greatest impact on the increased radiation tolerance of advanced deep-submicron bulk CMOS technologies are also discussed. These features include increased doping levels along the STI sidewall.

A continuous analytical model for radiation-induced degradation in fully-depleted (FD) silicon on insulator (SOI) n-channel MOSFETs is presented. The combined effects of defect buildup in the buried oxide and band-to-band tunneling (BBT) have been shown to be the primary mechanisms that determine the radiation effects on the electrical characteristics. Closed-form expressions for the front and back-gate surface potential incorporate these effects, thereby enabling accurate modeling of the degraded current voltage characteristics that result from ionizing radiation exposure.

The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices.

A modeling approach using two-dimensional device simulations is presented, which enables the extraction of parameters for the radiation-induced parasitic MOSFET created at the edge of the shallow trench isolation (STI) oxide. With the model, one can estimate drain-to-source off-state leakage current (I/sub OFF/) resulting from build-up of oxide trapped charge (N/sub OT/). The impact of nonuniform N/sub OT/ build-up in the STI resulting from total ionizing dose (TID) exposure and external bias conditions is analyzed through volumetric simulations and compared to experimental data. Saturation for the off-state leakage current as a function of trapped charge is also investigated.

A defect-based compact modeling approach for circuit reliability simulation based on surface potential calculations is presented. The modeling approach captures the bias-dependence of stress-induced defects such as (bulk) oxide-trapped charge and interface traps that cannot be described by typical fixed voltage shift models (i.e., threshold voltage, Vth-based models). The defect dynamic charge contribution is modeled under non-equilibrium conditions and for all regions of operation (i.e. from weak to strong inversion) and not just at the threshold (as in Vth-based models). The modeled is verified with 2-D TCAD simulations that incorporate oxide trapped charge and interface trap densities. Spice-level simulations of ring oscillators and SRAM cells reveal inaccuracies in describing aging effects when utilizing typical fixed voltage shift models as compared to the presented defect-based compact modeling approach.

The incorporation of total ionizing dose (TID) effects into surface-potential-based compact models requires calculating the dependence of surface potential ( ψ s ) on radiation-induced defect densities. This dependence is obtained through the introduction of the oxide trapped charge (N ot ) and the interface trap (N it ) areal densities into the surface potential equation (SPE). In this work we present an approach for introducing a non-uniform energy distribution of interface traps into calculations of ψ s . The approach is verified experimentally through comparisons with capacitance vs. voltage (C-V) characteristics of metal-oxide-semiconductor (MOS) capacitors exposed to ionizing radiation.

Solid electrolytes based on chalcogenide glasses have been one of the most promising candidates for the next generation non-volatile memories. Here we propose a new application of chalcogenide solid electrolytes for low cost, high performance microelectronic radiation sensor that reacts to γ-radiation to produce an easily measurable change in electrical resistance. The active layer material is Ag-doped GeS thin film glasses and several compositions of GeS base glasses were tested for best resistive sensing capability. Energy-dispersive X-ray spectroscopy (EDS) was used for elemental analysis and Raman scattering spectroscopy was measured to determine the structural details and radiation induced structural changes. We also present initial electrical measurement results with test devices.

Dual charge pump data show a reduction of circuit output voltage with dose. Through testing of individual process monitors, the response is identified as parasitic interdevice leakage caused by trapped oxide charge buildup in the isolation oxide. A library of compact models is generated for the field oxide parasitic based on test structure data along with 2-D structure simulation results. The charge pump schematic is then back annotated with transistors representative of the parasitic at different dose levels. Inclusion of the parasitic devices in schematic allows for simulation of the entire circuit at a specific dose. The reduction of circuit output with dose is then re-created in simulation.