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Semiconductors have long been perceived as a prerequisite for solid-state transistors. Although switching principles for nanometer-scale devices have emerged based on the deployment of two-dimensional (2D) van der Waals heterostructures, tunneling and ballistic currents through short channels are difficult to control, and semiconducting channel materials remain indispensable for practical switching. In this study, we report a semiconductor-less solid-state electronic device that exhibits an industry-applicable switching of the ballistic current. This device modulates the field emission barrier height across the graphene-hexagonal boron nitride interface with ION/IOFF of 106 obtained from the transfer curves and adjustable intrinsic gain up to 4, and exhibits unprecedented current stability in temperature range of 15–400 K. The vertical device operation can be optimized with the capacitive coupling in the device geometry. The semiconductor-less switching resolves the long-standing issue of temperature-dependent device performance, thereby extending the potential of 2D van der Waals devices to applications in extreme environments. In field-effect transistors, a semiconducting channel is indispensable for device switching. Here, the authors demonstrate semiconductor-less switching via modulation of the field emission barrier height across a graphene-hBN interface with ON/OFF ratio of 106.

Temperature-independent magnetoresistance (TIMR) has been studied for applications in magnetic field sensors operating in wide temperature ranges. Graphene is considered as one of the best candidates for achieving nonsaturating and large TIMR through engineering disorders. Nevertheless, large TIMR has not been achieved in disordered graphene with intrinsic defects, such as chemical doping and atomic dislocations. In this work, by introducing extrinsic defects, we realize nonsaturating and large TIMR in monolayer graphene transferred on a BiFeO3 nanoisland array (G/BFO-NIA). Furthermore, the G/BFO-NIA device exhibits a significantly larger MR (∼250% under 9 T) than other materials without gating operation, demonstrating its application feasibility. It is shown that the large MR is a result of the coexistence of electrons and holes with almost the same density, and the observed TIMR originates from the temperature dependence of carrier transport in graphene and of the dielectric property of BFO-NIA.

A high-speed residue-free transfer method using PDMS (polydimethylsiloxane) stamp and water infiltration between graphene and a hydrophilic surface is reported. Monolayer graphene was transferred from an enhanced fluorinated Al2O3 surface using PDMS. Water infiltration dramatically reduced the time required to separate the graphene from the Al2O3 substrate to a few minutes. The graphene was then successfully transferred to a target substrate (SiO2) using the PDMS stamp. Atomic force microscopy and lateral force microscopy was used to confirm the absence of residue on the transferred graphene surface.

Multilayer graphene is considered a promising material for various optoelectronic devices. To exploit its intriguing electronic properties, an electric field must be achieved inside this material. ...

We have investigated the effect of an Al

Surface modification layer of a silicon substrate has been used to enhance the performance of graphene field-effect transistors (FETs). In this report, ultrathin and chemically robust polymer brush was used as a surface modification to enhance the gas sensing properties of graphene FETs. The insertion of the polymer brush decreased substrate-induced doping of graphene. This leads to a huge increase in field-effect mobility as well as a minimum shift of the Dirac point voltage. The use of the polymer brush enables fast detection of target gas molecules because graphene sensing modality can be maximized at the undoped state of graphene. The increase of source-drain current, as well as the abrupt decrease of electron mobility upon NO2 exposure, was utilized for the instantaneous detection, and a limit of detection of 4.8 ppb was achieved with graphene FETs on PS brush. We also showed excellent cross-sensitivity of graphene gas sensors to NH3, CO2, and relative humidity condition; the source-drain current decreases upon NH3 exposure, while response to CO2 or relative humidity condition is extremely low. Our results prove that reducing the substrate-induced doping of graphene with a polymer brush is a direct method for boosting the gas sensing properties of graphene FETs.

Semiconductors have long been perceived as a prerequisite for solid-state transistors. Although switching principles for nanometer-scale devices have emerged based on the deployment of two-dimensional (2D) van der Waals heterostructures, tunneling and ballistic currents through short channels are difficult to control, and semiconducting channel materials remain indispensable for practical switching. In this study, we report a semiconductor-less solid-state electronic device that exhibits an industry-applicable switching of the ballistic current. This device modulates the field emission barrier height across the graphene-hexagonal boron nitride interface with ION/IOFF of 106 obtained from the transfer curves and adjustable intrinsic gain up to 4, and exhibits unprecedented current stability in temperature range of 15–400 K. The vertical device operation can be optimized with the capacitive coupling in the device geometry. The semiconductor-less switching resolves the long-standing issue of temperature-dependent device performance, thereby extending the potential of 2D van der Waals devices to applications in extreme environments., In field-effect transistors, a semiconducting channel is indispensable for device switching. Here, the authors demonstrate semiconductor-less switching via modulation of the field emission barrier height across a graphene-hBN interface with ON/OFF ratio of 106.

We have investigated the effect of an Al2O3passivation layer on the performance of few-layer WS2FETs. While the performance of WS2FETs is often limited by a substantial decrease in carrier mobility owing to charged impurities and a Schottky barrier between the WS2and metal electrodes, the introduction of an Al2O3overlayer by atomic layer deposition (ALD) suppressed the influence of charged impurities by high-κdielectric screening effect and reduced the effective Schottky barrier height. We argue that n-doping of WS2, induced by positive fixed charges formed at Al2O3/WS2interface during the ALD process, is responsible for the reduction of the effective Schottky barrier height in the devices. In addition, the Al2O3passivation layer protected the device from oxidation, and maintained stable electrical performance of the WS2FETs over 57 d. Thus, the ALD of Al2O3overlayer provides a facile method to enhance the performance of WS2FETs and to ensure ambient stability.

We have investigated the performances of barristors with a graphene-tungsten disulfide (WS 2 ) junction by varying the thickness of WS 2 and gate oxide. On-current density ( J ON ) and on- and off-current ratio ( J ON / J OFF ) increases, and sub-threshold swing ( V SS ) decreases with the WS 2 thickness. Also, barristors with thicker WS 2 required less workfunction shift, to switch the barristors. Therefore, unlike the traditional devices, V SS of barristor with gate dielectric 300 nm was smaller than that of 90 nm, when the former is fabricated with thicker WS 2 than the latter. Since materials properties of 2-dimensional semiconductors generally vary with their thickness, the thickness of 2D semiconductors could become a key parameter to engineer the performance of barristors with graphene and the 2D semiconductors.

We have investigated the current distribution between individual layers of multilayer MoS2 in a field-effect transistor structure with source and drain electrodes on the top layer. By employing a laser thinning technique, we partially etched down the multilayer in the middle of the device and monitored the electrical current after each etching step. The current was decreased by several orders of magnitude when the upper layers were partially etched away. Our observation suggests that the electrical current of multilayer MoS2 flows mainly through the upper layers close to the source/drain contacts due to relatively large interlayer resistance of MoS2.

We have investigated the effect of laser irradiation on monolayer MoS2 and observed the swellingup of the monolayer from the SiO2 substrate upon laser illumination. The mismatch in the thermal expansion between the substrate and MoS2 can result in the structural deformation. Employing this method, one can induce structural deformation in a desired pattern, and one can demonstrate the patterning of periodic ripples in monolayer MoS2 by using laser irradiation. The controlled fabrication of the ripple structure may be instrumental in understanding the effect of ripples on the interesting physical properties of monolayer MoS2.

The evolution of surface cleanliness and the electronic properties-Dirac voltage(V Dirac), hysteresis and mobility (μ) of a graphene field-effect transistor (GFET)-were monitored by measuring lateral force microscopy and drain current (I D) as a function of gate voltage (V G), after mechanically cleaning the surface, scan-by-scan, with contact-mode atomic force microscopy. Both the surface cleanliness and the electronic properties evolved, showing a sudden improvement and then saturation for a mobility of around 2200 cm2 V-1 s-1. We found that the mobility suppression of the as-fabricated GFET deviated from a randomly distributed impurities model, which predicted a greater mobility than obtained from the measured V Dirac. Therefore, the substrate impurities are excluded from the origins of the extraordinary suppression of the mobility, and the possible origin will be discussed.

Despite a rich choice of two-dimensional materials, which exists these days, heterostructures, both vertical (van der Waals) and in-plane, offer an unprecedented control over the properties and functionalities of the resulted structures. Thus, planar heterostructures allow p-n junctions between different two-dimensional semiconductors and graphene nanoribbons with well-defined edges; and vertical heterostructures resulted in the observation of superconductivity in purely carbon-based systems and realisation of vertical tunnelling transistors. Here we demonstrate simultaneous use of in-plane and van der Waals heterostructures to build vertical single electron tunnelling transistors. We grow graphene quantum dots inside the matrix of hexagonal boron nitride, which allows a dramatic reduction of the number of localised states along the perimeter of the quantum dots. The use of hexagonal boron nitride tunnel barriers as contacts to the graphene quantum dots make our transistors reproducible and not dependent on the localised states, opening even larger flexibility when designing future devices.

A model to explain the origin of channel width dependent field effect mobility is proposed. According to our model accounting the effect of non-uniform carrier transport in a graphene channel, the field effect mobility of wide channel graphene FET has been severely underestimated as much as two times, even without accounting the fringing field effect. Based on our model, we propose a more accurate protocol to extract the field effect mobility of graphene FET involving the use of narrow channel width devices. Display Omitted A percolative conduction model is proposed to elucidate the non-uniform transport in a graphene channel.The non-uniform transport causes an underestimation on the mobility at wide channel graphene device.A new mobility extraction method has been proposed to calibrate the error.

Recently, various electronic components including transistor, barristor, memory, and transparent electrode were implemented using graphene. While integrated circuits were demonstrated by combining graphene transistors and passive components, system on chip (SoC) platform, state-of-the-art semiconductor technology, by combining transistors and memories on the same chip, has not yet been demonstrated. The main obstacle of the realization of SoC is the complexity of fabrication processes originated from the process differences between the transistors and the memories. In this study, using simple and clean atomic force microscope lithography, we fabricated both the switching devices and the memories by forming very thin graphene oxide (GO) barriers in mono-layer graphene at the controlled oxidation voltages. Formed with 7 V and 9 V, the lateral graphene/GO/graphene junction devices exhibit switching of Fowler-Nordheim tunneling current and resistive memory behavior, respectively. The combination of high on/off current ratio (∼1000) of the switching device and nonvolatility of the memory device fabricated by the same process demonstrates the possibility of graphene SoC platform.

The optical constants, bandgaps, and band alignments of mono-, bi-, and trilayer WS2 were experimentally measured, and an extraordinarily high dependency on the number of layers was revealed. The refractive indices and extinction coefficients were extracted from the optical-contrast oscillation for various thicknesses of SiO2 on a Si substrate. The bandgaps of the few-layer WS2 were both optically and electrically measured, indicating high exciton-binding energies. The Schottky-barrier heights (SBHs) with Au/Cr contact were also extracted, depending on the number of layers (1-28). From an engineering viewpoint, the bandgap can be modulated from 3.49 to 2.71 eV with additional layers. The SBH can also be reduced from 0.37 eV for a monolayer to 0.17 eV for 28 layers. The technique of engineering materials' properties by modulating the number of layers opens pathways uniquely adaptable to transition-metal dichalcogenides.

Ethylenediamine-modified -cyclodextrin (Et-beta-CD) was immobilized on aggregated silver nanoparticle (NP)-embedded silica NPs (SiO2@Ag@Et--CD NPs) for the effective detection of flavonoids. Silica NPs were used as the template for embedding silver NPs to create hot spots and enhance surface-enhanced Raman scattering (SERS) signals. Et-beta-CD was immobilized on Ag NPs to capture flavonoids via host-guest inclusion complex formation, as indicated by enhanced ultraviolet absorption spectra. The resulting SiO2@Ag@Et-beta-CD NPs were used as the SERS substrate for detecting flavonoids, such as hesperetin, naringenin, quercetin, and luteolin. In particular, luteolin was detected more strongly in the linear range 10(-7) to 10(-3) M than various organic molecules, namely ethylene glycol, beta-estradiol, isopropyl alcohol, naphthalene, and toluene. In addition, the SERS signal for luteolin captured by the SiO2@Ag@Et-beta-CD NPs remained even after repeated washing. These results indicated that the SiO2@Ag@Et-beta-CD NPs can be used as a rapid, sensitive, and selective sensor for flavonoids.

Power amplifier circuits are implemented with graphene field-effect transistors (FETs), capacitors and inductors, and their gain is improved step-by-step by adjusting the passive components. The transistors are fabricated on a 150-mm wafer using conventional complementary-metal-oxide semiconductor processing along with graphene transferring processes. The completed circuit is implemented on a printed circuit board, which allows for adjustment of the external capacitance and inductance to study the performance of graphene RF FETs. A maximum signal gain of 1.3 dB is achieved at 380 MHz. The device parameters of the transistors are then extracted and the gain is analyzed, and the results show that lowering the source–drain conductance and gate resistance is the key in realizing high performance circuits.

Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance (C Q) which limits the effective gate dielectric reduction. In this work, we analyzed the effect of C Q on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator-metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. C Q contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from C Q, grapheme’s high mobility and low-voltage operation allows for graphene channels suitable for next generation transistors.

We report on the fabrication of completely uniform monolayer graphene on a metal thin film over a 150 mm Si substrate at a low temperature of 600 °C by inductively coupled plasma-enhanced chemical vapor deposition (ICPCVD). Through novel use of bimetallic catalyst such as CuNi and AuNi alloys we were able to control catalytic reaction at the metal surface and grow complete monolayer graphene with a Ni content less than 20 at.%. We also found that the 2D/G intensity ratio in the Raman spectra was almost invariant with growth time and the C 1s peak in the XPS spectra was observed only at the metal surface. This implies that monolayer graphene was possibly grown on these Ni-doped copper and gold catalysts by a self-limiting surface reaction under our CVD condition. From DFT calculations, it was shown that the catalytic activity of normally inactive Cu and Au could be enhanced through the addition of Ni atoms at surface sites, providing graphene growth at lower temperatures than pure Cu or Au. The carrier mobility of graphene films grown on these CuNi and AuNi alloy catalyst was measured to be over 9000 cm2 V−1 s−1 at room temperature, which is comparable to that of CVD graphene film grown on Cu foil. Therefore, we suggest an efficient way in growing a complete monolayer graphene on thin films at low temperatures, which could be a key issue in the application of graphene devices.

The rectifying Schottky characteristics of the metal-semiconductor junction with high contact resistance have been a serious issue in modern electronic devices. Herein, we demonstrated the conversion of the Schottky nature of the Ni-Si junction, one of the most commonly used metal-semiconductor junctions, into an Ohmic contact with low contact resistance by inserting a single layer of graphene. The contact resistance achieved from the junction incorporating graphene was about 10(-8) ~ 10(-9) Ω cm(2) at a Si doping concentration of 10(17) cm(-3).

Transparent graphene electrodes in III–V multijunction concentrator solar cells improved the cell efficiency by reducing the resistive power loss at high irradiance levels. The conversion efficiency of the solar cell increased by 13.8 % as a result of the decreased series resistance. Moreover, the irradiance level at which the maximum efficiency was reached increased upon using the graphene electrodes. This allows the solar cells to operate at higher concentration ratios, which can lead to a better performance and lower cost of the photovoltaic devices.

In this work, compact current modeling of field-effect transistors (FETs) with transferred graphene channel grown by using chemical vapor deposition is presented. A highly-doped silicon substrate is used as a back gate, channels are defined by using electron-beam lithography, and the channel length of the transistor is scaled down to 20 nm. The DC characteristics of the scaled graphene transistors are observed by considering the source/drain series resistances. In compact modeling of graphene FETs, an electron-hole puddle existing near the charge-neutral region (Dirac point) is considered at a low carrier density while the velocity saturation effect due to surface polar phonon scattering is included at a high carrier density.

Graphene based low noise amplifier has been studied actively because the noise characteristics of graphene devices are known to be superior to those of silicon devices. However, 1/f noise characteristics of graphene grown by chemical vapor deposition (CVD) may increase by an order of magnitude when measured before the charge exchange reaction at the interface of the graphene and substrate is saturated. Based on the close correlation between the level of low frequency noise signal and fast charge exchange reaction (in milliseconds), the conductivity fluctuation of graphene caused by the interfacial charge exchange reaction may be the source of the increased low frequency noise. This result suggests that the current assessment of noise characteristics is too optimistic for graphene and that the defect density of CVD graphene needs to be further reduced to minimize the charge exchange reaction.

We report nanoscale domain boundaries on single layer graphene probed with conductive probe atomic force microscopy in ultrahigh vacuum. Graphene was prepared using the inductively coupled plasma chemical vapor deposition technique on a copper substrate. Current mapping revealed domains 50–100 nm in size on the single layer graphene. Stick slip images revealed a hexagonal structure of the graphene layer in the middle of the domain. The conductance on the domain boundary is lower than that inside the domain structure, which is associated with disorder on the boundary, while friction and adhesion measurements on the domain boundaries did not show any contrast. We found that the conductance contrast is prominent at high loads, suggesting the domain boundary plays a significant role in the charge transport properties of graphene under mechanical deformation. Copyright © 2012 John Wiley & Sons, Ltd.

We have synthesized a very thin graphite film on polycrystalline Ni foil using radio frequency plasma-enhanced chemical vapor deposition (RF-PECVD) at relatively low temperature. Structural analysis through electron diffraction and Raman spectroscopy demonstrated that the PECVD grown graphite film consists of large grains sized over tens of microns and is highly ordered structure exhibiting Bernal stacking despite of low synthetic temperature of 850oC. Accordingly, the high carrier mobility of 4,500 cm2/Vsec was obtained at room temperature from a monolayer of PECVD grown graphene, which is higher than any reported value of CVD-grown graphene.

Graphene has been considered as a candidate for interconnect metal due to its high carrier mobility and current drivability. In this letter, the breakdown mechanism of single-layer chemical-vapor-deposited (CVD) graphene and triple-layer CVD graphene has been investigated at three different conditions (air exposed, vacuum, and dielectric capped) to identify a failure mechanism. In vacuum, both single- and triple-layer graphenes demonstrated a breakdown current density as high as ~108 A/cm2, which is similar to that of exfoliated graphene. On the other hand, the breakdown current of graphene exposed to air was degraded by one order of magnitude from that of graphene tested in vacuum. Thus, oxidation initiated at the defect sites of CVD graphene was suggested as a major failure mechanism in air, while Joule heating was more dominant with dielectric capping and in vacuum.

We have investigated random telegraph noise (RTN) observed in individual metallic carbon nanotubes (CNTs). Mean lifetimes in high- and low-current states, shigh and slow, have been studied as a function of bias-voltage and gate-voltage as well as temperature. By analyzing the statistics and features of the RTN, we suggest that this noise is due to the random transition of defects between two metastable states, activated by inelastic scattering with conduction electrons. Our results indicate an important role of defect motions in the 1=f noise in CNTs., 4 pages

Electrical characterization of an operating pn-junction diode is performed with scanning capacitance microscopy (SCM) and Kelvin probe force microscopy (KPFM) with submicron scale resolution. We image the spatial distribution of the carrier density inside a diode with SCM and the potential distribution on the surface of the operating diode with KPFM. The surface potential distribution measured at reverse bias is different from that in bulk. The potential drop is extended deep into a lightly p-doped region at reverse bias. The positive fixed oxide charge of 1–2×1011/cm2 would explain the modified potential drop: A known detrimental effect in such a device. The potential distribution at forward bias is nearly bulklike. The potential drops only near the metal–semiconductor junction.

Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.

We report a new strategy to selectively localize and control microtubule translocation via electrical control of microtubules using a microfabricated channel on a functionalized-graphene electrode with high transparency and conductivity. A patterned SU-8 film acts as an insulation layer which shields the electrical field generated by the graphene underneath while the localized electric field on the exposed graphene surface guides the negatively charged microtubules. This is the first report showing that functionalized graphene can support and control microtubule motility.

Many device scientists believe that current Ultra Large Scale Integration (ULSI) technology will face technical and economic difficulties in further miniaturization. It has been proposed that 1-dimensional (1-D) transistors with connecting wires and three-dimensionally stacked structures may replace current field effect transistors with planar integration structures. We propose a new scheme to fabricate and integrate 1-D active devices. As a first step, we show the way to form 1-D wires with spatially variable electronic structures and the way to characterize them.

One of the key components of modern device structures is the metal-semiconductor (MS) contact with low symmetric contact resistance. We report on a MS contact structure utilizing graphene insertion. In this strategy, graphene reduces or even eliminates in ideal conditions, the Fermi-level pinning at a MS junction. Since the metal, Ni, deposited on graphene reduced the work function of graphene, the doped graphene was able to lower the Schottky barrier at the MS junction. The Schottky barrier height of metal-graphene-Si (MGS) junction was obtained from temperature dependent I-V characteristics. We confirmed that the graphene doped with Ni reduced the Schottky barrier height from 0.67 eV to 0.20 eV in wafer scale test. We also demonstrated the formation of an ideal MGS Ohmic contact via conductive atomic force microscopy. The contact resistance of the ideal MGS was less than 1.0×10-6 Ω cm2 with low doped Si (1015 cm3). The resistance is comparable to that of a current device contact with highly doped Si. Since it only requires the insertion of a single layer of graphene, this method can be directly applied to the current Si technology to reduce the contact resistance at MS junctions.

Lifetime of multi-layer graphene interconnects under constant current stress is studied for the first time. Under a stress current density of 20MA/cm2 at 250°C exposed to air, Mean-Time-To-Fail (MTTF) of uncapped CVD graphene wire is about 6 hours. It is shown that lifetime is mainly limited by defect formation due to graphene oxidation.

Updating the Triode with Graphene In early electronics, the triode—a vacuum device that combined a diode and an electrical grid—was used to control and amplify signals, but was replaced in most applications by solid-state silicon electronics. One characteristic of silicon-metal interfaces is that the Schottky barrier created—which acts as a diode—does not change with the work function of the metal—the Fermi level is pinned by the presence of surface states. Yang et al. (p. 1140 , published online 17 May) now show that for a graphene-silicon interface, Fermi-level pinning can be overcome and a triode-type device with a variable barrier, a “barristor,” can be made and used to create devices such as inverters.

As silicon-based electronics approach the limit of improvements to performance and capacity through dimensional scaling, attention in the semiconductor field has turned to graphene, a single layer of carbon atoms arranged in a honeycomb lattice. Its high mobility of charge carriers (electrons and holes) could lead to its use in the next generation of high-performance devices. Graphene is unlikely to replace silicon completely, however, because of the poor on/off current ratio resulting from its zero bandgap. But it could be used to improve silicon-based devices, in particular in high-speed electronics and optical modulators.

Recent success of inexpensive and high-throughput chemical vapor deposition (CVD) growth [1] of graphene on Ni or Cu substrates has shown promises for potential industrial applications such as transparent electrodes [2] and field effect transistors (FET). [3] However, high-coverage uniform growth of monolayer graphene on a wafer scale is still a major obstruction, which impedes high yield integration of high performance field effect devices. Here, we report the first demonstration of high quality top-gated graphene field effect devices on 150 mm substrates exploiting unprecedented homogeneous CVD growth of monolayer graphene.

Using first-principles calculations of graphene having high-symmetry distortion or defects, we investigate band gap opening by chiral symmetry breaking, or intervalley mixing, in graphene and show an intuitive picture of understanding the gap opening in terms of local bonding and antibonding hybridizations. We identify that the gap opening by chiral symmetry breaking in honeycomb lattices is an ideal two-dimensional (2D) extension of the Peierls metal-insulator transition in 1D linear lattices. We show that the spontaneous Kekule distortion, a 2D version of the Peierls distortion, takes place in biaxially strained graphene, leading to structural failure. We also show that the gap opening in graphene antidots and armchair nanoribbons, which has been usually attributed to quantum confinement effects, can be understood with the chiral symmetry breaking.

Graphene and its derivatives (graphite, CNT) have very high conductivity and critical current density higher than 108 A/cm2, which can be utilized in interconnect applications. Theoretically, a doped graphene is predicted to have better performance than Cu as an interconnect conductor. However, the feasibility of graphene interconnect has not been experimentally examined systematically. In this paper, the critical current density of single layer and multilayer graphene are studied to provide insights about the feasibility of graphene interconnect technology.

Scanning tunneling microscopy (STM) and density functional theory (DFT) calculations were used to investigate the surface morphology and electronic structure of graphene synthesized on Cu by low temperature chemical vapor deposition (CVD). Periodic line patterns originating from the arrangements of carbon atoms on the Cu surface passivate the interaction between metal substrate and graphene, resulting in flawless inherent graphene band structure in pristine graphene/Cu. The effective elimination of metal surface states by the passivation is expected to contribute to the growth of monolayer graphene on Cu, which yields highly enhanced uniformity on the wafer scale, making progress toward the commercial application of graphene.

We measured Radio-Frequency (RF) performance of devices with graphene grown using low temperature Inductively-Coupled Plasma Chemical Vapor Deposition (ICP-CVD) method on 6-inch wafer for the first time. To remove the coupling of electrode in-plane, we introduced locally-embedded-back-gate using TiN metal. The symmetric structure of 2-gate fingers was adopted to reduce misalign issue during fabrication of the structure with underlap between Gate and Source/Drain, which was also adopted for the reduction of parasitic capacitance due to gate oxide with high dielectric constant. Cutoff frequency (ƒ T ) increase is moderately obtained with the decrease of gate length. Despite the low g m due to underlap region, we obtained ƒ T =80 GHz.