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Graphene and thin-film semiconductor heterojunction transistors integrated on wafer scale for low-power electronics
- Source :
- Nano letters. 13(12)
- Publication Year :
- 2013
-
Abstract
- Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.
- Subjects :
- Wafer-scale integration
Materials science
Transistors, Electronic
Graphene
business.industry
Mechanical Engineering
Transistor
Bioengineering
Nanotechnology
Heterojunction
General Chemistry
Condensed Matter Physics
law.invention
Semiconductor
Semiconductors
law
Optoelectronics
General Materials Science
Wafer
Graphite
Electronics
Thin film
business
Subjects
Details
- ISSN :
- 15306992
- Volume :
- 13
- Issue :
- 12
- Database :
- OpenAIRE
- Journal :
- Nano letters
- Accession number :
- edsair.doi.dedup.....2caeb15a8a856e452523ab0ba60fa242