Search

In this article, we report the reliability characterization of 7-nm technology, in which the highly scaled sixth generation of FinFETs and 256-Mb static random access memory (SRAM) cells were newly developed by featuring extreme ultraviolet (EUV). The intrinsic reliability mechanisms of 7-nm FinFET including hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric-breakdown (TDDB) are similar to that of the previous nodes, and would not be degraded by introducing the scaled FinFET. Moreover, we found that the use of EUV single patterning of middle of line (MOL) and back end of line (BEOL) improves reliability distribution remarkably as compared to the previous nodes using argon fluoride (ArF) multiple patterning techniques. We successfully demonstrated SRAM and logic high-temperature operating life (HTOL) up to 500 h, indicating the robustness of product-level reliability. These findings strongly suggest that the 7-nm technology featuring EUV is fully ready for high-volume manufacturing as well as providing a near future logic production with high-quality reliability.

In this paper, we report the extensive reliability characterization and modeling of multiple FinFET technology generations. Comprehensive study on intrinsic reliability of the FinFET such as hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB) is introduced. With taller and narrower Fin shape for higher performance, the increased FinFET self-heating (FSH) and its reliability impact are characterized and modeled. The localized layout related reliability on FinFET is also experimentally investigated to provide insights for understanding of local layout effect (LLE). The reliability optimization with Far-BEOL forming gas anneal to passivate the dangling bonds and improve dielectric integrity is analyzed by accounting for the effects of anneals using various gas sources (including high/normal pressure $\mathbf{D}_{2},\ \mathbf{H}_{2}$ , and $\mathrm{N}_{2}$ ). FinFET product HTOL data demonstrates reliability exceeding 10 years of life.

Far-BEOL forming gas anneal has been used to passivate the dangling bonds and to improve the integrity of the gate dielectric [1-2]. The extensive reliability characterization study was conducted on 14nm FinFETs to study the effects of anneals using various gas sources (including high/normal pressure D2, H2, and N2). Despite that high pressure D2 (HP D2) anneal gave the best I/O NFET HCI reliability performance, most of the other anneals also provided reasonable and comparable reliability results that can provide as more cost-effective alternate process approach. Product HTOL data using various DOEs demonstrated reliability exceeding 10yrs of life.

This paper investigates alpha-induced single event transient (SET) in combinational-logic in 10 nm bulk FinFET technology. FinFET technology improves SET in combinational-logic as well as single event upset (SEU) in flip-flops.

In this paper, BTI variation of 10nm FinFET is experimentally studied taking into account of the local layout effects. Although Fin shape is further optimized in 10nm compared with 14nm, the BTI and its variation show no obvious differences from the previous node. And this result is further confirmed by SRAM level reliability characterizations. In addition, the impacts of local layout effects on reliability are also investigated. Through Si data, BTI and its variation are not very sensitive to the layout effects which show within about 10% of the differences and the adopted structure for qualification can cover with all the different structures. Moreover, the results are also helpful for the accurate reliability modeling and circuit simulation.

One of the major challenges for the gate-first approach in high-k/metal-gate (HK/MG) transistor fabrication is finding the gate stacks that can survive high temperature annealing (typically over a thousand degrees, °C) and compatible with strain techniques. As transistor size scales down, it becomes hard to find the metals which can endure 1000°C or the high annealing temperature without the metal work function shift that causes performance degradation. Therefore, a gate-last technology where high temperature process has been decoupled from the metal gate processing has been introduced [1]. However, reliability concern is becoming severe, since gate stack can’t suffer enough thermal treatment [2]. In this paper, time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI) of transistors fabricated in 20nm HK/MG gate-last technology are studied with focus on nitrogen enrichment inside the HK/MG stack and its reliability effects.

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO"2 thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0

The conventional source/drain series resistance (Rsd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in Id and there is insufficient physical modeling. In this letter, we propose a modified Rsd extraction method that uses an optimized Id equation and a threshold voltage (Vth) extraction procedure for NWFETs. The Id equation is modified for the geometry of the NWFET, and Vth is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified Id equations to NWFETs. Therefore, Rsd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (dNW) when normalized by dNW, indicating that the extension resistance is the dominant component in the total Rsd.

This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance.

The hot-carrier (HC) effect in high-k/metal-gate nMOSFETs is characterized using radio-frequency (RF) small-signal parameter analysis. To explain a novel HC degradation of RF small-signal parameters, we propose a modified surface channel resistance model that can be applied to not only conventional SiO2/poly-Si-gate nMOSFETs but also high-k/metal-gate nMOSFETs.

We study quasi-ballistic transport in nanoscale high-κ/metal gate nMOSFETs based on radio-frequency (RF) S-parameter analysis. An RF S-parameter-based simple experimental methodology is used for direct extraction of device parameters (i.e., Leff, Rsd, and Cinv) and the effective carrier velocity veff from the targeted short-channel devices. Furthermore, an analytical top-of-the-barrier model, which self-consistently solves the Schrodinger-Poisson equations, is used to determine the ballistic carrier velocity vinj at the top of the barrier near the source. Based on the results of the experimental extraction and analytical calculations, backscattering coefficient rsat and ballistic ratio BRsat are calculated to assess the degree of the transport ballisticity for nMOSFETs. It is found that conventional high-κ/metal gate nMOSFETs will approach a ballistic limit at an effective gate length Leff of approximately 7 nm.

In this letter, we analyze the nonsaturating upturns of capacitance under strong accumulation bias in MOS capacitors with high-k dielectrics. By comparing the electrical properties of dielectric samples with and without HfO2 and by varying the ambient temperature, it is found that the conduction through the shallow trap levels in the HfO2 bulk produces not only a steady-state current but also a dynamic current, which, in turn, causes the upturn in capacitance. The addition of RC shunts to the conventional small-signal model is proposed to consider the dynamic leakage effect. The model's effectiveness is verified by fitting the measured impedance spectrum and the measured capacitance. We suggest that measuring at a high frequency of hundreds of megahertz eliminates the dynamic interaction by shallow trap levels, allowing gate capacitance to be successfully reconstructed.

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

Quasi-ballistic transport in nanoscale high-k/metal gate nMOSFETs is investigated by RF S-parameter analysis. A simple experimental method based on RF S-parameter is used for direct extraction of device parameters (L eff , C gc , R SD ) and the effective carrier velocity (v eff ) from targeted short channel devices. The ballistic carrier velocity (v inj ) at the top of the barrier near the source is determined by using the top-of-the-barrier model which self-consistently solves Schrodinger-Poisson equations. Combining the experimental extraction and the analytical top-of-the-barrier model, the backscattering coefficient (r sat ) is calculated to assess the degree of the transport ballisticity for the high-k/metal gate nMOSFETs.

We quantitatively compared the parasitic capacitance of the planar FETs and the DG FinFETs. Optimization with a fixed Sfin-to-H fin ratio significantly reduces C para /W, which renders DG FinFETs comparable to planar FETs. Process variation on W fin and H fin should be controlled, otherwise, the C para uniformity will be worse for DG FinFETs than it is planar FETs.

Hot carrier effects on RF small-signal parameters in high-k/metal gate nMOSFETs are characterized by DC and RF measurements. To explain the novel hot carrier-induced degradation, we suggest a modified surface channel resistance model that can be applied to both conventional SiO 2 and high-k nMOSFETs.

We investigate the low-frequency noise characteristics of HfSiON/metal gate nMOSFETs with and without La-doping and report new findings on the impact of La-doping on low-frequency noise of the nMOSFETs. The La-doped devices show lower noise intensity than the un-doped devices and it is attributed to the reduced trap density (N t ) and tunneling attenuation length (λ) caused by the La-doping. In the case of submicron devices, however, the La-doped devices show additional mobility-fluctuation noise at low-field condition and the additional noise intensity increases as the gate length decreases. These results indicate that the advantage of low noise of La-doping technique can decrease or even disappear in case of short-channel devices used for analog applications.

This paper presents a simple equivalent circuit model to characterize a gate impedance of MOS capacitor with high-k dielectric, which exhibited significant dynamic leakage. Series of RC-shunts was added to consider the effects of charge trapping in high-k dielectric. From our model, it is found that two-frequency method using the megahertz range gives us reasonable values for the gate capacitance because the traps with large time constants are unable to response the modulating frequency. Also, parameters for our model are systematically analyzed.

In this paper, we introduce the cylindrical coordinate based flicker noise model for Silicon NanoWire Field Effect Transistor (Si-NWFET) with Gate-All-Around (GAA) structure. For the accurate extraction of the volume trap density, N t , with 1/f noise modeling, the parameters which represent the intrinsic channel properties are determined by rejecting the series resistance R sd effect. Due to the random distribution of traps in Si-NWFETs, the 1/f noise data are obtained by averaging the drain current power spectral density, S id , for several devices. By using the proposed 1/f model, the extracted volume trap density is compared for three different oxide processes (ISSG/RTO/GNOx) and verified by hot carrier stress test.

RF performances of 100-nm metal gate/high-k dielectric nMOSFET and parameters degradation by hot carrier injection to apply to RF integrated circuits are investigated. The attained nMOSFETs RF performances are 132-GHz f T and 44-GHz f max . In addition to RF figures of merit (FOM, f T and f max ), variation of capacitance and resistance is monitored to study hot carrier effects.

We present high pressure hydrogen annel (HPHA) effects in two types contact etch stop layer (CESL) nitride MOSFETs. Performances increased in both samples of using rapid thermal chemical vapor deposition (RTCVD) and plasma enhanced chemical vapor deposition (PECVD) nitride stress layers, but reliability only degraded in PECVD samples after HPHA.

Effects of high pressure hydrogen annealing (HPHA) process on a nitride contact etch stop layer (CESL) MOSFETs is studied. High interface quality by HPHA leads to improved on-current (I on ) and transconductance (G m ) while reliability degradation is acceptable.

We investigate RF performances and hot carrier effects of nMOSFETs at cryogenic temperature. RF performances of HfO 2 dielectric nMOSFET at 77 K are improved more than those of SiO 2 dielectric nMOSFET although DC performances are improved similarly. The nMOSFET with HfO 2 dielectric has 127.4 GHz f T and 75.4 GHz f max at 77 K. In hot carrier injection measurement, g m of HfO 2 nMOSFET at 77 K is degraded more than 300 K although V th shift is less. The cause of g m reduction is discussed related to the trapping.

We have investigated reliability characteristics for a high-k/metal gate MOSFET with strain engineering under constant voltage stress (CVS). Using contact edge stop layer (CESL), tensile and compressive strains are applied to the channel region. Since the compressive MOSFET has more hydrogen in the CESL, the MOSFET has lower reliability characteristics than others. Though the hydrogen can passivate dangling bonds in the high-k dielectric, the passivated bonds are easily broken by voltage stress, which cause degradation of high-k layer.

In this paper, a novel method for effective mobility extraction of the advanced MOSFET devices using RF modeling scheme is proposed. The proposed method is robust to high gate leakage current and parasitic source/drain resistance. Also, this method can substantially reduce error from drain bias mismatch between channel conductance and gate-to-channel capacitance measurement, uses only single device, and is applicable to small-area devices. nMOSFET with HfSiON gate dielectric and TiN gate electrode is demonstrated with the proposed method.

Deuterium annealing has been widely used to help improve hot carrier injection (HCI) reliability of CMOS devices[1]. With introduction of high-k, and especially the gate-last metal gate processes, which decouples the high temperature annealing process, the effectiveness of D2 anneal is further investigated in this report. Especially, 20nm gate-last high-k/metal gate planar transistor was characterized in terms of threshold, gate leakage, charge pumping current, and reliability with and without D2 anneal and show that D2 anneal is very effective in suppressing HCI by up to ~3x. We also show that D2 anneal continues to be effective in 14nm 3-D FinFET transistors. The gate length used in this experiment is 20nm and the width is 1um for the 20nm node gate-last planar transistors. For annealing, pure deuterium gas (D2) is applied to all samples at The passivation rate k2 for between Si and D2 reaction and Vth can be expressed by eq. (1) and (2). As the deuterium pressure goes up, the passivation rate also increases and as a result, the interface trap density (Dit) reduces. Interface trap generation induced substrate current (ICP) was measured by the charge pumping technique in Fig. 1. Process applying the highest annealing pressure results in the lowest ICP. In other words, it explicitly explains that higher D2 pressure had higher D2 absorption rate at the Si/SiO2 interfaces as expressed in eq. (1). Specially in eq. (2), Qit is dependent on the surface potential, which is dependent on the gate voltage. As a result, the decrease in Qit causes successive threshold voltage increase as shown in Fig. 2. PMOS had higher sensitivity to Qit as its performance and reliability characteristics heavily rely on the IL-interface, whereas, NMOS depends more on the high-k region[3]. In addition, Qot, which is a cause for gate leakage current in off-state, can be suppressed through the diffusion of deuterium after annealing. Off-leakage current at subthreshold region decreases by more than 30% both in annealed P/NMOS devices in our experiment. Deuterium annealing process can improves not only device performance but also reliability. Fig. 3 shows HCI and BTI reliability versus stress time respectively. Fig. 3 represents that D2 annealing process improves hot carrier reliability by up to ~3x at 5000sec stress time for PMOS and ~2x for NMOS. Comparing with conventional hydrogen annealing process, deuterium has bigger mass and approximately 100 times slower desorption rate than hydrogen from the silicon[4], so D2 annealing process had less Vth change was anticipated. But, un-optimized additional annealing could also detach the deuterium from the silicon interface, that can cause increase in the number of dangling bonds in silicon interface. As shown in Fig. 3, there is a big improvement in HCI reliability, whereas, there are no significant differences in BTI reliability. These phenomenon is expected by deuterium desorption mainly due to the channel hot carriers. The channel hot carriers results in the reappearance of the interface defects, and degradation during HCI. Threshold voltage shift as a function of various BTI stress temperature with high pressure annealed wafer was extracted, and thermal activation energy of ~0.2eV was found from the temperature dependence in 20nm gate-last high-k/metal gate CMOS device. Fig. 4 shows the charge pumping result in 14nm FinFET devices. Comparison of ICP between 1x anneal (after M1 process) and 2x anneals (M1, and Final Metal) is shown. There is very small incremental change with 1x D2 anneals at the final metal layer. It means that D2 diffusion process is not the rate-limiting step, and the number of D2 annealing time is negligible in 3-D FinFET devices. We also verify hot carrier impact on the devices with different oxide thickness. More degradation is found in EG than SG as shown in Table 1. It is expected that higher voltage stress during HCI can easily detach the deuterium near Si interfaces in EG than SG, it causes more Vth shift degradation in EG. In conclusion, deuterium incorporation has improved HCI by 2x while achieving higher performance in 20nm gate-last high-k/metal gate technology. The effect of D2 anneal is highly expected to be continued in 14nm 3-D FinFET device. In the near future, D2 impacts using various split conditions on 14nm 3-D devices will be more deeply studied. References Kangguo Cheng, et al., Microelectronic engineering 56, pp353-358, 2001 Ki-Dan Bae, et al., ECS transaction 58 (70), pp3-7, 2013 Sangwoo Pae et al., IRPS, pp352-357, 2008 Jae-Sung Lee, Transactions on electrical and electronic materials, vol. 13, No. 4, pp188-191, August 25, 2012 Figure 1

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔV th) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔV th caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of V th. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.