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The local integration of III–Vs on Si is relevant for a wide range of applications in electronics and photonics, since it combines a mature and established materials platform with desired physical properties such as a direct and tuneable bandgap and high mobility. The large thermal expansion coefficient and lattice mismatch, however, pose a challenge for the direct growth of III–Vs on Si. In this paper we will review fabrication concepts to overcome this mismatch for the local integration of III–Vs on Si. In particular, we will briefly discuss processing methods based on aspect ratio trapping, nanowire growth, and template-assisted selective epitaxy (TASE). The focus of this review will be on the latter, where we will provide an overview of the different possibilities and embodiments of TASE and their promise for locally integrated active photonic devices.

International audience; We report on the selective area growth of InAs nanowires (NWs) by the catalyst-free vapor−solid method. Well-ordered InAs NWs were grown on GaAs(111)B and Si(111) substrates patterned with a dielectric mask using hydride vapor phase epitaxy (HVPE). Vertical and high aspect ratio InAs NWs with a hexagonal shape were grown on both GaAs and Si substrates. The impact of the growth conditions on the InAs morphology was investigated. The final shape of the InAs crystal was tuned from a NW to a nanoplatelet by controlling growth conditions such as growth temperature, vapor phase composition, and mask pattern. The influence of the aperture size on the nucleation density and then on the morphology of InAs is discussed. Small openings resulted in the formation of a single nucleus per hole, which was then converted to a NW. For larger apertures, the number of nuclei increased, leading to both three-dimensional crystals and NWs. The effect of growth temperature and the III/V ratio on the kinetics and thermodynamics of InAs growth is also discussed. The growth was first optimized on a GaAs(111)B substrate and then performed on Si, which is more suitable to develop devices. Finally, the absorbance and photoluminescence measurements were carried out on the InAs NW arrays, demonstrating the high potential of HVPE-grown InAs NWs for future multispectral photo-detection devices.

III-V semiconductors are ideal for light sources due to their tunable and direct band gap in the telecommunication band [1] , [2] , but their monolithic integration on Si is challenging, because of the significant thermal, polarity and lattice mismatch. At IBM Research we developed template-assisted selective epitaxy (TASE) [3] , [4] , where III-Vs nucleate at a confined Si seed and grow within an empty predefined oxide template. Using TASE, InP whispering gallery mode (WGM) lasers on Si emitting at ~840nm with comparable performance to wafer bonded devices were demonstrated [5] . To fully leverage the potential of integrated photonics, operation beyond the Si absorption edge is desired. Here, we extend TASE to the growth of InGaAs WGM cavities and demonstrate evidence of lasing at 300 K and 1530 nm. We subsequently compare the devices with previously reported InP WGM lasers.

As conductors in electronic applications shrink, microscopic conduction processes lead to strong deviations from Ohm's law. Depending on the length scales of momentum conserving ($l_{MC}$) and relaxing ($l_{MR}$) electron scattering, and the device size ($d$), current flows may shift from ohmic to ballistic to hydrodynamic regimes and more exotic mixtures thereof. So far, an in situ, in-operando methodology to obtain these parameters self-consistently within a micro/nanodevice, and thereby identify its conduction regime, is critically lacking. In this context, we exploit Sondheimer oscillations, semi-classical magnetoresistance oscillations due to helical electronic motion, as a method to obtain $l_{MR}$ in micro-devices even when $l_{MR}\gg d$. This gives information on the bulk $l_{MR}$ complementary to quantum oscillations, which are sensitive to all scattering processes. We extract $l_{MR}$ from the Sondheimer amplitude in the topological semi-metal WP$_2$, at elevated temperatures up to $T\sim 50$~K, in a range most relevant for hydrodynamic transport phenomena. Our data on micrometer-sized devices are in excellent agreement with experimental reports of the large bulk $l_{MR}$ and thus confirm that WP$_2$ can be microfabricated without degradation. Indeed, the measured scattering rates match well with those of theoretically predicted electron-phonon scattering, thus supporting the notion of strong momentum exchange between electrons and phonons in WP$_2$ at these temperatures. These results conclusively establish Sondheimer oscillations as a quantitative probe of $l_{MR}$ in micro-devices in studying non-ohmic electron flow., 14 pages with 4 figures

Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III–V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies—combining both TFETs and MOSFETs—could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal–oxide–semiconductor (CMOS) platform. Here, we report a scaled III–V hybrid TFET–MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec−1 for TFET devices and 62 mV dec−1 for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types. InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal–oxide–semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power logic systems.

Integration of high-quality semiconductor-superconductor devices into scalable and complementary metal-oxide-semiconductor compatible architectures remains an outstanding challenge, currently hindering their practical implementation. Here, we demonstrate growth of InAs nanowires monolithically integrated on Si inside lateral cavities containing superconducting TiN elements. This technique allows growth of hybrid devices characterized by sharp semiconductor-superconductor interfaces and with alignment along arbitrary crystallographic directions. Electrical characterization at low temperature reveals proximity induced superconductivity in InAs via a transparent interface.

The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In0.5Ga0.5As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm2 at -1 V and a responsivity up to 0.2 A/W at -2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results., Nature Communications, 13, ISSN:2041-1723

In this work we will discuss the use of Template-Assisted Selective Epitaxy (TASE) for the monolithic in-plane integration of active III-V photonic devices on silicon. We will show the use for highspeed InGaAs detectors, as well as for hybrid III-V/Si photonic crystal structures.

Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality (Q)-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate and hence, in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 {\mu}m to 1.6 {\mu}m at room temperature validating the device concept and its potential towards fully integrated light sources on silicon., Comment: 10 pages, 5 figures

In the present talk we discuss the development of the epitaxial technique Template-Assisted Selective Epitaxy (TASE)and its application for the monolithic integration of scaled III - V active photonic devices on silicon. A unique advantage of TASE for silicon photonics applications is that it enables a truly local integration of III-V material at precisely defined positions, it is therefore particularly suited for densely Integrated nanophotonic devices. Here we will discuss our work on InP-based microdisk lasers fabricated by either direct TASE growth or via the use of micro-substrates. Optical mode simulations using Lumerical are used to explore the design space. Notably, we are exploring the use of metal-clad cavities for further light confinement. The metal-clad cavities enable scaling of the laser diameter beyond what is achievable with a pure photonic cavity. Thermal simulations are used to explore the impact of the metal-cladding as a heat sink as opposed to plasmonic operation. We also evaluate the potential for electrical actuation and will show first results on monolithic photodetectors, using Sentaurus simulations to improve our understanding of device performance.

In the present talk we discuss the application of Template-Assisted Selective Epitaxy (TASE) for the monolithic integration of III-V active photonic devices on silicon. The main concept of TASE relies on the guided growth of III-Vs within a confined oxide template. At one extremity of the template there is access to silicon to start the nucleation, and subsequently it is the template which guides the growth progression. This decoupling of the resulting geometry from the growth mode and substrate orientation, results in a larger processing window as we no longer rely on the growth conditions to tune the geometry, as well as a number of other advantages. A further unique advantage of TASE for silicon photonics applications is that it allows for the truly local integration of III-V material at precisely defined positions, since the location of the III-V may be defined with nm-scale precision in the same lithographic step as silicon passives. TASE was originally developed for electronics, but in recent years we have expanded it to enable several photonic devices. In the present talk, I will discuss our work on GaAs and InP microdisk lasers fabricated by either direct growth or via the use of micro-substrates. These devices show lasing at room temperature around 870 nm with thresholds of about 10 pJ/pulse. We also explore the use of metal-clad cavities for further light confinement.

Hexagonal SiGe has been theoretically shown to feature a tunable direct bandgap in the range 0.4-0.8eV. We study arrays of site-selectively grown Si_(1-x)-Ge_x nanowires (NWs) grown using the crystal transfer method in which wurtzite GaP core NWs are used as template for SiGe growth. Our approach opens up routes towards photonic band-edge lasers using group-IV NWs. Low-temperature µPL studies of arrays of SiGe NW-arrays reveal strong emission at 0.395eV and linear power dependence for weak excitation levels (P_ex~0.01-1kW/cm^2). For P_ex>4kW/cm^2, a new peak emerges at 0.37eV with an intensity that increases according to ~(P_ex)^5, indicative of stimulated emission close to the photonic band-edge.

The tunnel FET (TFET) is considered as one of the most promising devices for ultra-low power operation, and it is clear that heterojunction devices are required to achieve simultaneously steep slope and high on-current (Ion). However, technologically, heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this paper we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development. In particular we will focus on the role of defects on device performance.

In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such as heterostructure channel stacks, which offer increased carrier mobility towards improved RF and RF-CMOS performance. Recent progress in tunneling field-effect transistors (TFETs) have enabled the TFET architecture as a process module, allowing for dense integration with MOSFETs on the same chip towards an extremely low-power CMOS technology. Finally, we highlight emerging applications for III-V devices at cryogenic temperatures, where there is a rising need for low-power electronics to support the scaling of quantum computers. The unique properties of III-V, their high mobility and band gap engineering make them highly suitable for this application.

The continuous scaling of electronic devices has brought Si based Complementary-Metal –Oxide-Semiconductor (CMOS) technology close to its limits, requiring novel materials and approaches to increase performance. Group III-V semiconductor nanowires have evolved as promising candidates due to their superior carrier mobility, saturation velocity and capability for bandgap engineering and integration in heterostructures, as well as their potential for use in active photonic devices. However, CMOS compatible, epitaxial integration of III-Vs on Si(100) remains challenging, mainly due to the formation of crystal defects, significantly reducing device performance. Selective Area Growth (SAG)1,2 and epitaxial lateral overgrowth (ELO)3–5 have both been demonstrated to reduce defects due to lattice mismatch. In a more recent method referred to as Template-Assisted Selective Epitaxy (TASE)6–10 nanostructures are grown entirely within pre-defined hollow template cavities containing a small Si seed, thus minimizing the...

We present and evaluate a novel integration approach for III-V microdisk cavities on Si. We demonstrate InP room-temperature microdisk lasers and compare the performance to similar InP microdisks fabricated via direct wafer bonding. InP allows for future integration of QWs for the NIR spectral range.

Local integration of III-V active photonic material on silicon is highly desirable for the dense cointegration of electronics and photonics. In this work, we integrate GaAs and InP microdisk lasers on silicon using template-assisted selective epitaxy (TASE). We demonstrate optically pumped room-temperature lasing from InP hexagonal microdisks integrated via TASE and evaluate their performance at lower temperatures.In order to assess and evaluate the viability of TASE, performance of InP hexagonal microdisks are compared to identical devices fabricated via the highly developed and mature direct wafer bonding technique. The lasing threshold as well as the light-in light-out curves of our TASE structures compare favorably with the bonded InP hexagonal microdisks. This demonstrates that our TASE approach is a promising technique for the monolithic integration of optical devices on Si.

Solar cells incorporating III-V nanowires have attracted much attention recently to increase the window of spectral absorption of the current photovoltaic technology based on silicon. This work uses a novel template-assisted selective epitaxy (TASE) to grow III-V nanowires on Si by filling a pre-defined hollow SiO 2 template. We discuss the developed template fabrication steps and demonstrate the integration of GaAs and InGaP nanowires on Si with well-controlled shape, dimensions and composition. This work demonstrates a new step towards the realization of III-V/Si tandem solar cells.

In this work we demonstrate InGaAs-on-Insulator FinFETs monolithically integrated on silicon substrate using selective epitaxy in oxide cavities. Scaled FinFETs, with a gate length down to 20 nm, are fabricated following a CMOS compatible process scheme including replacement meta gate (RMG). The difference between RMG and gate-first (GF) process flows on device performance is discussed. The implementation of an RMG scheme enabled improved off-state behavior, with a 50% reduction of the subthreshold slope. RMG FinFETs with L G = 90 nm and WFIN = 40 nm, show competitive performance, and on-current of 100 µA/µm at fixed off-current of 100 nA/µm.

GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor deposition and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the GaSb growth rate is governed by the desorption processes of an Sb surface layer and, in turn, is insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-blende with a low density of rotational twin defects, and even occasional twin-free structures are observed. Hall/van der Pauw measurements are conducted on 20 nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2/(V s), which matches literature values for high-quality bulk GaSb crystals. Finally, we demonstrate a process that enables cointegration of GaSb and InAs nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-performance complementary III-V metal-oxide-semiconductor technology.