Review: III–V infrared emitters on Si: fabrication concepts, device architectures and down-scaling with a focus on template-assisted selective epitaxy

The local integration of III–Vs on Si is relevant for a wide range of applications in electronics and photonics, since it combines a mature and established materials platform with desired physical properties such as a direct and tuneable bandgap and high mobility. The large thermal expansion coefficient and lattice mismatch, however, pose a challenge for the direct growth of III–Vs on Si. In this paper we will review fabrication concepts to overcome this mismatch for the local integration of III–Vs on Si. In particular, we will briefly discuss processing methods based on aspect ratio trapping, nanowire growth, and template-assisted selective epitaxy (TASE). The focus of this review will be on the latter, where we will provide an overview of the different possibilities and embodiments of TASE and their promise for locally integrated active photonic devices.