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Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates
- Source :
- IEEE Journal of the Electron Devices Society, Vol 3, Iss 3, Pp 176-183 (2015)
- Publication Year :
- 2015
- Publisher :
- IEEE, 2015.
-
Abstract
- In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, Ion of 6 μA/μm (|VGS| = |VDS| = 1 V) and a room-temperature subthreshold swing (SS) of ~160 mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET Ion performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.
Details
- Language :
- English
- ISSN :
- 21686734
- Volume :
- 3
- Issue :
- 3
- Database :
- Directory of Open Access Journals
- Journal :
- IEEE Journal of the Electron Devices Society
- Publication Type :
- Academic Journal
- Accession number :
- edsdoj.1b08e3ce7e24b2696723827b13cd2f9
- Document Type :
- article
- Full Text :
- https://doi.org/10.1109/JEDS.2015.2388793