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141 results on '"Grüttner, Kim"'

1. Design and Analysis of an Online Update Approach for Embedded Microprocessors

Author

Uven, Patrick, Ittershagen, Philipp, Grüttner, Kim, Rannenberg, Kai, Editor-in-Chief, Soares Barbosa, Luís, Editorial Board Member, Goedicke, Michael, Editorial Board Member, Tatnall, Arthur, Editorial Board Member, Neuhold, Erich J., Editorial Board Member, Stiller, Burkhard, Editorial Board Member, Tröltzsch, Fredi, Editorial Board Member, Pries-Heje, Jan, Editorial Board Member, Kreps, David, Editorial Board Member, Reis, Ricardo, Editorial Board Member, Furnell, Steven, Editorial Board Member, Mercier-Laurent, Eunika, Editorial Board Member, Winckler, Marco, Editorial Board Member, Malaka, Rainer, Editorial Board Member, Wehrmeister, Marco A., editor, Kreutz, Márcio, editor, Götz, Marcelo, editor, Henkler, Stefan, editor, Pimentel, Andy D., editor, and Rettberg, Achim, editor

Published
2023
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3. A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms

Author

Dariol, Quentin, Le Nours, Sebastien, Pillement, Sebastien, Stemmer, Ralf, Helms, Domenik, Grüttner, Kim, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Orailoglu, Alex, editor, Reichenbach, Marc, editor, and Jung, Matthias, editor

Published
2022
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7. Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs

Author

Stemmer, Ralf, Vu, Hai-Dang, Grüttner, Kim, Le Nours, Sebastien, Nebel, Wolfgang, Pillement, Sebastien, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Pnevmatikatos, Dionisios N., editor, Pelcat, Maxime, editor, and Jung, Matthias, editor

Published
2019
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10. A program state machine based virtual processing model in SystemC

Author

Schmidt, Tim, Grüttner, Kim, Dömer, Rainer, and Rettberg, Achim

Abstract

The Program State Machine (PSM) Model of Computation offers a rich set of modeling elements to describe behavioral and structural hierarchy, concurrency, synchronization, state transitions and timing. With the rising software complexity of today's embedded systems, the use of Real-Time Operating Systems (RTOS) has become state-of-the-art for nearly all System-on-Chip designs. Regrettably, the PSM model itself has insufficient support for the specification of the preemptive dynamic scheduling behavior of an RTOS. In this paper, we propose a model for dynamically dispatching PSM models on a virtual processing element. Our model aims to abstract from the targeted RTOS and the processor core through execution time annotations and a flexible preemptive scheduler model. Mapping a PSM model to a set of scheduled virtual processing elements only requires minor model transformation and enables early exploration of different processing element mappings and scheduling policies. Our virtual processing model for PSMs is realized on top of the SystemC library. We evaluate the proposed virtual processing model using a Canny edge detection filter.

Published
2015

12. Structural Contracts – Motivating Contracts to Ensure Extra-Functional Semantics

Author

Nitsche, Gregor, Görgen, Ralph, Grüttner, Kim, Nebel, Wolfgang, Rannenberg, Kai, Editor-in-Chief, Sakarovitch, Jacques, Series Editor, Goedicke, Michael, Series Editor, Tatnall, Arthur, Series Editor, Neuhold, Erich J., Series Editor, Pras, Aiko, Series Editor, Tröltzsch, Fredi, Series Editor, Pries-Heje, Jan, Series Editor, Whitehouse, Diane, Series Editor, Reis, Ricardo, Series Editor, Furnell, Steven, Series Editor, Furbach, Ulrich, Series Editor, Winckler, Marco, Series Editor, Rauterberg, Matthias, Series Editor, Götz, Marcelo, editor, Schirner, Gunar, editor, Wehrmeister, Marco Aurélio, editor, Al Faruque, Mohammad Abdullah, editor, and Rettberg, Achim, editor

Published
2017
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17. CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties

Author

Grüttner, Kim, Görgen, Ralph, Schreiner, Sören, Herrera, Fernando, Peñil, Pablo, Medina, Julio, Villar, Eugenio, Palermo, Gianluca, Fornaciari, William, Brandolese, Carlo, Gadioli, Davide, Vitali, Emanuele, Zoni, Davide, Bocchio, Sara, Ceva, Luca, Azzoni, Paolo, Poncino, Massimo, Vinco, Sara, Macii, Enrico, Cusenza, Salvatore, Favaro, John, Valencia, Raúl, Sander, Ingo, Rosvall, Kathrin, Khalilzad, Nima, and Quaglia, Davide

Published
2017
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18. Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties

Author

Hartmann, Philipp A., Grüttner, Kim, Nebel, Wolfgang, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Sano, Kentaro, editor, Soudris, Dimitrios, editor, Hübner, Michael, editor, and Diniz, Pedro C., editor

Published
2015
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19. FPGA based in-memory AI computing

Author

Helms, Domenik, Dariol, Quentin, Grüttner, Kim, Perjikolaei, Behnam R, Einhaus, Lukas, and Gregor, Schiele

Subjects
AI, in memory computing, FPGA
Published
2023

23. Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms

Author

Dariol, Quentin, Le Nours, Sebastien, Helms, Domenik, Stemmer, Ralf, Pillement, Sebastien, Grüttner, Kim, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Nantes Université - pôle Sciences et technologie, Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ), and German Aerospace Center (DLR)

Subjects
[SPI.OTHER]Engineering Sciences [physics]/Other, System Level Simulation, Power Model, Artificial Neural Networks, Multi-Core, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; When deploying Artificial Neural Networks (ANNs) onto multi-core embedded platforms, an intensive evaluation flow is necessaryto find implementations that optimize resource usage, timing andpower. ANNs require indeed significant amounts of computationaland memory resources to execute, while embedded execution plat-forms offer limited resources with strict power budget. Concurrentaccesses from processors to shared resources on multi-core plat-forms can lead to bottlenecks with impact on performance andpower. Existing approaches show limitations to deliver fast yetaccurate evaluation ahead of ANN deployment on the targetedhardware. In this paper, we present a modeling flow for timing andpower prediction in early design stage of fully-connected ANNs onmulti-core platforms. Our flow offers fast yet accurate predictionswith consideration of shared communication resources and scalabil-ity in regards of the number of cores used. The flow is evaluated onreal measurements for 42 mappings of 3 fully-connected ANNs exe-cuted on a clock-gated multi-core platform featuring two differentcommunication modes: polling or interrupt-based. Our modelingflow predicts timing with 97 % accuracy and power with 96 % accu-racy on the tested mappings for an average simulation time of 0.23 sfor 100 iterations. We then illustrate the application of our approachfor efficient design space exploration of ANN implementations.

Published
2023

25. Non-invasive Power Simulation at System-Level with SystemC

Author

Lorenz, Daniel, Hartmann, Philipp A., Grüttner, Kim, Nebel, Wolfgang, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Ayala, José L., editor, Shang, Delong, editor, and Yakovlev, Alex, editor

Published
2013
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36. Hybrid Performance Prediction Models for Fully-Connected Neural Networks on MPSoC

Author

Dariol, Quentin, Le Nours, Sebastien, Pillement, Sebastien, Stemmer, Ralf, Helms, Domenik, Grüttner, Kim, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Nantes Université - pôle Sciences et technologie, Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ), German Aerospace Center (DLR), and Charlier, Sandrine

Subjects
[SPI.OTHER]Engineering Sciences [physics]/Other, [SPI.OTHER] Engineering Sciences [physics]/Other, Model of Performance, Multi Processor, [SPI.TRON] Engineering Sciences [physics]/Electronics, Artificial Neural Networks, SystemC simulation, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

National audience; Predicting the performance of Artificial NeuralNetworks (ANNs) on embedded multi-core platforms is tedious.Concurrent accesses to shared resources are hard to model dueto congestion effects on the shared communication medium,which affect the performance of the application. In this paperwe present a hybrid modeling environment to enable fast yetaccurate timing prediction for fully-connected ANNs deployedon multi-core platforms. The modeling flow is based on theintegration of an analytical computation time model with acommunication time model which are both calibrated throughmeasurement inside a system level simulation using SystemC. Theproposed flow enables the prediction of the end-to-end latencyfor different mappings of several fully-connected ANNs with anaverage of more than 99 % accuracy.

Published
2022

38. The Scale4Edge RISC-V Ecosystem

Author

Ecker, Wolfgang, Adelt, Peer, Müller, Wolfgang, Heckmann, Reinhold, Kristic, Milos, Herdt, Vladimir, Drechsler, Rolf, Angst, Gerhard, Wimmer, Ralf, Mauderer, Andreas, Stahl, Rafael, Emrich, Karsten, Müller-Gritschneder, Daniel, Becker, Bernd, Scholl, Philipp, Jentzsch, Eyck, Schlamelcher, Jan, Grüttner, Kim, Palomero Bernardo, Paul, Bringmann, Oliver, Damian, Mihaela, Oppermann, Julian, Koch, Andreas, Bormann, Jörg, Partzsch, Johannes, Mayr, Christian, and Kunz, Wolfgang

Subjects
ecosystem, edge applications, RISC-V
Published
2022

40. Setup of an Experimental Framework for Performance Modeling and Prediction of Embedded Multicore AI Architectures

Author

Dariol, Quentin, Le Nours, Sebastien, Pillement, Sebastien, Grüttner, Kim, Helms, Domenik, Stemmer, Ralf, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Deutsches Zentrum für Luft- und Raumfahrt (DLR), IETR UMR 6164, and Charlier, Sandrine

Subjects
Real-Time Analysis, [SPI.OTHER]Engineering Sciences [physics]/Other, Embedded Artificial Intelligence, [SPI.OTHER] Engineering Sciences [physics]/Other, Model of Performance, Neural Network, Multi Processor, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

Evaluation of performance for complex applications such as Artificial Intelligence (AI) algorithms and more specifically neural networks on Multi-Processor Systems on a Chip (MPSoC) is tedious. Finding an optimized partitioning of the application while predicting accurately the latency induced by communication bus congestion, is hard using traditional analysis methods. This document presents a performance prediction workflow based on SystemC simulation models for timing prediction of neural networks on MPSoC.

Published
2022

41. Universal Safety Format: Automated Safety Software Generation

Author

Haxel, Fredierik, Viehl, Alexander, Benkel, Michael, Beyreuther, Bjoern, Birken, Klaus, Schmedes, Rolf, Grüttner, Kim, and Mueller-Gritschneder, Daniel

Subjects
Model Transformation, Functional Safety, Domain-specific Language, Software Safety Mechanism, Code Generation
Published
2022

45. Towards Probabilistic Timing Analysis for SDFGs on Tile Based Heterogeneous MPSoCs

Author

Stemmer, Ralf, Vu, Hai-Dang, Grüttner, Kim, Le Nours, Sébastien, Nebel, Wolfgang, Pillement, Sébastien, Charlier, Sandrine, University of Oldenburg, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Institute for Information Technology [Oldenburg] (OFFIS), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Nantes Université (NU)-Université de Rennes 1 (UR1)

Subjects
[SPI.OTHER]Engineering Sciences [physics]/Other, Real-Time Analysis, [SPI.OTHER] Engineering Sciences [physics]/Other, Probabilistic SystemC Model, Multi Processor, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; Abstract—Performance and timing prediction of complex parallel data flow applications on multi-core systems is still a very difficult discipline. The reason for it comes from the complexity of the hardware platforms with difficult or hard to predict timing properties and the rising complexity of the software itself. In this work, we are proposing the combination of timing measurement and statistical simulation models for probabilistic timing and performance prediction of Synchronous Data Flow (SDF) applications on tile-based MPSoCs. We compare our work against mathematical and traditional simulation based performance prediction models. We have shown that the accuracy and execution time of our simulation can be suitable for design space exploration.

Published
2020

46. UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems

Author

Barcelona Supercomputing Center, Agirre, Irene, Onaindia, Peio, Poggi, Tomasso, Yarza, Irune, Cazorla Almeida, Francisco Javier, Kosmidis, Leonidas, Grüttner, Kim, Abuteir, Mohammed, Loewe, Jan, Orbegozo, Juan M., Botta, Stefania, Barcelona Supercomputing Center, Agirre, Irene, Onaindia, Peio, Poggi, Tomasso, Yarza, Irune, Cazorla Almeida, Francisco Javier, Kosmidis, Leonidas, Grüttner, Kim, Abuteir, Mohammed, Loewe, Jan, Orbegozo, Juan M., and Botta, Stefania

Abstract

Following the same trend of consumer electronics, safety-critical industries are starting to adopt Over-The-Air Software Updates (OTASU) on their embedded systems. The motivation behind this trend is twofold. On the one hand, OTASU offer several benefits to the product makers and users by improving or adding new functionality and services to the product without a complete redesign. On the other hand, the increasing connectivity trend makes OTASU a crucial cyber-security demand to download latest security patches. However, the application of OTASU in the safety-critical domain is not free of challenges, specially when considering the dramatic increase of software complexity and the resulting high computing performance demands. This is the mission of UP2DATE, a recently launched project funded within the European H2020 programme focused on new software update architectures for heterogeneous high-performance mixed-criticality systems. This paper gives an overview of UP2DATE and its foundations, which seeks to improve existing OTASU solutions by considering safety, security and availability from the ground up in an architecture that builds around composability and modularity., The research presented throughout this paper has received funding from the European Community’s Horizon 2020 programme under the UP2DATE project (grant agreement 871465)., Peer Reviewed, Postprint (author's final draft)

Published
2020

47. Multi-core devices for safety-critical systems: a survey

Author

Barcelona Supercomputing Center, Perez Cerrolaza, Jon, Obermaisser, Roman, Abella Ferrer, Jaume, Cazorla Almeida, Francisco Javier, Grüttner, Kim, Agirre, Irune, Ahmadian, Hamidreza, Allende, Imanol, Barcelona Supercomputing Center, Perez Cerrolaza, Jon, Obermaisser, Roman, Abella Ferrer, Jaume, Cazorla Almeida, Francisco Javier, Grüttner, Kim, Agirre, Irune, Ahmadian, Hamidreza, and Allende, Imanol

Abstract

Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements., This work has been partially supported by the Spanish Ministry of Economy and Competitiveness under grant TIN2015-65316-P, Basque Government under grant KK-2019-00035 and the HiPEAC Network of Excellence. The Spanish Ministry of Economy and Competitiveness has also partially supported Jaume Abella under Ramon y Cajal postdoctoral fellowship (RYC-2013-14717)., Peer Reviewed, Postprint (author's final draft)

Published
2020

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