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Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms

Authors :
Dariol, Quentin
Le Nours, Sebastien
Helms, Domenik
Stemmer, Ralf
Pillement, Sebastien
Grüttner, Kim
Institut d'Électronique et des Technologies du numéRique (IETR)
Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes)
Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Nantes Université - pôle Sciences et technologie
Nantes Université (Nantes Univ)-Nantes Université (Nantes Univ)
German Aerospace Center (DLR)
Source :
RAPIDO 2023, Workshop on System En-gineering for constrained embedded systems (RAPIDO 2023), Workshop on System En-gineering for constrained embedded systems (RAPIDO 2023), Jan 2023, Toulouse, France. 8 p., ⟨10.1145/3579170.3579263⟩
Publication Year :
2023
Publisher :
HAL CCSD, 2023.

Abstract

International audience; When deploying Artificial Neural Networks (ANNs) onto multi-core embedded platforms, an intensive evaluation flow is necessaryto find implementations that optimize resource usage, timing andpower. ANNs require indeed significant amounts of computationaland memory resources to execute, while embedded execution plat-forms offer limited resources with strict power budget. Concurrentaccesses from processors to shared resources on multi-core plat-forms can lead to bottlenecks with impact on performance andpower. Existing approaches show limitations to deliver fast yetaccurate evaluation ahead of ANN deployment on the targetedhardware. In this paper, we present a modeling flow for timing andpower prediction in early design stage of fully-connected ANNs onmulti-core platforms. Our flow offers fast yet accurate predictionswith consideration of shared communication resources and scalabil-ity in regards of the number of cores used. The flow is evaluated onreal measurements for 42 mappings of 3 fully-connected ANNs exe-cuted on a clock-gated multi-core platform featuring two differentcommunication modes: polling or interrupt-based. Our modelingflow predicts timing with 97 % accuracy and power with 96 % accu-racy on the tested mappings for an average simulation time of 0.23 sfor 100 iterations. We then illustrate the application of our approachfor efficient design space exploration of ANN implementations.

Details

Language :
English
Database :
OpenAIRE
Journal :
RAPIDO 2023, Workshop on System En-gineering for constrained embedded systems (RAPIDO 2023), Workshop on System En-gineering for constrained embedded systems (RAPIDO 2023), Jan 2023, Toulouse, France. 8 p., ⟨10.1145/3579170.3579263⟩
Accession number :
edsair.doi.dedup.....a7f7b00541fee5720c2b894b6c942eb5