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1. Process Innovations for Future Technology Nodes with Back-Side Power Delivery and 3D Device Stacking

2. Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance

3. Poetry of al-Akhṭal : a close structural, thematic and stylistic analysis

6. 2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications

7. Non-Volatile RRAM Embedded into 22FFL FinFET Technology

8. MRAM as Embedded Non-Volatile Memory Solution for 22FFL FinFET Technology

9. Why do defaults affect behavior? Experimental evidence from Afghanistan

10. Optimization of Impact Resistant Throwable Unmanned Ground Vehicle Using Mathematical Modeling Techniques

11. Impact Testing of Different Materials on Wheels Used in Throwable Unmanned Ground Vehicles

13. EFFECT OF BMI (BODY MASS INDEX) ON BMD (BONE MINERAL DENSITY) IN POSTMENOPAUSAL WOMEN.

14. Research on the Writing History of Arabic Rhetoric Studies and its Importance

15. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size

16. OUTCOME OF PREMATURE RUPTURE OF MEMBRANES -- A STUDY OF 120 CASES IN DHAKA MEDICAL COLLEGE HOSPITAL.

17. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

18. High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

19. Future device scaling - Beyond traditional CMOS

21. A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array

23. 45nm High-k + metal gate strain-enhanced transistors

24. Dielectric breakdown in a 45 nm high-k/metal gate process technology

25. BTI reliability of 45 nm high-K + metal-gate process technology

26. A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

28. Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress

29. A 90-nm Logic Technology Featuring Strained-Silicon

30. A Logic Nanotechnology Featuring Strained-Silicon

31. Understanding stress enhanced performance in Intel 90nm CMOS technology

47. IDENTIFIKASI KAWASAN RAWAN KONVERSI PADA LAHAN SAWAH DI KECAMATAN 2 X 11 ENAM LINGKUNG KABUPATEN PADANG PARIAMAN BERBASIS GIS (GEOGRAPHIC INFORMATION SYSTEM)

48. Control of implant-damage-enhanced boron diffusion in epitaxially grown n-Si/p-SiGe/n-Si heterojunction bipolar transistors.

49. Control of implant-damage-enhanced boron diffusion in epitaxially grown n-Si/p-Si1-xGex/n-Si heterojunction bipolar transistors

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