100 nm gate length high performance/low power CMOS transistor structure.

Authors :: Ghani, T.
Ahmed, S.
Aminzadeh, P.
Bielefeld, J.
Charvat, P.
Chu, C.
Harper, M.
Jacob, P.
Jan, C.
Kavalieros, J.
Kenyon, C.
Nagisetty, R.
Packan, P.
Sebastian, J.
Taylor, M.
Tsai, J.
Tyagi, S.
Yang, S.
Bohr, M.
Source :: International Electron Devices Meeting 1999 Technical Digest (Cat No99CH36318); 1999, p415-418, 4p
Publication Year :: 1999

Language :: English
ISBNs :: 9780780354104
Database :: Complementary Index
Journal :: International Electron Devices Meeting 1999 Technical Digest (Cat No99CH36318)
Publication Type :: Conference
Accession number :: 92555773
Full Text :: https://doi.org/10.1109/IEDM.1999.824182