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Despite tremendous interests in ferroelectric field-effect transistors (FEFETs) for embedded, data-centric applications, the fundamental trade-offs between memory window (MW) and write voltage to optimize performance remains poorly understood. To that end, we fabricated ferroelectric (FE) $ZrO_{2}$ based, p-type FEFETs and studied the impacts of FE and the interfacial oxide layer (IL) thicknesses ( $t_{FE}$ and $t_{IL}$ , respectively) on device performance. We observe that a decrease of $t_{FE}$ and $t_{IL}$ reduces not only write voltages for erasing and programming, but also the memory window. A quantitative analysis of these results offers the following insights and guidelines for FEFET design: to decrease write voltages, all of $t_{FE}$ , $t_{IL}$ and coercive field of FE needs to decrease, and to compensate for the subsequent decrease in MW, the polarization of the FE needs to be increased - notwithstanding the fact that the reliability implications of the magnitude of FE polarization still need to be understood.

Recently, multilevel Resistive RAM (ReRAM) stacks have been demonstrated to have promising applications related to inference and learning in artificial intelligence. However, extensive studies on energy efficiency, repeatability, and retention during multilevel operations have not been undertaken previously. It is, therefore, required to investigate the device characteristics such as compliance current (CC) dependence, forming voltage, memory window, symmetry, and switching energy. Furthermore, understanding the impact of dielectric composition and/or electrode materials is necessary to optimize the device performance, such as switching characteristics, endurance, and energy efficiency. In this work, we have investigated a two-terminal ReRAM device, 10nm Ti/50nm TiN/7nm HfO2/1nm Al2O3/PVD Ti/TiN (Fig. 1), with bilayer switching dielectrics of HfO2 and Al2O3. In this case, the embedded Al2O3 layer was placed between the HfO2 layer and the top electrode (TE). We have evaluated the gradual resistance change capability with varying CC. The I-V characteristics of the ReRAM device, measured by a dc double sweep, is shown in Fig. 2. The device switched at a compliance current of 50nA with a forming voltage of 1.85 volts to set to low resistance state (LRS) from the high resistance state (HRS). The subsequent reset from LRS to HRS was obtained during the negative voltage ramp showing a bipolar switching operation (Fig. 2). With the variation of compliance current (50 nA to 70 nA), the LRS was gradually changed indicating multilevel LRS. It is known that by increasing the compliance current with a gradual set process, multiple conducting filaments (CFs) or thicker CFs can form setting the different LRS values and the annihilation of the CFs during the reset process can also moderately vary the HRS values. The resistance ratio between the HRS and LRS was observed to be more than 1000. The devices were subjected to 100 cycles of SET and RESET operations at different CCs without any failures. When the embedded Al2O3 layer was placed between the bottom electrode (BE) and the HfO2 layer, the switching compliance current was increased to 10 mA with a reduced forming voltage of 1.6V. Multilevel LRS states were observed for this device when the CC was varied from 10 mA to 12 mA for 100 cycles at each CCs. To further understand the behavior, TEM depth profile measurements were carried out, and it was observed that Al2O3 diffused from the peak at the as-deposited location into the HfO2 layer in both cases. While this improved the uniformity in switching behavior, the low switching energy consumption in the case of an embedded Al2O3 layer in between the HfO2 layer and the TE layer remains to be investigated. Replacing the PVD Ti layer (Fig. 1) with ALD Ti in the TE when an Al2O3 layer was between the bottom electrode (BE) and the HfO2 layer reduced the switching compliance current from 10 mA to 100 nA. This suggests that the metal quality of the TE can impact the switching behavior of the multilevel ReRAMs. Figure 1

Recently, HfO2-based resistive random-access memory (RRAM) devices have shown promise as candidates for in-memory computing applications. By engineering the distribution of defects or oxygen vacancies, the switching dielectric can potentially enable low power switching and multi-conductance levels. A higher concentration of oxygen vacancies closer to the top electrode a two-terminal RRAM device with a HfO2/Al2O3 bilayer structure reduces switching energy (1). Introducing excess oxygen vacancies near the top electrode through a hydrogen plasma treatment with a Ru as top electrode reduces the switching power of the device (2). In this work we study the pulsed SET operation of different HfO2-based RRAM devices for their possible uses as multi-level cells. We have compared two different RRAM devices with HfO2-based dielectrics. Device-A is prepared with hydrogen plasma treatment at mid-point of HfO2 deposition (10nm Ti/50nmTiN/3nm HfO2(plasma treatment) 3nm HfO2/5nm Ru/5nm ALD TiN/ 50nm PVD TiN). Whereas Device-B constitutes a HfO2/Al2O3 bilayer structure (10nm Ti/50nmTiN/7nm HfO2/1nm Al2O3/5nm Ru/5nm ALD TiN/50nm PVD TiN). Both the devices have Ru as the top metal. Fig. 1 and Fig. 2 show the conductance modulation obtained by applying successive pulse sequences (80 pulses) with increasing the pulse width tp (from 4 𝜇s to 10 ms) every 20 pulses where the pulse height, Vp, remained fixed at 2V during the experiment. A read pulse with voltage Vr=0.1V and pulse width tr=1ms is applied immediately after each pulse. The forming compliance current in Device-A is seven time lower than Device-B. Both devices clearly show promising behavior of multi-level conductance. Figure 1

The recent discovery of ferroelectric behavior in doped hafnia-based dielectrics, attributed to a non-centrosymmetric orthorhombic phase, has potential for use in attractive applications such as negative differential capacitance field-effect-transistors (NCFET) and ferroelectric random access memory devices (FeRAM). Alloying with similar oxides like ZrO2, doping with specific elements such as Si, novel processing methods, encapsulation and annealing schemes are also some of the techniques that are being explored to target structural modifications and stabilization of the non-centrosymmetric phase. In this study, we utilized synchrotron-based x-ray diffraction in the grazing incidence in plane geometry (GIIXRD) to determine the crystalline phases in hafnia-zirconia (HZO) compositional alloys deposited by atomic layer deposition (ALD). Here we compare and contrast the structural phases and ferroelectric properties of mechanically confined HZO films in metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) structures. Both MIM and MIS structures reveals a host of reflections due to non-monoclinic phases in the d-spacing region between 1.75A to 4A. The non-monoclinic phases are believed to consist of tetragonal and orthorhombic phases. Compared to the MIS structures a suppression of the monoclinic phase in MIM structures with 50% zirconia or less was observed. The correlation of the electrical properties with the structural analysis obtained by GIIXRD highlights the importance of understanding the effects of the underlying substrate (metal vs. Si) for different target applications.

Ferroelectric and antiferroelectric Hf/Zr-based oxide films have recently gained interest for memory and AI applications due to their promise of low power and CMOS compatibility. As Hf/Zr-based oxides are not ‘new’ materials, this paper will start with an overview of past learning on this material system. Recent results on fundamental understanding of the mechanism of ferroelectric and antiferroelectric switching will be presented. Challenges in implementation of this material system in high volume manufacturing will be discussed.

Metal-insulator-metal (MIM) stacks, though simple in design, are the backbone device for resistive random access memories (ReRAM) and, as such, play a vital role in emerging memory technologies. In this work, we characterize the impact of Ar, Ar/N2, and BCl3/Cl2 plasma processes on the physical properties of the TiN bottom electrode (BE) surface. The BCl3/Cl2 process increases roughness by 40%. Ar and Ar/N2 processes both decrease PVD TiN roughness by 50%. This reduction propagates through the entire MIM stack. X-ray photoelectron spectroscopy (XPS) indicates that both plasma processes alter the Ti-ON concentration on the TiN surface. The impact of BE surface roughness and composition on MIM electrical properties is currently under investigation.

Ru capping process was demonstrated on 48nm-pitch Cu damascene interconnect with area selective deposition technique of Ru CVD. Ru nucleation and film continuity were optimized by process including wet cleaning and dry surface treatments. Physical analysis and line leakage electrical test were conducted to evaluate Ru capping layer for different process conditions.

In this work, we presented the Hf-Zr system as a case study of materials that were evaluated in the past and are now receiving renewed interest due to its potential use in artificial intelligence (AI). A historical overview of Hf-Zr research and its promising new applications for emerging memories will be shared.

This paper investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks that were subjected to different slot plane antenna oxidation (SPAO) conditions: 1) prior to any high-k atomic layer deposition (ALD); 2) in between Al2O3 and ZrO2ALD layers; and 3) after the ALD of high- ${k}$ layers. The carrier transport mechanisms as a function of temperature on these samples were observed to be different. The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers depending on the SPAO treatments. Fowler-Nordheim tunneling seems to be the dominant transport mechanism at high field range when SPAO was performed after the high- ${k}$ layers were deposited. On the other hand, Poole-Frenkel emission and hopping conduction mechanism are dominant for other two samples in both gate electron injection and substrate electron injection (SEI) modes. The trap center ( $ {\phi }_{\text{t1}} = {0.13}$ eV) remains in the ZrO2 when ZrO2 is not subjected to the SPAO. Trap energy level $ {\phi }_{\text{t1}}$ (0.13 eV) was removed and $ {\phi }_{\text{t2}}$ (0.27 eV) still exists when only Al2O3 oxide layer was exposed to SPAO. Hopping distance, ${a}$ (about 0.3 nm) is extracted by hopping conduction model. After time dependent dielectric breakdown measurement, it was found that if GeO2 exists at the interface then it can be degraded easily by SEI stress. On the other hand, if SPAO was processed in between the high- ${k}$ layers the formation of a GeOx layer enhances the interface quality and provides better immunity to degradation under stress.

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Historically, complementary metal-oxide-semiconductor (CMOS) technology was driven by geometrical scaling of the front-end-of-line (FEOL) transistor but it has slowed down significantly in recent years. On the other hand, back-end-of-line (BEOL) interconnects are projected to continue scaling aggressively to meet power, performance and area targets in advanced nodes. In this paper, we will introduce and review BEOL interconnect options targeting sub-7nm metal pitch with an emphasis on materials and process technologies.

As device feature size continues to scale, new device architecture and dielectric materials with engineered properties are becoming essential in overcoming the issues in scaled CMOS devices such as short channel effects. Some of the recent innovations device makers are exploring for better electrostatic control and improved performance are the introduction of new device architecture such as gate all around devices (nanowires/nanosheets), and channel engineering such as high mobility channel materials (Ge and III-V). Ge is particularly attractive for use as a channel material for P-type MOSFETs due to its high hole mobility and Si VLSI high volume manufacturing (HVM) compatibility. However, there are couple significant remaining challenges to integrating Ge into 300mm Si VLSI HVM which are a stable gate-stack formation and integration of Ge on Si (1-5). In this talk, advances in Ge gate stack engineering will be discussed. Using Si compatible technologies we have demonstrated scaled EOT by engineering both the interface and high-k formation. Reference Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). H Lee, T. Nishimura, C. Lu, S. Kabuyanagi, A. Toriumi, IEDM, 32.5.1 (2014). S. Goley, M. K. Hudait, Materials, 2301 (2014). Xie, S. Deng, M. Shaekers, D. Lin, M. Caymax, A. Delabie, X-P Qu, Y-L. Jiang, D. Dedytsche, C. Detavernier, Semicond. Sci. Technol. 074012 (2012)

Neuromorphic computing represents a potential paradigm shift from conventional von Neumann computing architecture and shows promise for achieving massive parallelism and power efficiency for such data-centric tasks as image recognition and language processing. Based on the concept of synaptic plasticity, human-like machine learning can be potentially realized by use of arrays of electronic synapses that function in an analogous manner to biological neurons. One of the key features of this type of computing is the ability to control synaptic weights in an analog-like fashion for use in both inference and training applications. A number of existing device technologies in non-volatile memory systems exhibit attractive characteristics for such synaptic devices.[1,2] In particular, resistive switching devices (resistive random-access memory or ReRAM) can change and store their conductance value (G) in response to electrical stimuli making them potentially enabling for deep learning applications involving synaptic weights. For ReRAM devices, HfO2-based thin films can be utilized for filamentary oxide ReRAM and are an attractive option due to their fab-friendly processing and current implementation in high-volume manufacturing. In this study, we evaluated atomic layer deposition (ALD) for the growth of HfO2 for integration in both front-end-of-line (FEOL) and back-end-of-line (BEOL) compatible test structures on 300 mm wafers in order to optimize electrical performance for use as synaptic device elements in neuromorphic architectures. The effect of oxidant in the ALD process was evaluated and it was shown that H2O outperformed O3 in terms of better uniformity and lower forming voltage. By utilizing a hydrogen-based plasma either after the deposition or inserted as an intermediate step during deposition we were able to further decrease forming voltage for a fixed dielectric thickness. Reducing deposition temperature to 200°C in conjunction with the hydrogen-based plasma treatment offered an additional tuning knob to further reduce forming voltage. Stable high-resistance switching (> 100 kΩ) with analog behavior in scaled BEOL devices was also obtained using this optimized HfO2-based ReRAM. Additionally, a tight distribution of forming voltage was obtained ensuring that 99.9999% devices in a 14 nm ReRAM module can be formed below the targeted voltage. References Kuzum et al., Nanotechnology, 24, 382001 (2013) W. Burr et al., Advanced in Physics:X, 2, 89 (2016)

In this Letter, we report the percentage of the ferroelectric phase in a 10-nm-thick Hf0.5Zr0.5O2 (HZO) film deposited in a metal-insulator-metal stack by atomic layer deposition. The ferroelectric behavior was confirmed by polarization measurements and piezoresponse force microscopy. Ferroelectric behavior in this material has been attributed most likely to the formation of the polar non-centrosymmetric orthorhombic phase [Muller et al., Appl. Phys. Lett. 99, 102903 (2011)], which is difficult to distinguish from the tetragonal phase in x-ray diffraction due to peak overlap. Using a model for each of the crystal phases of hafnia-zirconia, the phase percentages were estimated using a Rietveld refinement method applied to grazing incidence x-ray diffraction data and a linear combination fit analysis procedure [McBriarty et al., Phys. Status Solidi 257, 1900285 (2020)] applied to grazing incidence extended x-ray absorption fine structure data. Using these methods, it was found that the tetragonal (P42/nmc) phase is the most prevalent at 48–60% followed by the polar non-centrosymmetric orthorhombic (Pca21) phase at 35%–40% with the remainder consisting of the monoclinic (P21/c) phase. Understanding the details of the effect of the phase structure on the electrical properties of these materials is extremely important for device engineering of HZO for logic and emerging nonvolatile memory applications.

One of the key challenges for Ge gate stack is to achieve an improved interface quality between Ge and the high-K dielectric. In order to overcome this limitation, various interface treatments like ozone pre-gate treatment and ozone ambient annealing (1), nitridation of Ge surface (2),formation of a GeO2 layer between Ge and high-K dielectric using ECR plasma technique (3) and formation of an ultra-thin SiO2/GeO2bilayer have been tried. It has recently been reported that slot plane antenna(SPA) microwave plasma treatment helps to improve the EOT and enhances the oxide quality by reducing impurities and leakage current when the dielectric is exposed during or after deposition (4). Moreover SPA oxidation possesses the unique property of having low electron temperature, which makes it a very low damage process compared to other techniques,either inductively coupled plasma(ICP) and electron cyclotron resonance(ECR) plasma (5). In this study we investigated the impact of SPA plasma oxidation (SPAO) treatment in improving the interface quality when MOS capacitors were fabricated on 300mm p-type Ge substrates. SPAO plasma treatments were performed at different steps in the high-k deposition process. The substrate was initially subjected to a dry chemical oxide removal (COR) process. Subsequently, three different sets of samples were prepared with the exposure of SPAO plasma at following locations (Fig.1): CASE-1: SPAO plasma treatment after Al2O3(1nm)/ZrO2(3.5nm) deposition; CASE-2: SPAO plasma treatment was carried out in between Al2O3(1nm) and ZrO2(3.5nm) deposition; CASE-3: the Ge substrate was exposed to SPAO plasma treatment after COR and prior to Al2O3(1nm)/ ZrO2(3.5nm) layer deposition. Al2O3(1nm) and ZrO2(3.5nm) layers were deposited by atomic layer deposition. Capacitance-voltage at multi-frequencies,current-voltage and conductance measurements were performed at room temperature. Parameters like flatband voltage (Vfb), equivalent oxide thickness(EOT), interface state density(Dit),and leakage current were estimated accurately after quantum mechanical corrections and eliminating the series resistance effect. As shown in Fig. 2 lowest fast interface state density is achieved when SPAO plasma treatment was performed after Al2O3 and prior to ZrO2 deposition (CASE-2). A comparable Dit is also observed when plasma exposure was done after the entire gate stack deposition (CASE-1) (Fig.2). From different experimental results significant degradation to both the dielectric quality and interface was observed when SPAO is performed just after COR (CASE-3). References: 1) Zhao Mei et al, Journal of Semiconductors, Volume 34, No. 3, 2013. 2) A. Dimoulas et al, Appl. Phys. Lett., volume 86, no. 3, 2005. 3) Yukio Fukuda et al, IEEE transaction on electron devices, volume 57, No. 1, 2010. 4) M.N. Bhuyian et al, ECS Journal of Solid State Sci and Techn, vol. 3(5), N83, 2014. 5) C. Tian et al, J. Vac. Sci. Technol. A 24, 1421, 2006. Figure 1

For exploring the prospect of higher-k dielectric phase engineering on a high mobility substrate, films of Hf1-xZrxO2 with varying x-values (0 ≤ x ≤ 1) were deposited on Al2O3 passivated Ge substrates using atomic layer deposition (ALD) with a cyclic deposit-anneal-deposit-anneal (DADA) scheme. The evolution of monoclinic to higher-k tetragonal structure with increasing ZrO2 concentration was probed by grazing incident x-ray diffraction and partial reciprocal space maps using the highly brilliant synchrotron x-ray source at the Cornell High Energy Synchrotron Source (CHESS). A primarily amorphous/nano-crystalline matrix of the as-deposited films changed to randomly aligned grains of nanocry stalline MO2 (M=Hf, Zr) after post deposition annealing at 800 °C for 200 seconds. In contrast, the DADA films annealed for same thermal budget showed high degree of preferred orientation along certain crystallographic directions. With increasing ZrO2 content, the structure of the films changed from a monoclinic to a tetragonal phase. A lower amount of ZrO2 (x = 0.33) was required for stabilizing the tetragonal phase in films grown on Al2O3 passivated Ge substrate as compared to similar films grown on a Si substrate via the same DADA process (x ≥ 0.50).

Miniaturization in Integrated Circuit fabrication has scaled to atomic dimensions in recent times. With critical device dimensions moving into the range of ~10nm, atomic layer processing control is becoming essential. Atomic Layer Deposition (ALD) uses separated film components at (or near) self-limiting conditions for atomic level uniformity and thickness control. The unique nature of ALD processing has opened the opportunity for a deposition technique that presents deposition components in a spatially separated method compared to sequential component exposure of traditional systems. Spatial ALD has differentiating characteristics that can benefit IC Fabrication at current fabrication dimensions. Historically, deposition systems for IC fabrication use batch furnace or single wafer configurations. The economic benefit of batch furnace processing has been challenged by the enhanced capabilities of single wafer processing as IC scaling emphasized critical film properties and uniformity. ALD processing has rejuvenated batch furnace benefits since separate exposures of deposition components provides excellent uniformity from self-limiting deposition layers, and lower particle defectivity since the components don’t mix. However, the sequential processing of individual components has strained the efficiencies of batch furnace and single wafer ALD processing. Spatial ALD moves substrates (wafers) through each deposition component separately in space, compared to the time sequential processing of batch furnaces and single wafer processing. There are several advantages to Spatial ALD processing, and several unique capabilities that can apply to IC fabrication. By depositing through movement, the deposition components can be maintained through a steady state, which is advantageous for plasma processing and for limiting peripheral equipment film accumulation. By its nature, the deposition rate of Spatial ALD is controlled by the speed of substrates passing through the deposition zones, which can provide unique controls for deposition. Deposition chemistry and process conditions can be designed to take advantage of Spatial ALD properties for unique benefits in IC fabrication. The presentation will explore some fundamental aspects of Spatial ALD processing, the dependency and opportunities of relevant chemistries, and potential applications for the unique capabilities of Spatial ALD, including unsaturated process conditions.

Multi-patterning processes such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) present new challenges to the semiconductor device manufacturing such as increased relative cost to previous nodes, longer cycle times, and increased (local) edge placement error between grid and cut/block layers. As the scaling requirements continue, the factors driving both EPE and electrical yield such as overlay, critical dimension control (CDU) and stochastics (LCDU) become greater concerns to multi-patterning. In addition to lithographic process variations, the unit processes such as plasma/vapor etch, deposition, wet/cleans can contributes additional variation in spacer/mandrel profiles leading to poor CDU control and ultimately within-wafer pitch walking. In this paper, we outline alternative SAQP integration schemes to improve the feature profile of both mandrel and spacer to minimize process variability. This patterning scheme designated as fly-cut SAQP introduces new concepts such top spacer removal by chemical-mechanical planarization, mandrel foot mitigation layers, multi-layered mandrel for accurate polish end-point and void-free gap fill to realize high fidelity transfer to the underlying hardmask. Finally, we will demonstrate the effectiveness for this new integration scheme as a candidate for multi-color/self-aligned block (SAB) and highlight the additional benefits of using such an approach.

In this paper we present an overview and examples of thin films processing technologies for future generations of leading edge semiconductor devices. We introduce the main driving forces affecting future thin film deposition and etch technologies including the push for 3D (vertical) power, performance and area scaling. We discuss new thin films processes on the near term horizon that enable future devices, improved contacts, scaled 3D interconnects, and advanced patterning technologies followed by a future outlook for scaling.

Even through Ge/high-k interface has been extensively studied the high leakage current associated with these gate stacks continues to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). Since several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are important and bulk defect and interface defect concentration affect the CV and GV characteristics several corrections to the characteristics are required to obtain accurate values. We have measured the CV and GV characteristics of Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN MOS capacitors with three different interface treatments by HP4284 LCR meter using different frequencies. The interface treatments are (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). The plots were corrected by three different methods. Firstly, we removed the effect of sheet resistance, RS . The second approach uses data (capacitance and conductance) measured at two different frequencies to solve two unknown variables (capacitance and conductance) (1). The solved CV plot is closer to the corrected CV plot at 1 MHz rather than that at 100 KHz. This allows us to use 1MHz corrected data to obtain the EOT information. Additionally, this approach helps to verify that 1MHz data is robust assuming that defects do not respond to the other frequencies used here. The third approach is to modify the measurement circuits (2) to enhance CV and GV characteristics. Fig. 1 shows the CV characteristics after the corrections by three different approaches for three different samples. COR&SPAOx samples show excellent CV characteristics. The details of all the correction methods and the advantages of these methods to correct CV and GV will be discussed. We will demonstrate that the correction methods are suitable for accurately measure the interface characteristics. The Dit calculated by two method (conductance and capacitance spectroscopy) (Fig. 2) are compared and discrepancy of the results between different samples and different methods will be explained. References Y. Ding and D. Misra, J. Vac. Sci. Technol. B, 33, 021203, 2015. K.J. Yang and C. Hu, IEEE Trans on Electron Dev, 46(7), 1500, 1999. K.S.K Kwa, S. Chattopadhyay, N.D. Jankovic, S.H. Olsen, L.S. Driscoll, and A.G. O'Neill, Semicond. Sci. Technol., 18(2), 82, 2003. Figure 1

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.

As Si metal oxide semiconducting field effect transistors have continued to scale, SiO2-based gate dielectric and polySi gates have been successfully replaced by high-k dielectrics and metal gate at the 45nm technology node and beyond. In order to continue scaling, improvements of key film properties of the high-k dielectric, such as k-value and leakage current, are needed. The electrical properties of HfO2-based dielectrics may be enhanced by structural modifications, since the k-value is dependent on the crystalline phase (monoclinic k=16, tetragonal k=70 and cubic =29) [1]. HfO2 films typically crystallize into the monoclinic phase, which is its most thermodynamically stable phase [2,3]. Alloying HfO2 with other oxides such as ZrO2, TiO2, Al2O3offer a viable option towards engineering the crystalline phase. In this regards, we have deposited 40 cycles of Hf1-xAlxOy films by atomic layer deposition with Al/(Hf+Al)% ranging from 0 to 25%. A set of samples were annealed under N2 at temperatures ranging from 680 oC to 800oC and compared to the as deposited samples. To investigate the crystallinity of the films, we performed grazing incidence in-plane X-ray diffraction (GIIXRD) on the annealed films and in-situ XRD during an anneal process using synchrotron radiation was used to determine the crystallization temperature (Tc) for the unannealed films. The GIIXRD measurements revealed the presence of non-monoclinic peaks which was also confirmed by the in-situ anneal XRD measurements. The crystallization temperature of the non-monoclinic phase obtained from the in-situ anneal XRD is plotted in Fig.1, where it is shown that higher Al/(Hf+Al)% results in higher Tc. In order to resolve the non-monoclinic phase, extended X-ray absorption fine structure (EXAFS) at was utilized. The EXAFS measurement combined with GIIXRD showed the ALD Hf1-xAlxOy films crystallize into a mixture of the tetragonal and monoclinic phases. The electrical properties were investigated by MOS capacitors with ALD TiN as the metal gate. The electrical measurements show a reduction in EOT after post deposition anneal (PDA). In addition, the leakage current was also reduced by a factor of 10 while maintaining a flat-band voltage that is comparable to PDA HfO2 films under identical conditions. The C-V plots of the as deposited samples and annealed samples are shown in Fig. 2 and Fig.3 respectively. We also investigated the effect of different thermal budgets on the Hf1-xAlxOy films. A ~2Å EOT reduction with lower gate leakage was obtained for devices with post deposition anneal near the crystallization temperature of the Hf1-xAlxOyfilms. However, the electrical performance is degraded for devices with higher or lower post deposition anneal temperature than the films’ crystallization. In summary, we have successfully deposited ALD Hf1-xAlxOy. The crystal phase was confirmed to be a mixed phase of tetragonal with monoclinic. The data shows an enhancement in electrical properties near the crystallization temperature of the Hf1-xAlxOyfilms. Acknowledgements Diffraction measurements were carried out at NSLS (X20A and X20C), BNL, which is supported by the DOE, Division of Materials Sciences and Division of Chemical Sciences, under Contract No. DE-AC02-98CH10886. References [1] X. Zhao et al., Phys. Rev. B, 65, 233106 (2002). [2] E.P Gusev, V. Narayanan, M. M Frank, Phys. Status Solidi A, 201, 1443 (2004). [3] D. A Neumayer, E. Cartier, J. Appl. Phys., 90, 1801 (2001).

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10). In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices. The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004). Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007). M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002). B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000). L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002). W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Use of Hf based high-k dielectric materials enabled CMOS device scaling beyond the 22 nm technology node. In order to scale the equivalent oxide thickness (EOT) to 0.7 nm and beyond, while achieving good reliability performance, improvement of the film properties and the deposition methods are highly desirable. It was observed that, the dielectric constant of ALD HfO2 can be improved by the addition of ZrO2 as it offers higher-k tetragonal stabilization when Zr/(Hf+Zr) percentage is more than 50% (1-2). It has recently been reported that the poor dielectric characteristics of ALD grown oxide films, such as the leakage current, can be improved by exposing the dielectric films to a slot-plane-antenna (SPA) plasma (3). Because of low electron temperature the SPA process causes very little damage as compared to conventional inductively coupled plasma (ICP) or electron cyclotron resonance (ECR) plasma (4). Also cyclic treatment during the ALD deposition process by using room temperature ultraviolet ozone, D2O radical, remote microwave N2O plasma, and/or thermal annealing have shown promising results toward improving film properties (5-7). In this study, for the first time, we examined the performance benefits due to the use of intermediate SPA Ar plasma treatment (DSDS) in the ALD deposition process of Hf1-xZrxO2 with 0%, 31% and 80% Zr/(Hf+Zr) percentages and compared them with the standard deposition process (As_Dep). Zr percentage was varied by precisely controlling the Hf-precursor to Zr-precursor pulse ratio in the ALD cycle. MOSCAPs were formed with TiN as gate material, where ALD Hf1-xZrxO2 was deposited on a SiON interface formed by remote plasma radical flow nitridation of chemically grown oxide on a p-Si substrate. It is observed that, DSDS Hf1-xZrxO2with 80% Zr has the lowest dielectric thickness and interfacial layer thickness as compared to others (Fig. 1(a)). Equivalent oxide thickness (EOT) for different Zr percentages for DSDS and As-Dep processing conditions were also compared. Effect of SPA Ar plasma and Zr addition on the reliability of ALD Hf1-xZrxO2 were monitored from the flat-band voltage shift due to a constant field stress at E= 27.5 MV/cm in the gate injection mode (Fig. 1(b)). Also, the gate leakage current density, before and after stress for different devices were monitored. When subjected to a constant field stress traps are generated in the gate dielectric and at the Si-IL interface. DSDS Hf1-xZrxO2with 80% Zr showed the lowest initial flat-band voltage shift after the first 20-second stress and the subsequent increase of positive charge formation was observed as the stress continued. Devices with intermediate Ar plasma have reduced gate leakage current density before stress and after 1000s stress, which implies suppression of oxide trap formation due to plasma exposure. Intermediate Ar plasma exposure to ALD Hf1-xZrxO2with 80% Zr seems to deposit superior dielectric with better EOT downscaling ability and good reliability performance. While Zr addition helps to produce a fine grain microstructure with less oxygen vacancies (2), SPA plasma further helps by reducing contaminants, increasing mass density, and superior bond structure of the film (3). References 1. K. Tapily et al,ECS Trans., 45 (3) 411-420 (2012). 2. R.I. Hegde, et al, J. Appl. Phys. 101, 074113 (2007) 3. T. Tanimura et al, J. Appl., Phys., 113, 064102 (2013) 4. C. Tian et al, J. Vac. Sci. Technol. A 24(4), 1421(2006). 5. S. Consiglio et al, ECS Trans., 41, 89 (2011). 6. R.D. Clark et al, ECS Trans., 35(4), 815 (2011). 7. A. Delabie et al, J. Electrochem. Soc.,153, F180 (2006). Figure 1(a): Dielectric thickness (filled symbols in the left scale) for DSDS and As-Dep gate oxides and interfacial layer (IL) thickness (open symbols in the right scale) for MOSCAPs with DSDS and As-Deposited HfO2 (0% Zr), Hf1-xZrxO2 (31% Zr), and Hf1-xZrxO2 (80% Zr). (All processes used 44 ALD cycles of HfO2/Hf1-xZrxO2 deposition at 2500 C) Figure 1(b): Flat-band voltage values obtained from Capacitance-Voltage (CV) characteristics for unstressed devices (filled symbols) and after 1000s stress (open symbols) with a constant field stress at E= 27.5 MV/cm in the gate injection mode. (MOSCAPS having HfO2 (0% Zr) are denoted by squares, Hf1-xZrxO2 (31% Zr) are denoted by circles, and Hf1-xZrxO2(80% Zr) are denoted by triangles.)

The relentless downscaling of the semiconductor device feature sizes has resulted in tremendous technological advances such as mobile/portable electronics, internet of things (IOT) just to name a few. New device engineering and dielectric materials with engineered properties are becoming essential in overcoming the issues seen in scaled CMOS devices such as short channel effects (SCE). Mobile device, automotive, IOT, big data, and machine learning will be the growth drivers of the semiconductor industry for the next decades to come. These applications will not be successful without new materials, novel processing and integration schemes. There have been several innovations recently in reducing power such as FinFETs, nanosheets, and nanowires. However, the power supply voltage has not significantly scaled below ~1V due to the physical limitation in transistor operation known as Boltzmann limitation which dictates the inability of scaling down the voltage require to increase the transistor drive current by a decade also known as the subthreshold swing (SS) below 60mV/decade. One solution investigated by device makers and foundries is ferroelectric FET (FeFET). The ferroelectric material acts as a transformer boosting the input voltage hence overcoming the Boltzmann limitation or SS below 60mV/decade. Several scaling boosters are being studied to enable further device performance improvement such as self-aligned gate contact, fully self-aligned via, negative capacitance. In this presentation, applications and challenges associated with implementing high-k dielectrics will be discussed.

Resistive random-access memory (RRAM) device has attracted wide attention for next-generation nonvolatile memory (NVM) application due to simple structure, high cycling endurance, good retention, low power consumption and fast switching time (1, 2). In recent years, RRAM devices are extensively researched for multi-level data storage (3, 4). RRAM devices can be driven to various resistance states by applying suitable compliance current values during the switching operation. In this work, multilevel resistive switching behaviors of RRAM devices with three different dielectric materials like HfO2, HfAlO2 and HfZrO2 are investigated with fixed top/bottom electrodes. To control the resistance state, a thin Al2O3 layer (1 nm) was inserted between the bottom electrode and switching dielectric (Ti/TiN/Al2O3/HfAlO2 or HfZrO2 or HfO2/Ti/TiN). The fabrication details of these devices are presented elasewhere (5). Fig. 1 shows DC endurance cycling on the LRS/HRS resistances of the three RRAM structures, (a) HfAlO2, (b) HfZrO2 and (c) HfO2 for different increasing compliance currents. The endurance cycling is performed with 20 cycles per compliance level. As can be seen from the figure, different low resistance states (LRS) and high resistance states (HRS) are well resolved after dc endurance cycling for HfAlO2 and HfZrO2 based RRAM devices. Devices with HfO2, on the other hand, does not show any multilevel LRS or HRS behavior for increase in compliance current. The reason is possibly due to the lack of oxygen vacancies available in the HfO2-RRAM structure. When HfZrO2 was subjected to a post deposition annealing (PDA) in nitrogen environment, the resistance distribution of LRS and HRS was improved, possibly due to improvement of dielectric quality while the oxygen vacancy concentration remained the same. To further improve the resistance window an additional 2 nm thick TiN layer was added before the Ti layer on top electrode of HfZrO2 based RRAM. The cycle to cycle distribution of HRS/LRS resistance of HfZrO2 based RRAM was significantly improved while the compliance current for switching was increased. In summary, process optimization and electrode selection with HfZrO2 as the switching layer can provide significant multilevel storage in RRAM devices. References: E. Ambrosi, A. Bricalli, M. Laudato and D. Ielmini, Faraday discussions DOI: 10.1039/c8fd00106e (2018). A. Prakash and H. Hwang. Physical Sciences Reviews, vol. 1(6), (2016) Chen, et al., Semiconductor Science and Technology7 (2015): 075002. J. Jang and V. Subramanian. Thin Solid Films 625 (2017): 87-92. D. Misra, S. Sultana, B. Jain, N. Bhat, K. Tapily, R.D. Clark, S. Consiglio, C.S. Wajda, and G.J. Leusink, ECS Trans., vol. 86(2), 77, 2018. Figure 1

We have integrated ALD barrier and Ru liner for novel interconnect integration and have evaluated electrical properties and time dependent dielectric breakdown (TDDB). RC and via resistance were reduced by the ALD barrier, and particularly it was confirmed that TDDB performance can be improved by using ALD TaAlN with an ultrathin film. Accordingly, ALD TaAlN barrier and CVD Ru liner are attractive barrier/liner combination for next generation interconnect integration schemes.

We have recently reported electrical performance improvements of atomic layer deposited (ALD) HfO2 films grown by use of a cyclical deposition and annealing scheme (termed DADA) compared to a single deposition with or without a post-deposition anneal (PDA). Likewise, a process for improving leakage and reliability characteristics of ALD HfZrO by use of an interspersed room temperature ultraviolet ozone (RTUVO) treatments, referred to as multi-deposition multi-room temperature annealing (MDMA), has recently been reported. We have developed a version of this MDMA process on our 300 mm clustered tool with in situ RTUVO treatments interspersed between ALD HfO2 depositions. In this report we compare these two processes (DADA vs. MDMA) for HfO2 dielectric formation in a low temperature MOSCAP flow with in-line measurements of the HfO2 and interface layer thicknesses.

Next generation CMOS devices use a high-κ dielectric layer (HfO 2 , HfSiO, HfSiON and La 2 O 3 ) grown on thin interfacial silicon dioxide as the gate dielectric. The higher dielectric constant of the Hf oxide based film stack allows a decrease in equivalent oxide thickness (EOT). Because the high-κ film stack has a greater physical thickness than an electrically equivalent SiO 2 film, the tunneling current decreases. It is a critical metrology requirement to measure the thickness of silicon dioxide and high-κ film stacks. Spectroscopic ellipsometry (SE) in the far UV wavelength region can be used to differentiate the high-κ films from silicon dioxide. This is due to the non-zero nature of the imaginary part of the dielectric function (beyond 6 eV) in the far UV region for high-κ films. There has been some conjecture that optical studies should be extended beyond 150 nm further into the VUV. This study addresses these concerns through determination of the dielectric function down to 130 nm. We show the fitted dielectric function of hafnium silicates and lanthanum oxide down to 130 nm. X-ray reflectivity (XRR) measurements were also performed on the high-κ films to complement the thickness measurements performed with SE.

We have used spectroscopic ellipsometry (SE) to measure layer thicknesses of HfO 2 /La 2 O 3 and La 2 O 3 /HfO 2 stacks on SiO 2 /p-Si. Two approaches to extract layer thicknesses from a single SE measurement were shown to be inaccurate, possibly due to similarities in the optical dispersions of HfO 2 and La 2 O 3 . The approach where SE data was collected after deposition of each layer and only the thickness of the top layer was determined by modeling was found to be capable of accurately measuring the thickness of each layer. These conclusions are supported by angle resolved X-ray photoelectron spectroscopy (ARXPS), X-ray reflectivity (XRR) and Rutherford backscattering spectroscopy (RBS) measurements.

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

Non-volatile resistive random-access memory (RRAM) devices are currently being investigated as a low power, high density and high-speed alternative DRAM (1). A transition metal oxide dielectric layer is typically used as an insulating layer in a metal-insulator-metal (MIM) structure. To reduce the large variability of switching parameters and high operation current in these RRAM devices, bilayer dielectric structures are being explored. In this work we have used several different bilayer structures using different dielectrics. In each device the bottom electrode (BE) was 10nm Ti/50nmTiN followed by 1nm Al2O3. The second dielectric layer or the switching layer was a 7-nm HfO2 (R3), HfZrO2 (R4 with Hf:Zr%=50%) or HfAlO2 (R1 with Hf:Al%= 3%) followed by the top electrode (TE) constituting of 8nm Ti/6nm ALD TiN+50nm PVD TiN. In some cases, the top electrode was varied to 2nm ALD TiN/8nm Ti/6nm ALD TiN+50nm PVD TiN (R5) by adding a 2nm ALD TiN layer prior to 8nm Ti. Some devices with HfZrO2 (R2) were subjected to a post deposition anneal (PDA) at 700oC for 60 s. In all cases, to enhance the switching characteristics on the top electrode 8 nm Ti was used as the cap layer material except in the case of R5 where 2nm of ALD TiN was deposited prior to 8 nm of Ti. The use of thin dielectric layer of 1nm Al2O3 was to suppress the sneak-path problem (3) in the low resistance state (RON). Comparing the variation of switching layer, it was observed that the device with 1nm Al2O3/7nm HfAlO2 (R1) provided the superior average Roff/Ron values and both set and reset power compared to HfO2 (R3), and HfZrO2 (R4) devices. When the HfZrO2 (R4) devices were compared with the identical device with PDA (R2) Ron increased and Roff decreased for the PDA device, reducing the Roff/Ron value. Variation of cap layer to TiN instead of Ti also showed similar Roff/Ronbehavior. D. Ielmini, Semicond. Sci. Technol. Vol. 31, 063002, 2016. Xiaorong Chen and Jie Feng, Appl. Phys. A, vol. 120, 67 2015 U. Chand, K-C. Huang, C-Y. Huang, and T-Y. Tseng, IEEE Trans. on Electron Devices, vol. 62(11), 3665, 2015

The recent discovery that with certain dopants hafnium oxide can be crystallized in a form that exhibits ferroelectricity has opened up a range of device possibilities(1). We have chosen to work within the Hf/Zr system for our initial studies. The advantages of the Hf/Zr doping system include the similarity in precursors which can enable several running modes for the ALD process including a co-pulsing scenario, as well a cycle ratio scenario for controlling the Zr doping. Because Zr and Hf are so similar structurally as well as chemically, the isologous precursors we employ have essentially identical delivery characteristics, including vapor pressure, relative sticking coefficient and relative decomposition point. Thus we expect the process to be capable of maintaining a highly consistent composition over a broad range of topology. In addition, the relative range of doping for which a strong remnant polarization is observed is much broader for the Hf/Zr system than for other dopants such as Al, Si, etc. which means this system should be more tolerant of small changes in composition than the other doping schemes. Generally, the ferroelectric phase of doped Hf oxide is thought to be a non-centrosymmetric orthorhombic phase that is co-crystallized with some other observable phases. In our studies we have found a strong correlation between the polarizability we observe and signals attributed to a tetragonal phase by grazing incidence X-ray diffraction using synchrotron radiation(2). In terms of electrical performance, we have shown reasonable polarization characteristics for films as thin as 5nm, and demonstrated the feasibility of using these films for multiple potential applications. We have explored the possibility of incorporating these films as gate dielectrics for a ferroelectric memory and have also demonstrated that we can fabricate a transistor exhibiting a steep subthreshold slope ( References: T. S. Böescke, J. Müller, D. Bräuhaus, U. Schröder and U. Böttger, in Technical Digest of the International Electron Devices Meeting, p. 24.5.1 (2011). S. Dey, K. Tapily, S. Consiglio, R. D. Clark, C. S. Wajda, G. J. Leusink, A. R. Woll, P. Sharma, S. Datta and A. Diebold, in Frontiers of Characterization and Metrology for Nanoelectronics, E. M. Secula and D. G. Seiler Editors, p. 223, Monterey, CA (2017). P. Sharma, K. Tapily, A. K. Saha, J. Zhang, A. Shaughnessy, A. Aziz, G. L. Snider, S. Gupta, R. D. Clark and S. Datta, in 2017 Symposium on VLSI Technology, p. T154 (2017).

The continued scaling of MOSFET devices necessitates the scaling of the gate dielectric in terms of equivalent oxide thickness (EOT) and associated k-value. As a replacement for SiO2 based gate dielectrics, which have reached their fundamental scaling limit, Hf-based dielectrics including HfO2, Hf silicate and nitrided Hf silicate have been chosen as viable materials.[1] Though the HfO2-based materials have generally been preferred, recent studies have shown that HfO2 with an admixture of ZrO2, which are both fully miscible, has the potential to provide a higher dielectric constant by means of stabilization of higher-k phases.[2,3] Moreover, the mixed oxide HfxZr1-xO2 has been shown to exhibit improved device performance and reliability compared to HfO2.[4] For the deposition of ultra-thin high-k gate dielectric films on planar structures, chemical vapor deposition may offer advantages in terms of wafer throughput, manufacturability, cost of ownership, and process flexibility compared to the alternately pursued atomic layer deposition based approaches. In this study we investigated the process characteristics and film properties of HfZrO4 (HfO2:ZrO2=1) thin films deposited using metallorganic chemical vapor deposition on a 300 mm production-worthy deposition chamber. The mixed oxide films were deposited using a mixture of Hf-t-butoxide and Zr-t-butoxide (1:1 molar ratio) at a wafer temperature of either 380°C or 480°C using O2 as a co-reactant. The Si wafers had a thin (~8A) layer of chemically grown SiO2. The physical properties of the films were analyzed using various characterization techniques including spectroscopic ellipsometry, corona-oxide-semiconductor (Quantox) leakage measurements, XRR, angle-resolved XPS, RBS, ICP-AES, and TEM. MOS capacitor structures featuring HfZrO4 dielectric were fabricated and tested using C-V and I-V measurements. Key electrical parameters (EOT, leakage current density, VFB) were compared with structures featuring HfO2 deposited using the same deposition system and process conditions used for the HfZrO4 process. The HfZrO4 growth rate (Fig.1) was observed to be the same for both deposition temperatures, thus indicating a mass transport limited growth rate regime. Density was observed to increase with deposition temperature in line with reported values for ALD-deposited HfZrO4 from metal chloride sources.[3] The increase in film density (and possibly decrease in film impurities) is also corroborated by improved Quantox measured leakage (Fig.2) as well as increase in metal coverage rates (Fig.3). Improvements in Jg vs EOT trends were observed when comparing HfZrO4 with HfO2 in MOS capacitor structures. Additionally, no measurable difference in CV hysteresis was observed for HfZrO4 compared to HfO2. In our deposition system an excellent wafer-to-wafer repeatability (0.86%) was observed for a mean thickness of 19 A over a 50 wafer run. These results indicate that MOCVD HfZrO4 is a promising material for advanced high-k applications. Figure 1. XRR measured thickness values and densities for HfZrO4 films deposited at 380°C and 480°C and associated growth rates determined from linear fits.

In this paper we will review some of our previous work on ALD deposited high-K dielectric stacks as well as present some of our more recent advances. We have shown that ALD can be used successfully to deposit high quality high-K gate dielectrics of Hf and Zr oxide. In addition, because of the inherent conformality of ALD processes, these dielectrics can be easily migrated to advanced device structures such as FINFETs. We have also been successful in developing ALD processes to deposit rare earth oxides (REOs), such as Y2O3 and La2O3. These processes are useful in creating layered dielectric structures where the REO functions as a threshold voltage adjustment layer. We use physical and electrical characterization of the films as deposited by ALD, including spectroscopic ellipsometry, corona oxide semiconductor charge measurement, TXRF, AES, angle resolved XPS, HRTEM, AFM, MEIS, and RBS, to provide information on the film growth mechanism and the primary parameters that influence the ALD growth of high-K oxides. We further correlate these findings with basic electrical results obtained from MOSFET and MOSCAP devices fabricated using our ALD processes to understand how process changes affect both the as-deposited films as well as the resulting devices.

Material interactions in advanced high-κ / metal gate stacks can have a significant effect of the performance of completed devices. The effect of these interactions was investigated using planar MOS capacitor stacks that might be used for the gate of a MOS transistor. Gate electrode materials included TaN, TaSiN, and W, and HfSiO and HfSiON were used as the gate dielectric materials with an ultra-thin SiO2 interface between the silicon substrate and the dielectric. Deposition methods included CVD and ALD.

Resistance capacitance time delay in Cu interconnects is becoming a significant factor requiring further performance improvements in future nanoelectronic devices. Choice of alternate interconnect materials, for example, refractory metals, and subsequent integration with underlying barrier and liner layers are extremely challenging for the sub-10 nm nodes. The development of conformal deposition processes for alternate interconnects, liner, and barrier materials are crucial in order for implementation of a possible replacement for Cu interconnects for narrow line widths. In this study, the authors report on ultrathin (∼3 nm) chemical vapor deposition (CVD) grown ruthenium films on 0.5 and 1 nm thick metal nitride (TiN, TaN) barrier layers deposited via atomic layer deposition (ALD). Using scanning electron microscopy, the authors determined the effect of the underlying barrier layer on the coverage of the ruthenium overlayer. The authors utilized synchrotron x-ray diffraction with in situ rapid thermal an...

Germanium devices are widely investigated due to their high hole and electron mobility compared to that of silicon. Mobility above 300 cm2V-1s-1 has been reported for Ge PMOS. On the other hand, Ge NMOS showed poor drive current and low mobility in previous studies. This poor performance is attributed to the inability to form a good Ge/high-k interface (1). They also exhibit hysteresis during the capacitance voltage (C-V) sweep because of the presence of slow trap states near the dielectric substrate interface (2). Recently, the use of a slot-plane-antenna (SPA) Ar plasma during the deposition of ALD Hf1-xZrxO2 on Si substrate was reported to enhance the EOT (equivalent oxide thickness) downscaling potential with a suppressed trap formation in the bulk oxide under electrical stress (3). In this work, we have investigated TiN/HfZrO/Al2O3/Ge gate stack using MOS capacitors with six different Zr/(Hf+Zr) content (0%, 25%, 33%, 50%, 75%, and 100%) in the dielectrics. The dielectrics were subjected to SPA plasma oxidation after the deposition process. Electrical characterization of these devices was studied in order to observe the impact of Zr addition in HfO2. The equivalent oxide thickness (EOT), flat-band voltage (VFB), interface state density (Dit), C-V hysteresis, and leakage current (I-V) behavior were analyzed. Figure 1 shows the comparison of EOT and VFB as a function of Zr content in the dielectrics. Figure 2 presents the C-V hysteresis data (to the left axis) and mid gap Dit (to the right axis) for these devices. The addition of Zr in HfO2 was found to enhance the EOT up to 75% Zr incorporation. These devices also showed lower hysteresis in the C-V characteristics. However, A reduction in EOT for these devices showed to increase the flat-band voltage shift (Fig. 1). While devices with 100% Zr showed the highest EOT value coupled with the lowest mid gap Dit, a reduction in EOT with Zr addition in HfO2 moderately increases the Dit (Fig. 2 to the right scale). Figure Captions: Fig. 1: Equivalent oxide thickness (filled squares to the right scale) and flat-band voltage (open triangles to the left scale) comparison for the addition of Zr in HfO2. Fig. 2: Hysteresis behavior extracted from C-V sweep first from accumulation to inversion and then from inversion to accumulation (filled squares to the left scale) and interface state density by conductance method (open circles to the right scale) for ALD Hf1-xZrxO2/Al2O3 gate stacks on Ge substrate. References: 1. Y. Ding, D. Misra, M. N. Bhuyian, ECS Trans., 69 (5) 313-322 (2015). 2. J. Lin, Y. Y. Gomeniuk, S. Monaghan et al., J. Appl. Phys., 114, 144105 (2013). 3. M. N. Bhuyian, D. Misra, K. Tapily et al., ECS. J. of Solid State Sci. Tech., 3(5) N83 (2014). Figure 1

Introduction of a thin GeO2 as the interfacial layer (IL) seems to be beneficial for formation of high-k gate stacks on germanium substrate. The thickness of GeO2/GeOx impacts the overall equivalent oxide thickness (EOT) because of its low dielectric constant compared to high-k layer. Current trends indicate that the formation of appropriate thickness of GeOx or GeO2 between high-k and Ge substrate seems to have low interface state density (D it). Since ZrO2 showed lower leakage current than HfO2 with similar dielectric high-k stack, ZrO2/Al2O3 bilayer as gate dielectric is becoming popular. Even though excellent gate stacks on germanium substrate has been demonstrated the reliability and the impact of interfacial layer is still unknown. This work investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks with thin GeO2 or GeOx layer, formed when the gate stack was exposed to pre- or post-deposition slot plane antenna plasma oxidation (SPAO). The post Al2O3/ZrO2 deposition SPAO forms relatively thicker GeO2 and post Al2O3 deposition SPAO forms thinner GeO2 whereas pre-deposition SPAO forms thin fragmented GeOx layer at the interface. We have observed that the relatively thicker GeO2 interfacial layer formed after the post Al2O3/ZrO2 deposition SPAO degraded faster during time dependent dielectric breakdown (TDDB) measurements on substrate injection mode compared to the thin GeO2 or GeOx interfacial layers (Fig. 1). The improvement in TDDB degradation for thinner interfacial layer thickness suggests that electrons tunnel through the thinner GeOx IL, and TDDB measured the quality of Al2O3 rather than IL. The TDDB characteristics in gate injection mode suggests that the SPAO can significantly affect the TDDB characteristics GEI mode (Fig. 1). The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers when SPAO was performed after the gate stack deposition. By employing carrier transport mechanisms as a function of temperature in both gate and substrate injection mode we were able to identify the traps that contributes to the TDDB degradation. The trap center (f t1 = 0.13 eV) observed in the ZrO2 when ZrO2 is not subjected to the SPAO, i.e. pre-deposition SPAO. This trap f t1 (0.13 eV) was eliminated for post Al2O3/ZrO2 deposition SPAO. While defects in the ZrO2 layer determines the TDDB characteristics in gate injection mode the GeO2 or GeOx interfacial layer thickness determines the TDDB degradation in substrate injection mode. Figure 1

The kinetics of the hydrogen reduction of tungsten hexafluoride were studied. The growth rate was measured as a function of the process conditions, which were determined in situ by means of laser Raman scattering. The partial pressures were measured at a height of 17 mm above the center of a 100 mm wafer in a cold-wall single-wafer low-pressure chemical vapor deposition reactor. The hydrogen reduction reaction was on the order of 1/6 in WF 6 and 1/2 in H 2 . The activation energy was equal to 64 kJ mol -1 . An analysis of available reaction paths revealed that either the formation or the desorption of HF is the rate-limiting step. Since only one activation energy is present, the rate-limiting step is valid for the complete regime that was investigated.

The influence of adding dichlorosilane (SiH2Cl2) or germane (GeH4) to the SiH4-based reduction reaction of tungsten-hexafluoride (WF6) has been investigated in order to enhance the properties of the silane W-CVD process: e.g. selectivity and step-coverage. It is shown that the kinetics of the silane-dichlorosilane process can be characterised by a surface reaction limitation, thus improving the control of the process. For the mixed SiH4GeH4 reduction reaction of WF6 it is shown that the GeH4 process dominates the reaction kinetics. Also addition of SiH2Cl2 to the GeH4-based reduction of WF6 has been examined. It is found that in this case the formation of W is only slightly influenced. The reaction kinetics are similar to that of the unmodified deposition process.

Electromigration and stress migration in Al metallization are major reliability issues for advanced IC's. Recently it has been shown that, compared to AlSiCu alloy films, alloys containing Si, V and Pd combine excellent plasma etchability with good corrosion resistance, while a high resistance against electromigration is maintained [1]. It is commonly accepted that the resistance against stress migration, i.e. the creep strength, of Al can be improved by addition of alloying elements in combination with appropriate heat treatments (e.g. precipitation hardening). We present data on the influence of alloying elements on the behaviour of stress as a function of temperature for a number of Al-alloy films. Pure mono- and polycrystalline Al, AlSi(1.0 at%)Cu(1.0 at%) and AlV(0.1 at%)Pd(0.1 at%) films were studied. The sputter conditions, the film thickness and the annealing conditions were similar to reliability tests described in the literature. These films are subjected to thermal cycles from 50 to 425°C in a vacuum furnace, while the stress behaviour was measured by means of wafer curvature measurements.

Using a five-step atomic layer deposition (ALD)-anneal (DADA) process, with 20 ALD cycles of metalorganic precursors followed by 40 s of rapid thermal annealing at 1073 K, we have developed highly crystalline Hf1−xZrxO2 (0 ≤ x ≤ 1) thin films (