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The hysteresis effect observed in the transfer characteristics of n-channel bottom-gate hydrogenated polymorphous silicon (pm-Si:H) thin-film transistors (TFTs) is investigated in terms of the channel width. Such phenomenon is observed in devices of wide channel (>20 μm), whereas it diminishes in devices of narrow channel. The hysteresis of wide channel TFTs is mainly due to charges injected from the channel, trapped in the gate dielectric. As the channel width is reduced the edge effect becomes more significant and the effect of carrier injection from the channel is eliminated, which is balanced by the effect of charge injection from the gate electrode.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated, using as channel material hydrogenated amorphous silicon (a-Si:H)/nanocrystalline silicon (nc-Si:H) bilayers, deposited at 230 °C by plasma-enhanced chemical vapor deposition, and SiN x as gate dielectric. The stability of these devices is investigated under three bias stress conditions: (i) gate bias stress ( V G = 25 V, V D = 0), (ii) on-state bias stress ( V G = 25 V, V D = 20 V) and (iii) off-state bias stress ( V G = −25 V, V D = 20 V). It is found that the TFT degradation mechanisms are strongly dependent on the bias stress conditions, involving generation of deep and tail states in the active area of the channel material, carrier injection (electrons or holes) within the gate insulator and generation of donor trap states at the gate insulator/channel interface. The common features and the differences observed in the degradation behaviour under the different bias stress conditions are discussed.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated on amorphous silicon (a-Si)/nanocrystalline silicon (nc-Si) bilayers, deposited at 230 °C by plasma-enhanced chemical vapour deposition. The impact of the channel length on the electrical and low-frequency noise characteristics of the TFTs is investigated. The results show that the 1/ f noise can be interpreted in terms of carrier number fluctuations, except the long channel devices where the 1/ f noise is interpreted in terms of the Hooge’s mobility fluctuations model at low drain currents. The gate insulator trap density has been evaluated, demonstrating that the nc-Si extended underneath the n + drain contact area contributes to the measured noise.

The effect of the channel width dimension on the electrical characteristics of amorphous/nanocrystalline silicon bilayer thin-film transistors (TFTs) is investigated. For comparison, nanocrystalline silicon monolayer TFTs are also studied. The experimental results show that the leakage current is decreased and the back-channel conduction is suppressed in bilayer channel devices. The overall results demonstrate that the performance of bilayer TFTs is enhanced with decreasing the channel width, which is attributed to the corner effect

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.

Localized states in Au/n-GaAs Schottky diodes, with InAs quantum dots (QDs) embedded in GaAs confining layers, were studied by means of low frequency noise measurements at temperatures ranging from 160 K to 299 K. Diodes containing a single array or three arrays of QDs were used; they all exhibited generation–recombination noise at low forward currents, which we attribute to local traps located in the GaAs layer. In the diode with a single array of QDs, a shallow trap level was detected with the activation energy about 0.037 eV, located above the Fermi level. In the diodes with three arrays of QDs we observed, in addition to the shallow level, a deep level located 0.1 eV below the midgap.

The effects of hot carriers on the characteristics of intrinsic offset gated n-channel polysilicon thin-film transistors (TFTs), with channel length L = 10 μm, have been studied in relation to the offset length Δ L . From the evolution of the transfer and output characteristics during stress, the degree of the device degradation is deduced. In devices with Δ L = 0.5 and 1 μm, the on-state current is substantially reduced, whereas the subthreshold region remains almost unaffected. In devices with Δ L = 2 μm, the transfer characteristics are shifted first positively after short stressing time and then negatively, the on-state current is still substantially reduced and well-defined kink is formed in the subthreshold region. The device degradation is found to become more pronounced as the gate offset length increases. A model explaining the post-stress performance of offset gated devices is presented.

Hot-carrier effects in n-channel polysilicon thin-film transistors (TFTs), with channel width W=10 /spl mu/m and length L=10 /spl mu/m, are investigated. An analytical model predicting the post-stress performance is presented, by treating the channel of the stressed device as a series combination of a damaged region extended over a length /spl Delta/L beside the drain and a region of length L-/spl Delta/L having the properties of the unstressed device. The apparent channel mobility is derived considering that the mobility of the damaged region is described with the mobility of amorphous Si TFTs, whereas the mobility of the undamaged region is described with the mobility of the virgin device. From the evolution of the static characteristics during stress, the properties of the damaged region with stress time are investigated.

Experimental investigation of the substrate current Isub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, Isub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, Isub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.

The low-frequency noise in offset-gated polysilicon thin-film transistors (TFTs) is investigated. It is shown that the spectral density of the drain current fluctuations can be interpreted in terms of the carrier number fluctuations, considering the extrinsic transconductance of the device. The relation between the extrinsic transconductance of the offset-gated polysilicon TFT and the intrinsic transconductance of the self-aligned device was found to depend mainly on the polysilicon layer quality. An effective density of traps N/sub teff//sup */ was extracted which reflects the contribution to the noise of the active and passive channel. The extracted noise index N/sub teff//sup */ is lower when the polysilicon layer quality is improved (lower in-grain defect density).

A simple method to determine the Interface and bulk density of states in polycrystalline silicon thin-film transistors is presented. The energy distribution of the interface trap density has been extracted from analysis of the transfer characteristics in the subthreshold region of operation. Using the obtained interface state distribution, the energy distribution of the bulk traps has been determined by fitting the surface potential at each gate voltage with an analytical theoretical model. Both interface and bulk traps were found to consist of deep states with constant density near the mid-gap and band-tails with density increasing exponentially with the energy when the trap energy approaches the conduction band-edge.

The effects of hydrogenation on the performance and stability under electrical stress of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated. The hydrogenation is performed in pure H 2 plasma or in plasma of 4% H 2 diluted in He gas. Devices hydrogenated in plasma of H 2 /He exhibit lower subthreshold swing with better uniformity and lower leakage current, which indicate passivation of mid-gap trap states arising from dangling bonds at the grain boundaries. Hot-carrier experiments demonstrate that the stability of p-channel TFTs is improved as the hydrogenation becomes more efficient due to the effective removal of donor-type trap states at the grain boundaries.

The stability of p-channel polycrystalline silicon thin-film transistors, hydrogenated in pure hydrogen plasma, is investigated. The hot-carrier induced degradation mechanisms are studied for operation in the saturation region and different gate bias voltages V g . During on-state stress at high | V g |, first an effective shortening of the channel length is observed due to trapping of hot electrons. As the stress proceeds further, donor-type interface states are generated, resulting in an increase of the electric field near the drain due to built-up of positive charge in these states by trapping of hot holes. During on-state stress at low | V g |, the transistor parameters are improved due to further passivation of grain boundary deep and tail states, caused by dissociation of hydrogen molecules by hot electrons near the drain region. During off-state stress, hot electrons are injected in the gate oxide near the drain causing an effective shortening of the channel length and a reduction of the minimum leakage current.

The effects of gamma-ray irradiation on the performance of polycrystalline silicon thin-film transistors are investigated. After irradiation, the threshold voltage of the TFTs is shifted negatively and well-defined kinks are formed in the subthreshold regions of the transfer characteristics, explained by the turn-on of back channel and sidewall leakage current paths. In the non-irradiated device, the leakage current I L is controlled by the reverse biased drain junction, while after irradiation I L is limited by the intrinsic resistance of the polysilicon material itself.

The effect of the SiO2/polycrystalline silicon (polysilicon) interface roughness on the stability of n-channel large grain polysilicon thin-film transistors (TFTs) is investigated. The positive gate voltage of 20 V is used in the bias stress experiments, with the source and drain grounded. It is shown that the current through the gate oxide and the stability of the TFT are directly related to the importance of the interface roughness. The evolution of the TFT parameters with stress duration indicates that the turn-on voltage Von and the subthreshold swing voltage S are degraded due to the generation of dangling bond midgap states, while the leakage current IL and the maximum transconductance Gm are degraded due to the generation of strain-bond tail states. Moreover, the parameters Von and IL are found to degrade faster than the parameters S and Gm, respectively, due to electron trapping in the gate oxide.

The effects of low gate voltage |V/sub g/| stress (V/sub g/=-2.5 V, V/sub d/=-12 V) and high gate voltage |V/sub g/| stress (V/sub g/=V/sub d/=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V/sub g/| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V/sub g/| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds.

Large-grain excimer laser-annealed polysilicon TFTs are studied. Due to the large grain size of the polysilicon film (about 2.5 /spl mu/m), we propose a model for the on-current (above threshold voltage) taking into account the number of grain boundaries within the channel. This linear-region model considers grain and grain boundaries as two noncorrelated regions within the channel of a polysilicon TFT. The trap density at the grain boundaries and the device parameters involved in this model are determined by fitting the experimental transfer characteristic in the linear regime. Moreover, we show that the proposed model provides reliable results within a temperature range from 150 K to 300 K. Finally, it serves to optimize the energy density of laser annealing and to make predictions about polysilicon TFT technology, since TFTs performances versus grain size plots can be obtained.

The leakage current I L of offset gate n- and p-channel excimer laser annealed polycrystalline silicon thin-film transistors (polysilicon TFTs) has been investigated experimentally. It has been found that the leakage current is almost independent of the polysilicon layer quality. In n-type polysilicon TFTs, I L arises from band-to-band tunneling due to extension of the drain junction to the gate end by diffusion of phosphorus ions from the drain contact within the offset region. In p-channel TFTs, I L first increases rapidly and then saturates at high drain voltages. This leakage current behavior is explained qualitatively by a model based on the change of the effective offset length, caused by the applied drain voltage on the positive ions of boron, diffused from the drain contact within the offset region.

Hot-carrier effects have been investigated in n-channel thin-film transistors fabricated on large grain polysilicon films. The bias-stress conditions for maximum device degradation have been determined by photon emission measurements. Under these bias-stress conditions, devices with identical transfer characteristics before stress, are either stable or exhibit strong degradation with reduced field effect mobility. We propose that the different degradation behavior is related with the quality of the grain boundaries and their position in the channel with respect to the drain junction. The results indicate that when a grain boundary is located closer to the drain region, it becomes more prone to degradation by the hot carriers generated in the high field region of the drain junction. Numerical simulations suggest that the device degradation is due to an increase of the grain boundary band tail states. In addition to this mechanism, the existence of a critical path for the current flow from source to drain has been proposed to explain the observed different degradation behavior of similar devices.

The influence of the material quality and thickness on the leakage current of polycrystalline silicon thin-film transistors is investigated. Improvement of the polycrystalline silicon layer (i.e., increase of the average grain size or decrease of the intragrain defect density) reduces only the leakage current at low electric fields in the drain region. At high electric fields, the leakage current is independent of the film quality and thickness due to the fundamental nature of the leakage current mechanisms. The experimental data indicate that Poole–Frenkel enhanced emission from traps at low electric fields and band-to-band tunneling at high electric fields are the dominant conduction mechanisms of the leakage current.

Gd and GdCo layers were evaporated onto n-type silicon and silicides were formed by in situ annealing at 400 and 700 °C. The electrical properties of the resulting Schottky diodes were investigated by current-voltage, capacitance-voltage and low frequency noise measurements. The Gd/Si contacts show an ohmic behaviour for both annealing temperatures, while the GdCo/Si contacts show a rectifying behaviour with a high (~0.65 eV) and a low (~0.52 eV) Schottky barrier height for the annealing temperatures of 400 and 700 °C, respectively. It was found that Co retards the Gd-Si reaction and reduces the density of the donor-type point defects generated within the silicon substrate during the Gd silicidation process.

An analytical model of the above-threshold voltage transconductance of large grain polycrystalline silicon thin-film transistors (TFTs) is presented. The devices were fabricated on 50 nm thick polysilicon films prepared by combined solid phase crystallization (SPC) of amorphous silicon and excimer laser annealing (ELA) at various energy densities. The structural properties of the polysilicon films were investigated by transmission electron microscopy. The transconductance model includes exponential band tails for the grain boundary traps, the eAect of polysilicon/SiO2 interface scattering and the channel depth variation with gate voltage. Based on this model, the transconductance dependence on gate bias is investigated in devices with diAerent interface roughness. It is found that at low gate voltages, the transconductance increases with the gate bias due to the grain boundary barrier lowering eAect. The observed decrease of the transconductance at high gate biases is mainly related to the size of the interface roughness. ” 2000 Elsevier Science Ltd. All rights reserved.

Thin-film transistors (TFTs), fabricated on solid-phase-crystallized polycrystalline silicon (polysilicon) films subjected to laser annealing, were studied. For the resulting large-grain polysilicon TFTs, a model is proposed that takes into account two well-distinguished regions within the channel of the transistor: the intra-grain region and the grain boundaries. By using this model, we found that the extracted on-voltage is mainly grain-boundary dependent while the maximum transconductance is mostly intra-grain defect dependent. Moreover, with the aid of this model, the physics of the large-grain polysilicon TFTs becomes more evident and an optimal laser energy density was found for best device performance.

Experimental results of low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) with varying gate dimensions (constant gate width W and varying gate length L) are presented. The power spectral density of the drain current fluctuations SI was found to depend linearly on the inverse of the effective gate area Ag,eff which is related to the gate area W×L and the number of grains present within the transistor channel. This result implies localization of the low frequency noise sources on the gate oxide-polysilicon interface and on the grain boundaries. The 1/Ag,eff scaling law must be taken into account for correct estimation of trap densities in polysilicon TFTs.

The structural and electrical properties of excimer laser annealed polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated in relation to the laser energy density. The devices were fabricated on 50 nm thick polysilicon films prepared by excimer laser crystallization (ELA) of amorphous silicon or by a combined solid phase crystallization (SPC) and ELA process. The structural properties of the polysilicon films have been investigated by transmission electron microscopy analysis. The effective density of states distributions in the polysilicon films and in the oxide traps near the oxide/polysilicon interface have been determined from low frequency noise measurements. The TFT performance parameters are compared with respect to their correlation with the structural properties of the polysilicon films and their electrically active defects, the basic variables being the starting material (amorphous silicon or SPC polysilicon) and the laser energy density.

The structural and trap properties of polycrystalline -FeSi2 thin films, grown by rapid thermal or conventional furnace annealing on (100) Si substrates of high resistivity, were investigated by transmission electron microscopy and low-frequency noise measurements performed at room temperature with the current I as a parameter. The power spectral density of the current fluctuations shows a 1/f´ (with >1) behaviour and is proportional to I (with

A study on hot-carrier phenomena in high temperature processed undoped and hydrogenated n-channel polysilicon thin film transistors (TFTs) is presented. First, stress conditions are determined by photon emission measurements during impact ionization condition. Next four stress regimes are performed. We distinguish two modes of stress conditions according to drain voltage during stressing: High drain voltage stress (HDVS) and low drain voltage stress (LDVS). Each of these modes gives different results when applied to our TFTs. During HDVS condition, two regimes are observed. First, hot-hole injection into the oxide occurs synchronically with interface-state generation. At a second stage, this mechanism saturates and electron injection through the polySi–SiO2 barrier takes place with less interface states generated. In contrast, during LDVS conditions no saturation of interface-state generation is observed and two regimes of transconductance degradation appear. The distribution in the gap of the stress-induced interface states is calculated by a known method. Finally, on- and off-state current stress was studied. Off-stressing affects mainly the gate oxide and is not accompanied by measurable impact ionization phenomena and thus no considerable interface-state generation.

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.

Polycrystalline silicon thin-film transistor (polysilicon TFT's) characteristics are evaluated by using a low-frequency noise technique. The drain current fluctuation caused by trapping and detrapping processes at the grain boundary traps is measured as the current spectral density. Therefore, the properties of the grain boundary traps can be directly evaluated by this technique. The experimental data show a transition from 1/f behavior to a Lorentzian noise. The 1/f noise is explained with an existing model developed for monocrystalline silicon based on fluctuations of the inversion charge near the silicon-oxide interface. The Lorentzian spectrum is explained by fluctuations of the grain boundary interface charge with a model based on a Gaussian distribution of the potential barriers over the grain boundary plane. Quantitative analysis of the 1/f noise and the Lorentzian noise yield the oxide trap density and the energy distribution of the grain boundary traps within the forbidden gap.

Low-frequency noise measurements have been carried out at room temperature in polycrystalline semiconducting iron disilicide (β-FeSi2) thin film with the current I as a parameter. The power spectral density of the current fluctuations exhibits a 1/f behavior at low frequencies (f

The deposition temperature dependence of the characteristics of TiNx/n-Si Schottky diodes fabricated via reactive magnetron sputtering, is studied through the current-voltage characterization and the low frequency excess noise measurements. As the deposition temperature was varied from room temperature up to 400 degrees C, both the ideality factor of the diode and the power spectral density of the noise current decreased. The analysis of the low frequency noise shows that the noise due to the trapping and detrapping at the interface due to the random walk of electrons via the modulation of the barrier height dominates the noise due to the mobility fluctuation, except at very low current levels, in these non-ideal diodes. It is found that the interface states density could be reduced by almost an order of magnitude by raising the deposition temperature up to 400 degrees C from room temperature. (C) 1999 Elsevier Science B.V. All rights reserved. Applied Surface Science

The accurate knowledge of the effective channel length in a polysilicon thin film transistor (TFT) is of great importance. The reduction ΔL of the channel length is due to lateral diffusion from the source and drain contacts into the gate region. The usual method for determining ΔL is based on plotting the straight line 1/ID versus length mask Lm in the linear region and extrapolating the straight line to intersect the x-axis. We show that this method is approximate and leads to an underestimation of the reduction channel length due to the existence of the access resistance. We propose an alternative method based on the saturation current IDsat using the 1/IDsat versus Lm plots. We show that this method is more accurate especially when the access resistance of the device is important. The extracted parameters ΔL for n- and p-channel polysilicon TFTs are more compatible with the device performance.

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V on) and on-state current (I on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V on is observed, attributed to electron injection into the gate dielectric, followed by I on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.

The electrical characteristics and the low frequency noise of Schottky contacts on n-type Si(100) have been systematically measured. The thin films were deposited by reactive magnetron sputtering at room temperature. Based on a model of a parallel combination of an ideal diode of current and a generation-recombination diode of current , we have extracted the contribution of both diodes to the measured total current I. Treating the two components and as different noise generators, we have analysed the observed white noise at high frequencies and the excess current noise at lower frequencies. The white noise is explained by using a pure shot noise for the component , by applying Gupta's general theorem on noise in non-linear driven devices for the component and by considering an additional noise generator with a Nyquist-type intensity. The excess current noise is explained by a model based on fluctuations of the generation-recombination current only. Analysis of the versus I data allowed us to determine the interface state density.

The performance of n- and p-channel high-temperature processed polycrystalline silicon thin-film transistors (polysilicon TFTs) has been investigated by conduction and low-frequency noise measurements. The polysilicon films were doped by boron or phosphorus ion implantation at concentrations of about 6×1016 and 3×1017 cm−3, respectively, and hydrogenated by ion implantation of hydrogen. Undoped and nonhydrogenated polysilicon films were also used for comparison. Channel length reduction due to dopant diffusion from the source and drain contacts was found to affect the transistor conduction and its associated noise. Low-frequency noise measurements indicate that the noise power spectral density of the drain current is mainly due to carrier number with correlated mobility fluctuation. The experimental data reveal the presence of exponential band tails in both n- and p-channel hydrogenated undoped polysilicon TFTs. In nonhydrogenated boron doped n-channel devices, high density of band tails and deep levels a...

The off-state current in n- and p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) is investigated systematically by conduction measurements at various temperatures and low-frequency noise measurements at room temperature. It is demonstrated that the leakage current is controlled by the reverse biased drain junction. The main conduction mechanisms are due to thermal generation at low electric fields and Poole–Frenkel accompanied by thermionic filed emission at high electric fields. The leakage current is correlated with the traps present in the polysilicon bulk and at the gate oxide/polysilicon interface which are estimated from the on-state current activation energy data. Analysis of the leakage current noise spectral density confirms that deep levels with uniform energy distribution in the silicon band gap are the main factors in determining the leakage current. The density of deep levels determined from noise analysis is in agreement with the value obtained from conductance acti...

Shallow p+/n junctions are produced by low energy Boron or Boron Fluorine implantation into n-type silicon preamorphised substrate. Preamorphisation step was obtained by high dose Ge+ ions implantation at various energies ranging between 30 to 150 keV. The electrical characteristics of the diodes (reverse current density and noise spectral density) are shown to be strongly dependent on the preamorphisation Ge+ ions implantation energy. Combining electrical analysis with transmission electron microscopy allowed us to correlate the diode behaviour with the extended defects distribution induced by the regrowth of the amorphous layers. We report that these defects, usually named End-Of-Range, strongly affect the electrical performance when located within or close to the space charge region.

An improved analysis of the low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) is presented. The analysis takes into account an exponential energy distribution for the density of states and the flat-band voltage fluctuations for the origin of the drain current noise. Analysis of the drain current spectral density enables the characterization of the gate oxide/polysilicon interface and the active polysilicon layer quality.

The recombination lifetime and diffusion length of intentionally iron-contaminated samples were measured by the Surface Photo Voltage (SPV) and the Elymat technique. The lifetime results from these techniques for intentionally iron-contaminated samples were analysed, in particular for the aspect of the injection-level dependency of recombination lifetime. Based on theoretical considerations, a method for the analysis of deep-level parameters combining constant photon flux SPV and Elymat measurements has been developed. This method is based on a detailed numerical analysis of the Elymat technique, including the Dember electric field, the characteristics of the laser beam, the transport parameters of the semiconductor and multilevel Shockley-Read-Hall (SRH) recombination kinetics. The results of the numerical simulation are applied to the analysis of recombination lifetime measurements on intentionally iron-contaminated samples. We compared numerical simulations and experimental results from SPV and Elymat for p-type samples using the classical acceptor level atEv +0.1 eV and the donor level of FeB pairs atEc -0.3 eV as recombination centre. Better consistency in the interpretation of the results has been found in the doping range 1014–1016 cm−3 supposing theEc -0.3 eV level as predominant recombination centre. An attempt to extract the electron and hole capture cross-sections for this defect is made.

By the year 2000 electronics will probably be the basis of the largest industry in the world. Silicon microelectronics will continue to keep a dominant place covering 99% of the `semiconductor market'. The aim of this review article is to indicate for the next decade the domains in which research work in `physics' is needed for a technological advance towards increasing speed, complexity and density of silicon ultra large scale integration (ULSI) integrated circuits (ICs). By `physics' we mean here not only condensed matter physics but also the basic physical chemistry and thermodynamics. The review begins with a brief and general introduction in which we elucidate the current state of the art and the trends in silicon microelectronics. Afterwards we examine the involvement of physics in silicon microelectronics in the two main sections. The first section concerns the processes of fabrication of ICs: lithography, oxidation, diffusion, chemical and physical vapour deposition, rapid thermal processing, etching, interconnections, ultra-clean processing and microcontamination. The second section concerns the electrical operation of the ULSI devices. It defines the integration scales and points out the importance of the intermediate scale of integration which is the scale of the next generation of ICs. The emergence of cryomicroelectronics is also reviewed and an extended paragraph is dedicated to the problem of reliability and ageing of devices and ICs: hot carrier degradation, interdevice coupling and noise are considered. It is shown, during our analysis, that the next generation of silicon ICs needs mainly: (i) `scientific' fabrication and (ii) microscopic modelling and simulation of the electrical characteristics of the scaled down devices. To attain the above objectives a return to the `first principles' of physics as well as a recourse to nonlinear and non-equilibrium thermodynamics are mandatory. In the references we list numerous review papers and references of specialized colloquia proceedings so that a more detailed survey of the subject is possible for the reader.

Low-frequency noise measurements have been carried out in polycrystalline silicon thin-film transistors (polysilicon TFTs) with different interface roughnesses. Independently of the interface roughness, the drain current noise can be ascribed to carrier number fluctuations. In devices with a large interface roughness, a noise overshoot is observed at drain currents around 3μA, attributed to generation-recombination (g-r) centers. The traps responsible for the g-r noise are located within the gate oxide near the interface, created by the carriers injected into the gate oxide by the field enhanced at the rough polysilicon∕SiO2 interface. The g-r noise corresponds to a single trap level of density 3.8×1017cm−3 and time constant 20ms. Devices exhibiting g-r noise degrade more rapidly during electrical stress.

Results on the impact of hot-carrier effects on the transfer and low-frequency noise characteristics of n-channel poly-crystalline silicon thin-film transistors (polysilicon TFTs) are presented. After stressing at the condition of maximum substrate current, the experimental data show that TFTs suffer from substantial on-current reduction. Through numerical simulation, it is shown that the stress-induced degradation increases the density of the band tail traps in a region extending 200 nm from the drain and the series resistance on the drain side. It is found that the origin of the noise is reverted from carrier number fluctuation for the unstressed to the mobility fluctuation for the stressed device.

Hot-carrier effects in offset gated n-channel polycrystalline silicon thin-film transistors of channel length L=10 μm and intrinsic offset lengths ΔL=0.5 and 1 μm are investigated. The gate- and drain-bias conditions for maximum device degradation were determined from substrate current measurements. The experimental data show that hot-carrier stress provokes an anomalous threshold voltage and on-state current degradation, exhibiting a “staircase-like” degradation with stress time. These results lead to the conclusion that, at the initial stages of stress, a small offset region from the drain end is damaged due to charging of the grain boundaries. As the stress proceeds further and the grain boundary traps are filled with electrons generated by impact ionization, the damage is transferred to the neighboring offset region, resulting in a staircase-like degradation of the device parameters with stress time.

Application of the on-line Elymat technique for measuring bulk carrier recombination lifetime is numerically analysed using a complete three-dimensional carrier transport simulation including the Dember electric field, the characteristics of the laser beam, the transport parameters of the wafer and Shockley-Read-Hall recombination kinetics. We found a strong dependency of the measured lifetime on the shape and power of the laser beam as well as on the deep energy level of the impurity in the gap, owing to nonlinear effects not described by the classical model. Our numerical simulations show that the use of a small laser beam permitting the approximation of point-like excitation gives the most reliable results. The comparison between our numerical simulations and experimental results for iron-contaminated p-type samples with a resistivity between 1 and 18 Omega cm shows that the donor level of Fe-B pairs at Ec-0.3 eV and not the classical acceptor level at Ev+0.1 eV is the predominant site of recombination of Fe-B pairs in p-type silicon in the above doping range. First results for the electron and hole capture cross sections for this defect will be given. Based on these results, the sensitivity of the technique is shown to be less than 1011cm-3 in the case of Fe-B pairs corresponding to less than 10 PPT (parts per trillion).

Low-frequency noise measurements have been carried out in platinum silicide Schottky diodes on n-type silicon in the forward conduction regime and with the forward current IF as a parameter. The power spectral density of the current fluctuations shows a 1/f behavior and is proportional to IFβ (with 1

A model for the low frequency noise of polycrystalline silicon thin film transistors (polysilicon TFTs) is proposed. The model takes into account fluctuations of the grain boundary potential barrier induced by those of the grain boundary interface charge and fluctuations of carriers due to trapping in oxide traps located close to the interface. Using the proposed model, it is demonstrated that both grain boundary and oxide traps can be determined in polysilicon TFTs from noise measurements.