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A characterization approach has been developed for evaluating stochastic printing failures in EUV contact holes. Demand for consistent yield exceeding 10 billion contacts requires robust process co-optimization with a focus on stochastic defect reduction throughout the patterning process flow. To monitor and quantify failure rates across process points, implementation of a holistic approach for accurate and high-throughput methodologies is proposed.

As the complexity of both design and processing increase for advanced FinFET technology, defect metrology will continue to provide the best strategies for Defect Review Scanning Electron Microscopy (DR-SEM) and Automatic Defect Classification (ADC). The precise defect location navigation, and the accuracy of random and systematic defect classification can be improved by introducing Computer-Aided Design (CAD) into DR-SEM and ADC processes. The Design Based ADC (DBA) not only differentiates systematic and random defect on CAD for yield control but also determines the precise defect locations for weak point analysis. We will present a method for the implementation of weak point CAD for DR-SEM review and ADC through a case study of a BEOL CMP layer of an advanced FinFET process demonstrating its benefit to defect analysis and control.

Photomask issues can result in shifted pattern defects printed on the wafer. In the case of sub-1x nm nodes, these pattern defects of interest (DOI) can be difficult for conventional optical inspections to detect. In this paper we present a case study of a new mask qualification for a MOL gate open (GO) contact mask layer. The new mask was introduced to compensate for a known open between trench silicide (TS) contact and GO. During qualification, a shift in the GO overlay was seen on one section of the wafer and suspected to be the cause of a TS-gate short. A Design of Experiments (DOE) was created to investigate if the issue was solely mask related or if it could be mitigated during processing (litho/etch). Physical mode e-beam inspection was used to monitor the DOE wafers, however the resolution of the e-beam inspection tool was not sufficient to conclusively classify the defects observed. A high resolution, high landing energy SEM defect review was introduced post e-beam inspection to better monitor the splits running as part of the DOE.

Defect metrology for advanced FinFET devices faces a variety of challenges in terms of accurate classification of Defect Review Scanning Electron Microscopy (DR-SEM) images. As the Defect of Interest (DOI) size shrinks in proportion to the printed feature dimension, it is critical that these platforms adjust to continue to provide the best possible defect classification. This can be achieved most efficiently by introducing Computer-Aided Design (CAD) information into these platforms. In order to improve imaging of defects in DR-SEM, CAD data is used to enhance the alignment step, providing more accurate navigation to defects and allowing the magnification to scale according to the smaller defect size. We present a streamlined method to introduce this CAD based alignment step into the existing recipe management system on the DR-SEM platform. While decreasing image FOV is beneficial, the introduction of CAD information into Automatic Defect Classification (ADC) can provide valuable information on the defect’s location. Design Based ADC (DBA) achieves this by providing the means to differentiate the defect’s impact on device performance based on CAD data such as mask or process step. We present two case studies of DBA on multi- patterning and epi layers in the sub-1x FinFET process.

As the semiconductor industry moves to sub 1× nm nodes, with complex 3D structures, high aspect ratio (HAR) features and multiple patterning steps, the ability to detect and characterize defects is becoming increasingly difficult. Defects, located at the bottom of HAR structures or buried in the previous layers, are making the devices vulnerable to failure. It is critical to characterize these defects to understand the failure mechanism, to qualify a new process and for accurate yield prediction. For failure analysis, the defect locations on the wafer are marked and sent for Transmission Electron Microscopy (TEM) imaging, leading to high cycle times, with limitation on number of locations on the wafer. In this paper, we present results from novel backscattered electron (BSE) detection, where inline Scanning Electron Microscopy (SEM) images can provide vital information regarding the failure mechanism in much shorter cycle times, with no limitations on number of locations.

As the semiconductor industry continues to advance to smaller and smaller nodes, Defect Review Scanning Electron Microscopy (DR-SEM) and ADC (Automatic Defect Classification) face increasingly difficult challenges. The Defects of Interest (DOI) shrink as the features shrink, leading to imaging difficulty purely based on scale. Also, more complex defect analysis is required for DOI's formed during multiple patterning steps or DOI's created in previous steps. A smart approach to ADC must be adopted which allows for high quality defect classification focused on root cause analysis and yield prediction in short cycle times. In this paper, we present results from novel approach: Design Based ADC (DBA). Here, design information with current DR-SEM and ADC platforms is combined, leading to superior and robust classification.

As the scaling continues and industry moves to sub 1× nm nodes, Defect Review Scanning Electron Microscopy (DR-SEM) faces increasingly difficult challenges. The Defects of Interest (DOI) shrink as the features shrinks leading to imaging difficulty purely based on scale. The defect signal gets immersed in noise and the challenge of separating false from true is larger than ever. Also, more complex defect analysis is required for DOIs with 3D morphology and for previous layer DOI. A smart approach to DR-SEM must be adopted which allows for high quality imaging focused on yield improvements within a short cycle time. In this paper we demonstrate that reporting defects location in computer aided design (CAD) coordinates eliminates tool and user discrepancy in the inspection/review loop, facilitating robust DOI search at higher magnification and sensitivity. Further, smart implementation of defect analysis such as high landing energy see-through imaging, quantitative material analysis and tilt imaging on select DOI subsets allows for root-cause analysis and improved classification of defects which were previously misclassified or determined to be SNV (SEM non-visual).