Search

We investigated the effect of channel hot carrier (CHC) stressing on the creation of gate oxide defect centers causing random telegraph signals (RTSs) in pMOSFETs. To identify these stress-induced hole traps in the oxide and fully characterize their trapping properties, variable temperature RTS measurements were performed from room temperature down to 215 K and repeated after each stressing interval, up to 1200 s. The trapping properties of the stress-induced defect sites and those present before stress are quantified, including the hole capture and emission activation energies, structural relaxation in the oxide network due to trapping/detrapping, and entropy change as well as the energy level and position of the trap in the oxide. Based on this information, disassociated III-Si and hydrogen bridge defects are identified as the hole trapping centers in SiO2. Difference was observed between the process- and stress-induced traps in the entropy change upon hole emission from the oxide trap to Si channel (electron capture from the Si valence band), implying the possibility of stress-induced structural defects being different than the native ones.

We report on the investigation of random telegraph signals (RTSs) in pMOSFETs at variable temperatures to identify and characterize the hole traps residing at the oxide–semiconductor interface. Attractive center defects as well as a repulsive center defect are identified with trap location, capture cross section, remote Coulomb scattering coefficient, capture barrier energy, trap binding enthalpy, relaxation energy, and change in entropy with hole emission. The attractive centers responsible for RTS were a pair of dissociated three-coordinated silicon (D-III-Si) defects while the repulsive center was identified as a puckered/back-projected oxygen vacancy defect, [a pair of under-coordinated silicon (III-Si) and over-coordinated oxygen (III-O) defects]. Both contain ${E}\gamma ^{\prime }$ centers. This is the first time when such detailed analysis is reported on the hole traps in SiO2 which are responsible for RTS.

Investigating random telegraph signals (RTS) observed in MOS devices is important for studying the gate-oxide defect characteristics and developing simulation and modeling tools in highly scaled devices. In this paper, we are presenting a comprehensive, variable-temperature, single-to-multitrap scalable RTS model and a simulation tool (RTSSIM) based on the first principles, and supported by experimental data. The physical and electrical characteristics of the actual oxide defects are considered, such as trapping barrier energy, capture cross section, trap-binding enthalpy, entropy change with emission, Coulombic scattering effect, and the trap location. Experimentally obtained time-domain switching data and RTS traces reconstructed by the developed simulation tool are compared for assessing the accuracy of the modeling. In this paper, we identified the trap species responsible for the RTS as an unrelaxed neutral oxygen deficiency center ( $V^{0}$ ODC II) with measured and theoretically verified relaxation energy of 1.11, 1.25, and 0.60 eV. RTSSIM is a tool used to mimic or reproduce a given noise measurement on a particular device. The simulation tool shows over 92% accuracy in replicating the RTS and trap characteristics. The model also represents the first realistic simulation of multilevel RTS.

A physics-based model has been implemented to describe the low-frequency noise behavior in differently processed reduced-surface-field lateral double-diffused MOS devices. The developed model is based upon the correlated carrier number and the mobility fluctuation theory known as the unified model but has been modified to account for the fluctuations in the extended drain and the channel. Unlike the unified 1/f noise model, nonuniform trap distribution has been taken into account with respect to position in the gate oxide and band-gap energy. The effect of stress on dc and noise characteristics has been investigated. Individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides are evaluated as a function of stress duration. The model is experimentally verified to identify the physical mechanisms for degradation due to stressing.

Carrier trapping via tunneling into the gate oxide was implemented into a partial differential equation-based semiconductor device simulator to analyze the 1/f-like noise in silicon MOSFETs. Local noise sources are calculated using the carrier tunneling rates between trap centers in the oxide and those at the interface. Using the Green's transfer function approach, noise contributions from each node in the oxide mesh to the overall noise at the specified contact terminals are simulated. Unlike traditional 1/f noise analyses in MOSFETs, the simulator is capable of simulating noise for a wide range of bias voltages and device structures. The simulation results show that for an uniformly doped channel, the region in the oxide above the pinch-off point in saturation is most critical for low frequency noise generation while for a graded channel device the source side of the gate oxide region becomes important. By comparing the simulation results with the measured noise data, the oxide defect density in the noise producing regions can be profiled.

We report a device physics theory and compact model that predicts the threshold voltage mismatch for CMOS transistors using the halo implant. This model is able to fit CMOS VT mismatch across temperature and device geometry, validating the underlying physical argument. A bias method is presented and shown to recover part of the matching degradation due to the halo implant.

The implementation of generation–recombination (g–r) noise in a partial differential equation based device simulator is presented. Derived from the Shockley–Read–Hall model, the strength of each local g–r noise source is calculated based on the carrier transition rates between the conduction band, valence band, and trap states. The perturbations of these local g–r noise sources are then transmitted to the electrodes of the simulated device through scalar Green’s functions. g–r noise simulations are compared with existing measurements made on a four trap level, p-type silicon resistor. Good agreement between measured and simulated data is observed.

Unrelaxed neutral oxygen deficiency centres (ODCs) (V0 ODC II) in SiO2 have been identified as the cause of random telegraph signals (RTSs) in highly scaled n-type metal–oxide–semiconductor field-effect transistors. Variable temperature RTS measurements were performed to extract trap capture cross-sections, capture activation energy, relaxation energy associated with the gate oxide defects, and the trap energy in the SiO2 bandgap to determine the trap species and type. The results indicate that the electron is captured by a neutral ODC that is transformed into a negatively charged vacancy (V−). This is the first time V0 ODC II centre is confirmed to be the source of electron switching through RTS measurements defining four different trap characteristics.

The low-frequency 1/f-like noise of gated n/sup +/-p silicon diodes has been measured and analyzed in terms of trapping and detrapping of holes in defect centers located in the bulk section of the space charge region at 0.43 eV below the conduction band. Both the trap characteristics and their precise physical location are resolved from the noise measurements showing that the noise producing defect region moves closer to the metallurgical junction when forward bias is increased. The noise measurements independently confirm that thermal substrate pretreatments lower the defect density in the diodes fabricated in Czochralski (CZ) grown substrates. The defect centers are assumed to be associated with precipitated oxygen/dislocation complexes.

Random telegraph signals (RTS) are investigated on MOSFETs where a systematic procedure is developed to extract the RTS parameters from a large volume of multi-level switching events with a Poisson distribution. RTS measurements can be utilized to identify and characterize gate oxide defects with better resolution than frequency domain power spectral density, deep level transient spectroscopy, or charge pumping techniques. We demonstrate here multi-level RTS method to investigate gate dielectric trap characteristics including type (acceptor or donor), position of the traps from the of Si/SiO2 interface in the oxide, and along the channel, using the effect of gate bias on the mean carrier capture and emission times, and the number of active traps.

A review is presented for the physics-based flicker noise model developed to describe the origin of low-frequency fluctuations in LDMOS transistors. The model is based on the Unified 1/f Noise Model, but it considers a more realistic spatial and energy distribution of traps in the dielectric instead of uniform trap distribution. It not only correctly computes the observed noise power spectral density in LDMOS, but it successfully predicts the degradation of noise characteristics with applied high voltage stress. We verified the model for two different technology samples that were fabricated in standard BiCMOS processes. This paper focuses on the analysis and modeling approach for the viability of the correlated carrier number and mobility fluctuation based 1/f noise model for LDMOSFETs. Observations from some recent approaches on LDMOS noise modeling are also highlighted here.

Testing and characterization are fundamental tasks in any semiconductor manufacturing or circuit development activity. These activities call for flexible, yet efficient tools that allow for automated execution. This paper describes the development of an independent Testing Development Environment (TDE) as a platform for designing testing and characterization procedures for use in a production line setting. The proposed platform supports DC, parametric, and noise measurement capabilities in a modular, designer customizable library of testing functions. The platform structure, customization protocols, and I/O formats are discussed, along with the process of populating its function library with procedures for evaluating passive and active devices with diverse requirements and formats. Over four dozen testing procedures have been added to the tool. User-level interactions are used to illustrate the easiness of use and flexibility of this platform.

Generation-recombination noise associated with bulk defect levels in silicon is modeled in a partial differential equation-based device simulator to study the maximum allowable defect density that guarantees generation-recombination (g-r) noise-free operation in the presence of hot-carrier effects and space-charge injection.

We report a device physics theory and compact model that predicts the threshold voltage mismatch for CMOS transistors using the halo implant. This model is able to fit CMOS VT mismatch across temperature and device geometry, validating the underlying physical argument. Layout and biasing methods are presented and shown to recover part of the matching degradation due to the halo implant.

Trap assisted generation-recombination noise spectra of advanced n-channel MOSFETs are numerically simulated using the drift-diffusion transport model and focusing on the bimolecular electron transitions between the channel and gate oxide. Good agreement between measured and simulated data is observed in both the linear and saturated regime of operation under sub-threshold and inversion conditions. Reverse engineering of the measured noise data reveals the discrete trap distributions in the oxide responsible for the observed spectra.

The development of a numerical, postprocessor, device noise simulator, capable of simulating velocity fluctuation and Hooge type 1/f noise is described. Three-dimensional noise maps are presented for a bipolar transistor and MOSFET revealing the noise contributions of specific device areas. Where applicable, good agreement with analytical results is obtained.