Search

International audience; A B S T R A C THeterojunction Bipolar Transistors needed for high-frequency applications require precise dopant control. Insitu doped epitaxies used during device fabrication rely on surface preparation to obtain an optimized dopingprofile. Defects due to imperfect cleaning relates to high emitter resistance and low-frequency noise.Base epitaxy is followed by the fabrication of thin L-shaped oxide spacers and in-situ arsenic-doped emitterepitaxy by Low Pressure Chemical Vapor Deposition. A cleaning step between spacers formation and emitterepitaxy is mandatory to remove residual contamination. Hydrofluoric acid (HF) wet cleaning, in-situ remoteplasma cleaning (SiconiTM) and thermal treatments have been tested. A minimum etching budget is sought forlimiting spacer consumption while adequately cleaning the interface.Time Of Flight-Secondary Ion Mass Spectroscopy (TOF-SIMS) and High-Resolution Transmission ElectronMicroscopy (HR-TEM) are used to characterize the interface and measure levels of arsenic, oxygen, fluorineand carbon. Emitter resistance and base-emitter breakdown voltage measurements are used to show the impacton electrical figures of merit. Siconi targeting 10 Å of thermal oxide removal followed by a thermal treatment(800 ◦C, 60 s) in the deposition chamber results the best process among the tested ones.

3D sequential integration, such as CoolCubeź, allows to stack vertically layer of devices. Levels of interconnection, also called intermediate Back-End-Of-Line, are needed between successive layers of transistors to avoid routing congestion. Thus, thermal stability of the dielectrics must be studied in order to fulfil the CoolCubeź requirement: at least to be stable up to 500°C during 2h. Consequently, the stability of several barrier layers and oxide based materials has been studied through optical characterizations (ellipsometry, Fourier Transform InfraRed spectroscopy and ellipsometric-porosimetry). SiCO (k=4.5), in replacement of standard SiCNH (k=5.6) material as barrier layer seems very promising. Regarding the inter-layer dielectric stability, the state-of-the-art porous SiOCH (k=2.5) stays suitable for a thermal budget of 500°C, 2h. Display Omitted

3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self-aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre-treatments have been carried out. Indeed, a novel Ni-based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si-Cap) and Si0.7Ge0.3:B S&D pre-amorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si-Cap. Moreover, the presence of Si-Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

In this work, the solid-state reaction between a 7 nm thick Ni0.9Co0.1 film and a silicon substrate has been studied. By combining various characterization methods (e.g. sheet resistance measurement, X-ray reflectivity, X-ray diffraction), a comprehensive phase sequence of the NiCo silicide formation has been proposed. At low temperature, we observed the formation of metal-rich Ni2Si-like phases: δ-(NiCo)2Si and θ-(NiCo)2Si. Contrary to Ni0.9Pt0.1 based silicides, the δ-Ni2Si phase appears before the θ-Ni2Si one. Beyond 320 °C, the (NiCo)Si monosilicide formation is initiated and this latter is complete at 400 °C. The presence of Co strongly decreases the NiSi2 formation temperature. This early formation of disilicide allows avoiding film agglomeration and enhances the thermal stability of NiSi silicide. Complementary studies using wavelength dispersive X-ray fluorescence allowed studying the cobalt behavior and highlighted the formation of a Co composition gradient into the metal-rich silicide phases at relatively low temperature (220–260 °C).

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives in terms of heterogeneous integration. We will review the opportunities brought by CoolCube™ and will present the most advanced technological demonstration of 3D CMOS over CMOS CoolCube™ integration.

While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ from usual copper/low-k, it is necessary to study how standard cells electrical characteristics will be affected. We modeled different descriptions of iBEOL in 14nm FDSOI process and simulated standard cells characteristics. The average power consumption is almost the same while large cells with high drive timing degradation can be up to 20% in the worst case. This sensitivity analysis allowed us to identify which parameters (permittivity, resistivity) have the greatest impact depending on standard cell type and provide technology and design guidelines. Our goal here was to limit the performance degradation to around 5% maximum for the bottom tier standard cells.

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over CMOS 3D VLSI integration on 300mm wafers is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.

Auteur correspondant: "philippe.rodriguez@cea.fr"; International audience; In this work, we studied the solid-state reaction between a Ni$_{0.9}$Co$_{0.1}$ film and a silicon substrate. NiCo silicide is considered to substitute Ni-and NiPt-based silicides in 3D integration in order to extend the bottom transistor thermal stability. Thanks to the combined analysis of sheet resistance data, X-ray reflectivity spectra modelling, X-ray diffraction and wavelength dispersive X-ray fluorescence analyses on Ni$_{0.9}$Co$_{0.1}$ /Si samples annealed at various temperatures, we were able to describe the phase sequence of the NiCo silicide formation.

In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. In order to relax this thermal budget limitation, the thermal stability of the bottom level must be increased, especially for the silicide. In that purpose, Ni0.9Co0.1 alloy is proposed to replace the current Ni0.85Pt0.15 silicide. For the first time, this Ni0.9Co0.1 salicide has been integrated on pMOS FDSOI transistors with state of the art process leading to performance improvements compared to the standard Ni0.85Pt0.15 salicide. In this study, the cobalt incorporation into the salicide has been investigated to enhance its thermal stability.

3D VLSI technology based on CoolCube™ process offers ultra-high density of integration with up to 108 3D Vias (3D-V) per mm2 offering gate level 3D integration capability. For process stability and wide range of temperature compliancy, Intermediate Back End of Line (IBEOL) is targeted to be made with Tungsten lines in a SiO 2 (k=3.9) dielectric, increasing equivalent resistivity by 6 and capacitance by 1.6 compared to standard Back End of Line (BEOL) (copper lines in low k dielectrics). In this study we propose to study impact in Performance, Power and Area (PPA) using W/SiO 2 compared to Cu/low-k IBEOL. Results show area gain up to 60.9% and performance gain up to 21.7% for 3D cases comparing to 2D using 28 nm FDSOI technology. Using W/SiO 2 shows limited impact on performance with maximal 1.93% degradation comparing to Cu/low-k IBEOL.

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Design of conventional 2D integrated circuits is becoming more and more challenging as we strive to keep on following Moore's law. Cost, thermal behavior, multiple patterning, increasing number of design rules, transistor characteristics, variability and back end properties coupled with a constant need for a higher integration of functions / peripherals are creating an increasingly complex equation to solve for designers. Moving to the next node and taking advantage of the technology are now far from being straightforward as time to market has never been so short for industry. In order to overcome or at least postpone the time when we'll have to face the "next node migration constraints", a possible solution could be staying at the same node and go 3D with possible benefits such as wire length reduction, power savings and increased operating frequency. Since more than ten years now, interconnect technologies like Through Silicon Via (TSV), High Density (HD)-TSV and Copper to Copper (Cu-Cu) have arisen to take advantage of this possible 3-dimensional physical implementation with proofs of concept [1] or more recently industrial products [2]. Main drawback of these technologies is that they are not shrinking at the same speed as transistors are, making them somehow power hungry; moreover the more they will shrink, the more precision will be needed for chip to chip alignment. To reach the highest possible standard cell and tier to tier interconnect densities required for cost-effective chips, 3D sequential integration process [3][4][5] (also known as Monolithic 3D or CoolCubeTM) is currently developed with main features being sequential fabrication of MOS layers and correlation of tier to tier interconnect size with process node allowing fine-grain 3D partitioning of designs. These particularities make it a durable opportunity to slow down next node design migration while still improving integration. To fully benefit from CoolCubeTM technology, a whole new way of designing circuits, from synthesis to place and route, will be required as some new challenges will arise. The point of this presentation is to show the possible use and limitations of the aforementioned technologies with a focus on Monolithic 3D and to give some insights about market expectations, challenges and available design techniques.

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presnts “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (