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AtNAP , an Arabidopsis NAC transcription factor family gene, functions as a negative regulator via transcriptional repression of AREB1 in salt stress response. AtNAP is an NAC family transcription factor in Arabidopsis and is known to be a positive regulator of senescence. However, its exact function and underlying molecular mechanism in stress responses are not well known. Here, we investigated functional roles of AtNAP in salt stress response. AtNAP expression significantly increased at the seedling stage, with higher expression in both shoots and roots under NaCl, mannitol, and ABA treatments. T-DNA insertional loss-of-function mutants of AtNAP were more tolerant to salt stress than wild type (WT), whereas AtNAP-overexpressing transgenic plants (OXs) were more sensitive to salt stress than WT during germination, seedling development, and mature plant stage. Transcript levels of stress-responsive genes in the ABA-dependent pathway, such as AREB1, RD20, and RD29B, were significantly higher and lower in atnap mutants and AtNAP OXs, respectively, than in WT under salt stress conditions, suggesting that AtNAP might negatively regulate the expression of those genes under salt stress conditions. Indeed, AtNAP repressed the promoter activity of AREB1 under normal and salt stress conditions. These results indicate that AtNAP functions as a negative regulator in the salt stress response. Our results, together with previous studies, suggest that AtNAP functions as a negative regulator in osmotic stress responses, whereas it functions as a positive regulator in senescence.

As various graphics processing unit architectures are deployed across broad computing spectrum from a hand-held or embedded device to a high-performance computing server, OpenCL becomes the de facto standard programming environment for general-purpose computing on graphics processing units. Unlike its CPU counterpart, OpenCL has several distinct features such as its disciplined memory model, which is partially inherited from conventional 3D graphics programming models. On the other hand, due to ever increasing memory bandwidth pressure and low power requirement, the capacity of on-chip caches in GPUs keeps increasing over time. Given such trends, we believe that we have interesting programming model/architecture co-optimization opportunities, in particular, how to energy-efficiently utilize large on-chip caches for GPUs. In this paper, as a showcase, we study the characteristics of the OpenCL memory model and propose a technique called GPU Region-aware energy-efficient non-inclusive cache hierarchy, or GREEN cache hierarchy. With the GREEN cache, our simulation results show that we can save 56 percent of dynamic energy in the L1 cache, 39 percent of dynamic energy in the L2 cache, and 50 percent of leakage energy in the L2 cache with practically no performance degradation and off-chip access increases.

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2 \microm-diameter, 6 \micro m-height through-silicon vias (TSVs) and 3.4\nbsp\microm-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

As scaling DRAM cells becomes more challenging and energy-efficient DRAM chips are in high demand, the DRAM industry has started to undertake an alternative approach to address these looming issues-that is, to vertically stack DRAM dies with through-silicon-vias (TSVs) using 3-D-IC technology. Furthermore, this emerging integration technology also makes heterogeneous die stacking in one DRAM package possible. Such a heterogeneous DRAM chip provides a unique, promising opportunity for computer architects to contemplate a new memory hierarchy for future system design. In this paper, we study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency. In particular, we found that, if we want to design an SRAM row cache in a DRAM chip, simple stacking alone cannot address the majority of traditional SRAM row cache design issues. In this paper, to address these issues, we propose a novel floorplan and several architectural techniques that fully exploit the benefits of 3-D stacking technology. Our multi-core simulation results with memory-intensive applications suggest that, by tightly integrating a small row cache with its corresponding DRAM array, we can improve performance by 30% while saving dynamic energy by 31%.

Arabidopsis AtERF71/HRE2, a transcription activator, is located in the nucleus and is involved in the signal transduction of low oxygen and osmotic stresses. In this study, microarray analysis using AtERF71/HRE2-overexpressing transgenic plants was performed to identify genes downstream of AtERF71/HRE2. A total of 161 different genes as well as AtERF71/HRE2 showed more than a twofold higher expression in AtERF71/HRE2-overexpressing transgenic plants compared with wild-type plants. Among the 161 genes, 24 genes were transcriptional regulators, such as transcription factors and DNA-binding proteins, based on gene ontology annotations, suggesting that AtERF71/HRE2 is an upstream transcription factor that regulates the activities of various downstream genes via these transcription regulators. RT-PCR analysis of 15 genes selected out of the 161 genes showed higher expression in AtERF71/HRE2-overexpressing transgenic plants, validating the microarray data. On the basis of Genevestigator database analysis, 51 genes among the 161 genes were highly expressed under low oxygen and/or osmotic stresses. RT-PCR analysis showed that the expression levels of three genes among the selected 15 genes increased under low oxygen stress and another three genes increased under high salt stress, suggesting that these genes might be downstream genes of AtERF71/HRE2 in low oxygen or high salt stress signal transduction. Microarray analysis results indicated that AtERF71/HRE2 might also be involved in the responses to other abiotic stresses and also in the regulation of plant developmental processes.

Plants have developed various regulatory pathways to adapt to environmental stresses. In this study, we identified Arabidopsis MKKK20 as a regulator in the response to osmotic stress. mkkk20 mutants were found to be sensitive to high concentration of salt and showed higher water loss rates than wild-type (WT) plants under dehydration conditions. In addition, mkkk20 mutants showed higher accumulation of superoxide, a reactive oxygen species (ROS), compared to WT plants under high salt condition. In contrast, transgenic plants overexpressing MKKK20 displayed tolerance to salt stress. MKKK20 transcripts were increased by the treatments with NaCl, mannitol, MV, sorbitol, and cold, suggesting that MKKK20 is involved in the response to osmotic, ROS, and cold stresses. In-gel kinase assay showed that MKKK20 regulates the activity of MPK6 under NaCl, cold, and H(2)O(2) treatments. Taken together, our results suggest that MKKK20 might be involved in the response to various abiotic stresses, especially osmotic stress, through its regulation of MPK6 activity.

Various transcription factors are involved in the response to environmental stresses in plants. In this study, we characterized AtERF71/HRE2, a member of the Arabidopsis AP2/ERF family, as an important regulator of the osmotic and hypoxic stress responses in plants. Transcript level of AtERF71/HRE2 was highly increased by anoxia, NaCl, mannitol, ABA, and MV treatments. aterf71/hre2 loss-of-function mutants displayed higher sensitivity to osmotic stress such as high salt and mannitol, accumulating higher levels of ROS under high salt treatment. In contrast, AtERF71/HRE2-overexpressing transgenic plants showed tolerance to salt and mannitol as well as flooding and MV stresses, exhibiting lower levels of ROS under high salt treatment. AtERF71/HRE2 protein was localized in the nucleus, and the C-terminal region of AtERF71/HRE2 was required for transcription activation activity. Taken together, our results suggest that AtERF71/HRE2 might function as a transcription factor involved in the response to osmotic stress as well as hypoxia.

The plant hormone, abscisic acid (ABA), is a main signal transducer that confers abiotic stress tolerance to plants. Although the pathway of ABA production and the genes catalyzing its biosynthesis are largely defined, the regulatory mechanism of ABA biosynthesis in response to abiotic stress remains much unknown. In this study, to identify upstream genes regulating ABA biosynthesis involved in abiotic stress signal transduction, Arabidopsis thaliana mutants with altered promoter activity of 9-cis-epoxycarotenoid dioxygenase 3 (NCED3), a key gene in ABA biosynthesis, were identified and characterized. Among selected mutants, lenc1 (for low expression of NCED3 1) after dehydration treatment had lower AtNCED3 promoter activity compared with wild type. lenc1 mutation is recessive and is located on chromosome 4. Expression analysis of AtNCED3 and quantification of ABA levels showed that both the AtNCED3 transcripts and the endogenous ABA in lenc1 were less abundant than in wild type under dehydration treatments. The lenc1 was hypersensitive to methyl viologen (MV), LiCl, NaCl and high light. The aerial part of lenc1 lost water faster than wild type possibly due to a larger stomata opening. Our results suggest LENC1 might act as a positive regulator in AtNCED3 gene expression under osmotic stress.

As dynamic RAM scaling approaches its physical limit, phase-change memory is the most mature and well-studied option for potential DRAM replacement. However, malicious wear-out attacks can exploit PCM's limited write endurance. To address this, a low-cost wear-leveling scheme can dynamically randomize the data addresses across the entire address space and obfuscate their actual locations from users and system software.

Plants adapt to abiotic stresses by complex mechanisms involving various stress-responsive genes. Here, we identified a DEAD-box RNA helicase (RH) gene, AtRH17, in Arabidopsis, involved in salt-stress responses using activation tagging, a useful technique for isolating novel stress-responsive genes. AT895, an activation tagging line, was more tolerant than wild type (WT) under NaCl treatment during germination and seedling development, and AtRH17 was activated in AT895. AtRH17 possesses nine well-conserved motifs of DEAD-box RHs, consisting of motifs Q, I, Ia, Ib, and II-VI. Although at least 12 orthologs of AtRH17 have been found in various plant species, no paralog occurs in Arabidopsis. AtRH17 protein is subcellularily localized in the nucleus. AtRH17-overexpressing transgenic plants (OXs) were more tolerant to high concentrations of NaCl and LiCl compared with WT, but no differences from WT were detected among seedlings exposed to mannitol and freezing treatments. Moreover, in the mature plant stage, AtRH17 OXs were also more tolerant to NaCl than WT, but not to drought, suggesting that AtRH17 is involved specifically in the salt-stress response. Notably, transcriptions of well-known abscisic acid (ABA)-dependent and ABA-independent stress-response genes were similar or lower in AtRH17 OXs than WT under salt-stress treatments. Taken together, our findings suggest that AtRH17, a nuclear DEAD-box RH protein, is involved in salt-stress tolerance, and that its overexpression confers salt-stress tolerance via a pathway other than the well-known ABA-dependent and ABA-independent pathways.

In this study, we constructed various kinds of binary vectors with the pPZP backbone for co-overexpression, tissue- or development-specific expression and stress-inducible expression, and validated them for ectopic expression of target genes. Using a modified CaMV 35S promoter, a binary vector was generated for co-overexpression of two different genes and was confirmed to be efficient for overexpressing two different target genes at the same time and place. Binary vectors containing At2S3, KNAT1 or LFY promoters were constructed for tissue-specific or development-specific gene expression, and the binary vectors were suited for embryo/young seedling stage-, shoot apical meristem- or leaf primordia-specific expressions. Furthermore, the binary vectors containing RD29A or AtNCED3 promoters were validated as suitable vectors for gene expression induced by abiotic stresses such as high salt, ABA, MV and low temperature. Taken together, the binary vectors constructed in this study would be very useful for analyzing the biological functions of target genes and molecular mechanisms through ectopic expression.

A traditional fixed-function graphics accelerator has evolved into a programmable general-purpose graphics processing unit over the last few years. These powerful computing cores are mainly used for accelerating graphics applications or enabling low-cost scientific computing. To further reduce the cost and form factor, an emerging trend is to integrate GPU along with the memory controllers onto the same die with the processor cores. However, given such a system-on-chip, the GPU, while occupying a substantial part of the silicon, will sit idle and contribute nothing to the overall system performance when running non-graphics workloads or applications lack of data-level parallelism. In this paper, we propose COMPASS, a compute shader-assisted data prefetching scheme, to leverage the GPU resource for improving single-threaded performance on an integrated system. By harnessing the GPU shader cores with very lightweight architectural support, COMPASS can emulate the functionality of a hardware-based prefetcher using the idle GPU and successfully improve the memory performance of single-thread applications. Moreover, thanks to its flexibility and programmability, one can implement the best performing prefetch scheme to improve each specific application as demonstrated in this paper. With COMPASS, we envision that a future application vendor can provide a custom-designed COMPASS shader bundled with its software to be loaded at runtime to optimize the performance. Our simulation results show that COMPASS can improve the single-thread performance of memory-intensive applications by 68% on average.

In this paper, a coexistence mechanism between IEEE 802.15.4 and IEEE 802.11b, Active Channel Reservation for cOexiStence (ACROS), is proposed. The key idea underlining ACROS is to reserve the channel for IEEE 802.15.4 transmission, where IEEE 802.11 transmissions are forbidden. The request-to-send (RTS)/clear-to send (CTS) mechanism within IEEE 802.11 is used to reserve a channel. The proposed ACROS mechanism is implemented into a PC based prototype. The embedded version of ACROS is also developed to mitigate the timing drift problem in the PC-based ACROS. The efficiency of ACROS is shown using the throughput and packet error rate achieved in actual experiments.

An updated take on Amdahl's analytical model uses modern design constraints to analyze many-core design alternatives. The revised models provide computer architects with a better understanding of many-core design types, enabling them to make more informed tradeoffs.

Despite increasing reports that CCCH zinc finger proteins function in plant development and stress responses, the functions and molecular aspects of many CCCH zinc finger proteins remain uncharacterized. Here, we characterized the biological and molecular functions of AtC3H17, a unique Arabidopsis gene encoding a non-tandem CCCH zinc finger protein. AtC3H17 was ubiquitously expressed throughout the life cycle of Arabidopsis plants and their organs. The rate and ratio of seed germination of atc3h17 mutants were slightly slower and lower, respectively, than those of the wild type (WT), whereas AtC3H17-overexpressing transgenic plants (OXs) showed an enhanced germination rate. atc3h17 mutant seedlings were smaller and lighter than WT seedlings while AtC3H17 OX seedlings were larger and heavier. In regulation of flowering time, atc3h17 mutants showed delayed flowering, whereas AtC3H17 OXs showed early flowering compared with the WT. In addition, overexpression of AtC3H17 affected seed development, displaying abnormalities compared with the WT. AtC3H17 protein was localized to the nucleus and showed transcriptional activation activity in yeast and Arabidopsis protoplasts. The N-terminal region of AtC3H17, containing a conserved EELR-like motif, was necessary for transcriptional activation activity, and the two conserved glutamate residues in the EELR-like motif played an important role in transcriptional activation activity. Real-time PCR and transactivation analyses showed that AtC3H17 might be involved in seed development via transcriptional activation of OLEO1, OLEO2 and CRU3. Our results suggest that AtC3H17 has pleiotropic effects on vegetative development such as seed germination and seedling growth, flowering and seed development, and functions as a nuclear transcriptional activator in Arabidopsis.

AtSFT12, an Arabidopsis Qc-SNARE protein, is localized to Golgi organelles and is involved in salt and osmotic stress responses via accumulation of Na + in vacuoles. To reduce the detrimental effects of environmental stresses, plants have evolved many defense mechanisms. Here, we identified an Arabidopsis Qc-SNARE gene, AtSFT12, involved in salt and osmotic stress responses using an activation-tagging method. Both activation-tagged plants and overexpressing transgenic plants (OXs) of the AtSFT12 gene were tolerant to high concentrations of NaCl, LiCl, and mannitol, whereas loss-of-function mutants were sensitive to NaCl, LiCl, and mannitol. AtSFT12 transcription increased under NaCl, ABA, cold, and mannitol stresses but not MV treatment. GFP-fusion AtSFT12 protein was juxtaposed with Golgi marker, implying that its function is associated with Golgi-mediated transport. Quantitative measurement of Na+ using induced coupled plasma atomic emission spectroscopy revealed that AtSFT12 OXs accumulated significantly more Na+ than WT plants. In addition, Na+-dependent fluorescence analysis of Sodium Green showed comparatively higher Na+ accumulation in vacuoles of AtSFT12 OX cells than in those of WT plant cells after salt treatments. Taken together, our findings suggest that AtSTF12, a Golgi Qc-SNARE protein, plays an important role in salt and osmotic stress responses and functions in the salt stress response via sequestration of Na+ in vacuoles.

S-RBP11, a chloroplast protein, which was isolated using activation tagging system, is shown to be the first Arabidopsis small RNA-binding group protein involved in oxidative and salt stress responses. Activation tagging is one of the most powerful tools in reverse genetics. In this study, we isolated S-RBP11, encoding a small RNA-binding protein in Arabidopsis, by salt-resistant activation tagging line screen and then characterized its function in the abiotic stress response. The isolated activation tagging line of S-RBP11 as well as transgenic plants overexpressing S-RBP11 showed increased tolerance to salt and MV stresses compared to WT plants, whereas s-rbp11 mutants were more sensitive to salt stresses. Transcription of S-RBP11 was elevated upon MV treatment but not NaCl or cold treatment. Interestingly, S-RBP11 protein was localized in the chloroplast and the N-terminal 34 amino acid region of S-RBP11 was necessary for its chloroplast targeting. Our results suggest that S-RBP11 is a chloroplast protein involved in the responses to salt and oxidative stresses.

SIMD execution units in GPUs are increasingly used for high performance and energy efficient acceleration of general purpose applications. However, SIMD control flow divergence effects can result in reduced execution efficiency in a class of GPGPU applications, classified as divergent applications. Improving SIMD efficiency, therefore, has the potential to bring significant performance and energy benefits to a wide range of such data parallel applications. Recently, the SIMD divergence problem has received increased attention, and several micro-architectural techniques have been proposed to address various aspects of this problem. However, these techniques are often quite complex and, therefore, unlikely candidates for practical implementation. In this paper, we propose two micro-architectural optimizations for GPGPU architectures, which utilize relatively simple execution cycle compression techniques when certain groups of turned-off lanes exist in the instruction stream. We refer to these optimizations as basic cycle compression (BCC) and swizzled-cycle compression (SCC), respectively. In this paper, we will outline the additional requirements for implementing these optimizations in the context of the studied GPGPU architecture. Our evaluations with divergent SIMD workloads from OpenCL (GPGPU) and OpenGL (graphics) applications show that BCC and SCC reduce execution cycles in divergent applications by as much as 42% (20% on average). For a subset of divergent workloads, the execution time is reduced by an average of 7% for today's GPUs or by 18% for future GPUs with a better provisioned memory subsystem. The key contribution of our work is in simplifying the micro-architecture for delivering divergence optimizations while providing the bulk of the benefits of more complex approaches.

Aurora A kinase has drawn considerable attention as a therapeutic target for cancer therapy. However, the underlying molecular and cellular mechanisms of the anticancer effects of Aurora A kinase inhibition are still not fully understood. Herein, we show that depletion of Aurora A kinase by RNA interference (RNAi) in hepatocellular carcinoma (HCC) cells upregulated FoxO1 in a p53-dependent manner, which induces cell cycle arrest. Introduction of an RNAi-resistant Aurora A kinase into Aurora A-knockdown cells resulted in downregulation of FoxO1 expression and rescued proliferation. In addition, silencing of FoxO1 in Aurora A-knockdown cells allowed the cells to exit cytostatic arrest, which, in turn, led to massive cell death. Our results suggest that FoxO1 is responsible for growth arrest at the G2/M phase that is induced by Aurora A kinase inhibition.

Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1–4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM (see Fig. 10.6.1). Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5×5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.

In this paper, we present a novel approach of using the integrated GPU to accelerate conventional operations that are normally performed by the CPUs, the bulk memory operations, such as memcpy or memset. Offloading the bulk memory operations to the GPU has many advantages, i) the throughput driven GPU outperforms the CPU on the bulk memory operations; ii) for on-die GPU with unified cache between the GPU and the CPU, the GPU private caches can be leveraged by the CPU for storing moved data and reducing the CPU cache bottleneck; iii) with additional lightweight hardware, asynchronous offload can be supported as well; and iv) different from the prior arts using dedicated hardware copy engines (e.g., DMA), our approach leverages the exiting GPU hardware resources as much as possible. The performance results based on our solution showed that offloaded bulk memory operations outperform CPU up to 4.3 times in micro benchmarks while still using less resources. Using eight real world applications and a cycle based full system simulation environment, the results showed 30% speedup for five, more than 20% speedup for two of the eight applications.

Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).

As DRAM scaling becomes more challenging and its energy efficiency receives a growing concern for data center operation, an alternative approach— stacking DRAM die with thru-silicon vias (TSV) using 3-D integration technology is being undertaken by industry to address these looming issues. Furthermore, 3-D technology also enables heterogeneous die stacking within one DRAM package. In this paper, we study how to design such a heterogeneous DRAM chip for improving both performance and energy efficiency, in particular, we propose a novel floorplan and several architectural techniques to fully exploit the benefits of 3-D die stacking technology when integrating an SRAM row cache into a DRAM chip. Our multi-core simulation results show that, by tightly integrating a small row cache with its corresponding DRAM array, we can improve performance by 30% while saving dynamic energy by 31% for memory intensive applications.

Plants have developed disparate regulatory pathways to adapt to environmental stresses. In this study, we identified MKK4 as an important mediator of plant response to osmotic stress. mkk4 mutants were more sensitive to high salt concentration than WT plants, exhibiting higher water-loss rates under dehydration conditions and additionally accumulating high levels of ROS. In contrast, MKK4-overexpressing transgenic plants showed tolerance to high salt as well as lower water-loss rates under dehydration conditions. In-gel kinase assays revealed that MKK4 regulates the activity of MPK3 upon NaCl exposure. Semi-quantitative RT-PCR analysis showed that expression of NCED3 and RD29A was lower and higher in mkk4 mutants and MKK4-overexpressing transgenic plants, respectively. Taken together, our results suggest that MKK4 is involved in the osmotic-stress response via its regulation of MPK3 activity.

As technology scaling poses a threat to DRAM scaling due to physical limitations such as limited charge, alternative memory technologies including several emerging non-volatile memories are being explored as possible DRAM replacements. One main roadblock for wider adoption of these new memories is the limited write endurance, which leads to wear-out related permanent failures. Furthermore, technology scaling increases the variation in cell lifetime resulting in early failures of many cells. Existing error correcting techniques are primarily devised for recovering from transient faults and are not suitable for recovering from permanent stuck-at faults, which tend to increase gradually with repeated write cycles. In this paper, we propose SAFER, a novel hardware-efficient multi-bit stuck-at fault error recovery scheme for resistive memories, which can function in conjunction with existing wear-leveling techniques. SAFER exploits the key attribute that a failed cell with a stuck-at value is still readable, making it possible to continue to use the failed cell to store data, thereby reducing the hardware overhead for error recovery. SAFER partitions a data block dynamically while ensuring that there is at most one fail bit per partition and uses single error correction techniques per partition for fail recovery. SAFER increases the number of recoverable fails and achieves better lifetime improvement with smaller hardware overhead relative to recently proposed Error Correcting Pointers and even ideal hamming coding scheme.

We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.

Virtual caches are employed as L1 caches of both high performance and embedded processors to meet their short latency requirements. However, they also introduce the synonym problem where the same physical cache line can be present at multiple locations in the cache due to their distinct virtual addresses, leading to potential data consistency issues. To guarantee correctness, common hardware solutions either perform serial lookups for all possible synonym locations in the L1 consuming additional energy or employ a reverse map in the L2 cache that incurs a large area overhead. Such preventive mechanisms are nevertheless indispensable even though synonyms may not always be present during the execution.In this paper, we study the synonym issue using Windows applications workload and propose a technique based on Bloom filters to reduce synonym lookup energy. By tracking the address stream using Bloom filters, we can confidently exclude the addresses that were never observed to eliminate unnecessary synonym lookups, thereby saving energy in the L1 cache. Bloom filters have a very small area overhead making our implementation a feasible and attractive solution for synonym detection. Our results show that synonyms in these applications actually constitutes less than 0.1% of the total cache misses. By applying our technique, the dynamic energy consumed in L1 data cache can be reduced up to 32.5%. When taking leakage energy into account, the savings is up to 27.6%.