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Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory
- Source :
- CICC
- Publication Year :
- 2010
- Publisher :
- IEEE, 2010.
-
Abstract
- We describe the design and analysis of 3D-MAPS, a 64-core 3D-stacked memory-on-processor running at 277 MHz with 63 GB/s memory bandwidth, sent for fabrication using Tezzaron's 3D stacking technology. We also describe the design flow used to implement it using industrial 2D tools and custom add-ons to handle 3D specifics.
Details
- Database :
- OpenAIRE
- Journal :
- IEEE Custom Integrated Circuits Conference 2010
- Accession number :
- edsair.doi...........a6e28610d2b68ba5fc28e3d782eb5824
- Full Text :
- https://doi.org/10.1109/cicc.2010.5617464