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Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

Authors :
Dae Hyun Kim
Dongki Kim
Dong Hyuk Woo
Sunggu Lee
Sungkwang Lee
Sungjoo Yoo
JaeWoong Chung
Source :
DAC
Publication Year :
2012
Publisher :
ACM, 2012.

Abstract

Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).

Details

Database :
OpenAIRE
Journal :
Proceedings of the 49th Annual Design Automation Conference
Accession number :
edsair.doi...........cf9de70419cb88e2f4af02a1a944e338
Full Text :
https://doi.org/10.1145/2228360.2228519