8 results on '"Di Sarro J"'
Search Results
2. Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations.
3. ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology.
4. A scalable SCR compact model for ESD circuit simulation.
5. A dual-base triggered SCR with very low leakage current and adjustable trigger voltage.
6. Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies.
7. Study of Design Factors Affecting Turn-on Time of Silicon Controlled Rectifiers (SCRS) in 90 and 65nm Bulk CMOS Technologies.
8. Use of Low-Cost Magnetic Materials Containing Waste Derivatives for the (Photo)-Fenton Removal of Organic Pollutants.
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.