48 results on '"Dennard, R."'
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2. SEMICONDUCTOR DEVICE INCLUDING DUAL-LAYER SOURCE/DRAIN REGION
3. High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET
4. FDSOI CMOS with dielectrically-isolated back gates and 30nm LG high-γ/metal gate
5. Technologies to further reduce soft error susceptibility in SOI
6. Technical literature [Reprint of "Field-Effect Transistor Memory" (US Patent No. 3,387,286)]
7. Ion Implanted MOSFET's With Very Short Channel Lengths
8. Design of micron MOS switching devices
9. Silicon CMOS devices beyond scaling
10. A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time
11. Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs.
12. Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
13. Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon
14. Design and characteristics of n-channel insulated-gate field-effect transistors
15. Modeling and characterization of long on-chip interconnections for high-performance microprocessors
16. CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications
17. A High Performance Liquid-Nitrogen CMOS SRAM Technology.
18. 0.5 μm CMOS Device Design and Characterization.
19. A CMOS Off-Chip Driver/Receiver with Reduced Signal Swing and Reduced Power-Supply Disturbance.
20. Channel profile optimization and device design for low-power high-performance dynamic-threshold MOSFET.
21. Experimental technology and performance of 0.1-µm-gate-length FETs operated at liquid-nitrogen temperature
22. A Hardened Field Insulator.
23. A HIGH PERFORMANCE LIQUID-NITROGEN CMOS SRAM TECHNOLOGY
24. Fabrication of a miniature 8K‐bit memory chip using electron‐beam exposure
25. Technology challenges for ultrasmall silicon MOSFET’s
26. Behavior of the ferroresonant series circuit containing a square-loop reactor
27. IGFET circuit performance: N-channel vs P-channel
28. A Vestigial-Sideband, Phase-Reversal Data Transmission System
29. Design and Characteristics of n-Channel Insulated-gate Field-effect Transistors
30. An experimental high-density memory array fabricated with electron beam
31. Session 9 nonvolatile memories
32. Soft error rate scaling for emerging SOI technology options
33. 1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro
34. High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions.
35. Soft error rate scaling for emerging SOI technology options.
36. Scalability and biasing strategy for CMOS with active well bias.
37. CMOS with active well bias for low-power and RF/analog applications.
38. 1 GHz fully pipelined 3.7 ns address access time 8 k×1024 embedded DRAM macro.
39. 0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography.
40. A Fully Scaled Half-Micrometer NMOS Technology Using Direct-Write E-Beam Lithography.
41. Modeling and Control of Alpha-Particle Effects in Scaled-Down VLSI Circuits.
42. A 34µm2DRAM cell fabricated with a 1µm single-level polycide FET technology.
43. History dependence of non-fully depleted (NFD) digital SOI circuits.
44. Accurate measurement of pass-transistor leakage current in SOI MOSFET's.
45. Session 9 nonvolatile memories.
46. Iddq Testing for High Performance CMOS - The Next Ten Years.
47. Have fun with this budget.
48. One widow's story ... would your wife be prepared?
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