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This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (VT) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in VT (ΔVT) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔVT is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔVT during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔVT with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device's thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems. [ABSTRACT FROM AUTHOR]

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors. [ABSTRACT FROM AUTHOR]

In this paper the results of modeling and simulation of NBTI effects in p-channel power VDMOS transistor have been presented. Based on the experimental results, the threshold voltage shifts and changes of transconductance during the NBT stress have been modeled and implemented in the PSPICE model of the IRF9520 transistor. By predefining the threshold voltage value before the NBT stress, and by assigning the stress time, transfer characteristics of the transistor are simulated. These characteristics are within (1.33÷11.25)% limits in respect to the measured ones, which represents a good agreement. [Projekat Ministarstva nauke Republike Srbije, br. OI 171026 i br. TR 32026]

The behaviour of oxide and interface defects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors, firstly degraded by the gamma-irradiation and electric field and subsequently recovered and annealed, is presented. By analyzing the transfer characteristic shifts, the changes of threshold voltage and underlying changes of gate oxide and interface trap densities during the stress (recovery, annealing) of investigated devices, it is shown that these two types of stress influence differently on the gate oxide and the SiO2-Si interface. [Projekat Ministarstva nauke Republike Srbije, br. OI171026]

The annealing of radiation-induced defects in burn-in stressed n-channel power VDMOSFETs with thick gate oxides (100 and 120 nm) is analysed. In comparison with the previous spontaneous recovery, the changes of device electrical parameters observed during annealing are highlighted by the elevated temperature and voltage applied to the gate, and are more pronounced in devices with a 120 nm thick gate oxide. The threshold voltage of VDMOSFETs with a 100 nm thick gate oxide during annealing has an initially slow growth, but then increases rapidly and reaches the value higher than the pre-irradiation one (rebound effect). In the case of devices with a 120 nm thick gate oxide, the threshold voltage behaviour also consists of a slight initial increase followed by a rapid, but dilatory increase, with an obvious tendency to achieve the rebound. The changes of channel carrier mobility during annealing are similar in all samples: at first, it slowly and then rapidly declines, and after reaching the minimum it begins to increase. In the case of VDMOSFETs with a thicker gate oxide, these changes are much slower. The underlying changes in the densities of gate oxide-trapped charge and interface traps are also delayed in devices with a thicker gate oxide. All these phenomena occur with certain delay in burn-in stressed devices compared to unstressed ones. The leading role in the mechanisms responsible for the observed phenomena is attributed to hydrogen related species.

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analyzed in terms of the mechanisms responsible. In the case of positive bias stressing, electron tunneling from neutral oxide traps associated with trivalent silicon ≡Sio defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunneling from the charged oxide traps ≡Sio+ to interface-trap precursors ≡Sis-H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunneling from the silicon valence band to oxygen vacancy defects ≡Sio / Sio≡ is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors ≡Sis−Η with the charged oxide traps ≡Sio+ Sio≡ and H+ ions are proposed to be responsible for interface trap buildup.

This paper describes and compares the recovery of the threshold voltage shift of lateral and vertical p-channel double diffused MOS field effect transistors caused by irradiation. The internal structure of both p-VDMOS and p-LDMOS devices is analyzed, alongside a thermal compensation technique that takes advantage of the analyzed structures. Thermal characterization and irradiation are performed on two different series of commercial devices: the CD4007, which contains p-channel lateral DMOSFET, and the commercial p-channel power vertical DMOSFETs IRF9520 and IRF9530. After irradiation, thermal annealing was carried out, in order to measure threshold voltage recovery and to compare and assess both groups of devices as dosimeters. The measuring setup and conditions for all experiment phases are described in detail. The results are discussed, and the usage of these devices as dosimeters in some commercial applications is considered. [ABSTRACT FROM AUTHOR]

This paper describes a new method for measuring and characterizing electrical parameters of ceramic materials. In addition, a comparison of experimental results obtained by manual measurement and an application of a new method for characterizing doped BaTiO3 ceramics at different temperatures and frequencies was performed. An LCR meter and a programmable testing furnace were used to measure the material’s dielectric parameters as a function of temperature. When measuring the parameters using the manual method, the results were obtained by manual control of the LCR meter, that is, they were measured by manually setting the parameters. The results were compared with those obtained using a new method for automatic control of the LCR meter, for which an application was developed. This comparison shows that feature measurement can be done fully automatically. By measuring samples of Er/BaTiO3 doped ceramics, it was possible to compare the results obtained by both methods. Based on the analysis of the measured results, it can be concluded that the new method is more precise, and the results are easier to manipulate in further work. In addition, the new method enables greater reproducibility of measurements, compared to the application of the manual method, which allows one measurement to be performed during the day. The described new method provides the possibility to measure material characteristics without the presence of a human factor. [ABSTRACT FROM AUTHOR]

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