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Carbon nanotubes (CNTs) are a type of nanomaterial that have excellent electrical properties such as high carrier mobility, high saturation velocity, and small inherent capacitance, showing great promise in radio frequency (RF) applications. Decades of development have been made mainly on cut-off frequency and amplification; however, frequency conversion for RF transceivers, such as CNT-based mixers, has been rarely reported. In this work, based on randomly oriented carbon nanotube films, we focused on exploring the frequency conversion capability of CNT-based RF mixers. CNT-based RF transistors were designed and fabricated with a gate length of 50 nm and gate width of 100 μm to obtain nearly 30 mA of total current and 34 mS of transconductance. The Champion RF transistor has demonstrated cut-off frequencies of 78 GHz and 60 GHz for fT and fmax, respectively. CNT-based mixers achieve high conversion gain from −11.4 dB to −17.5 dB at 10 to 15 GHz in the X and Ku bands. Additionally, linearity is achieved with an input third intercept (IIP3) of 18 dBm. It is worth noting that the results from this work have no matching technology or tuning instrument assistance, which lay the foundations for the application of Ku band transceivers integrated with CNT amplifiers. [ABSTRACT FROM AUTHOR]

A high conversion gain, low noise up-conversion mixer for 5G New Radio band (850 MHz) Internet of Thing (IoT) applications implemented in UMC 0.18 μm standard CMOS technology is presented. The proposed mixer is based on the Flipped voltage follower current mirror with a passive switching circuit. The proposed up-conversion mixer achieves a noise figure (NF) of 4.4 dB, maximum Conversion Gain (CG) of 33.85 dB, maximum input third-order intercept point (IIP3) of 33.16 dBm, and output third-order intercept point (OIP3) of 11.89 dBm. It has a total power consumption of 23.58 mW with a 1.2 V supply voltage. The overall chip area of the design is 26.5 µm × 54.9 µm. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are a type of nanomaterial that have excellent electrical properties such as high carrier mobility, high saturation velocity, and small inherent capacitance, showing great promise in radio frequency (RF) applications. Decades of development have been made mainly on cut-off frequency and amplification; however, frequency conversion for RF transceivers, such as CNT-based mixers, has been rarely reported. In this work, based on randomly oriented carbon nanotube films, we focused on exploring the frequency conversion capability of CNT-based RF mixers. CNT-based RF transistors were designed and fabricated with a gate length of 50 nm and gate width of 100 μm to obtain nearly 30 mA of total current and 34 mS of transconductance. The Champion RF transistor has demonstrated cut-off frequencies of 78 GHz and 60 GHz for fT and fmax, respectively. CNT-based mixers achieve high conversion gain from −11.4 dB to −17.5 dB at 10 to 15 GHz in the X and Ku bands. Additionally, linearity is achieved with an input third intercept (IIP3) of 18 dBm. It is worth noting that the results from this work have no matching technology or tuning instrument assistance, which lay the foundations for the application of Ku band transceivers integrated with CNT amplifiers.

This paper presents a highly linear and high gain down conversion mixer for ultra-wide band receivers for Internet of Things (IoT) applications. The proposed mixer is based on UMC 180 nm technology and is intended for use in the sub-6 GHz radio frequency spectrum. To reduce the effective threshold voltage for low voltage operation, the forward body bias approach has been used with reverse biased diodes. It also reduces the leakage current and improves the noise figure. The modified derivative superposition technique has been employed in transconductance stage to improve the linearity (IIP3) by suppressing third order nonlinear components of the signal. The gm-boosting approach has also been used with the MDS technique to improve Conversion Gain (CG). CG of 17.95 dB, IIP3 of 38.2 dBm, and Noise Figure (NF) of 6.23 dB are achieved with the proposed design. This circuit operates at 0.9 V and consumes 1.89 mW of power. [ABSTRACT FROM AUTHOR]

The Photon Counting Histogram Expectation Maximization (PCH-EM) algorithm has recently been reported as a candidate method for the characterization of Deep Sub-Electron Read Noise (DSERN) image sensors. This work describes a comprehensive demonstration of the PCH-EM algorithm applied to a DSERN capable quanta image sensor. The results show that PCH-EM is able to characterize DSERN pixels for a large span of quanta exposure and read noise values. The per-pixel characterization results of the sensor are combined with the proposed Photon Counting Distribution (PCD) model to demonstrate the ability of PCH-EM to predict the ensemble distribution of the device. The agreement between experimental observations and model predictions demonstrates both the applicability of the PCD model in the DSERN regime as well as the ability of the PCH-EM algorithm to accurately estimate the underlying model parameters.

We develop a novel algorithm for characterizing Deep Sub-Electron Read Noise (DSERN) image sensors. This algorithm is able to simultaneously compute maximum likelihood estimates of quanta exposure, conversion gain, bias, and read noise of DSERN pixels from a single sample of data with less uncertainty than the traditional photon transfer method. Methods for estimating the starting point of the algorithm are also provided to allow for automated analysis. Demonstration through Monte Carlo numerical experiments are carried out to show the effectiveness of the proposed technique. In support of the reproducible research effort, all of the simulation and analysis tools developed are available on the MathWorks file exchange (Hendrickson and Haefner, 2022).

Recently, the demand for small, low-cost electronics has increased the use of cost-effective tiny inductors in power-management ICs (PMICs). However, the conduction loss caused by the parasitic DC resistance (RDCR) of a small inductor leads to low efficiency, which reduces the battery usage time and may also cause thermal problems in mobile devices. In particular, these issues become critical when a conventional boost converter (CBC) is used to achieve high-output voltage due to the large inductor current. In addition, as the output voltage increases, a number of issues become more serious, such as large output voltage ripple, conversion-ratio limit, and overlap loss. To solve these issues, this paper proposed a high-voltage boost converter with dual-current flows (HVDF). The proposed HVDF can achieve a higher efficiency than a CBC by reducing the total conduction loss in heavy load current conditions with a small inductor. Moreover, because in the HVDF, the current delivered to the output becomes continuous, unlike in the CBC with its discontinuous output delivery current, the output voltage ripple can be significantly reduced. Also, the conversion gain of the HVDF is less sensitive to RDCR than that of the CBC. To further increase the conversion gain, a time-interleaved charge pump can be connected in series with the HVDF (HVDFCP) to achieve higher output voltage beyond the limit of the conversion gain in the HVDF while maintaining the advantages of a low inductor current and small output voltage ripple. Simulations using PSIM were performed along with a detailed numerical analysis of the conduction losses in the proposed structures. The simulation results were discussed and compared with those of the conventional structures. [ABSTRACT FROM AUTHOR]

A low-voltage, low-power, high-conversion-gain, short-range up-conversion Gilbert mixer for the licence-free band (865–867 MHz) in India is presented. In this work, the Gilbert cell transconductance stage is replaced by an inverter amplifier with a resistive feedback current mirror. The current bleeding technique is also applied to attain high conversion gain (CG) and low noise figure (NF). The design is realised in 180 nm CMOS SCL process technology and powered by 0.9 V. The proposed design offers a CG of 26.62 dB and an NF of 6.48 dB@866.5 MHz at the expense of an OIP3 of −3.3 dBm with the total power consumption of 1.94 mW. Its layout occupies a core area of 52 µm × 53 µm. [ABSTRACT FROM AUTHOR]

This paper compares two in-pixel source follower stage designs for low noise CMOS image sensors embedded both on a same 5 mm by 5 mm chip fabricated in a 180nm CIS process. The presented chip embeds two pixel variants, one based on a body-effect-canceled thin oxide PMOS and the other embeds a native thick oxide NMOS. On the other hand they share the same sense node, same amplification circuit and 11bit single slope analog to digital converter (SS-ADC). The imager characterization demonstrates a histogram peak noise of 0.34e $^{-}_{\text{RMS}}$ with the PMOS SF pixel and 0.47e $^{-}_{\text{RMS}}$ with the NMOS SF at maximum analog gain. This performance is obtained at room temperature and 119 frame per second. Both pixel variants demonstrate a full well capacity over 5600 electrons.

A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal–oxide–semiconductor (CMOS) image sensors (APS) with at least four transistors is presented. This model, based on the fundamental principles of electronic noise, may provide a reliable calibration of the gain conversion, which is one of the most important parameters of CMOS Image Sensor pixels. The new model revisits the "gold standard" ratio method of the measured variance of the shot noise to the mean value. The model assumes that shot noise is the dominant noise source of the pixel. The microscopic random time-dependent voltage of any shot noise electron charging the junction capacitance C of the sensing node may have either an exponential form or a step form. In the former case, a factor of 1/2 appears in the variance to the mean value, namely, q/2C is obtained. In the latter case, the well-established ratio q/C remains, where q is the electron charge. This correction factor affects the parameters that are based on the conversion gain, such as quantum efficiency and noise. The model has been successfully tested for advanced image sensors with six transistors fabricated in a commercial FAB, applying a CMOS 180 nm technology node with four metals. The stochastic modeling is corroborated by measurements of the quantum efficiency and simulations with advanced software (Lumerical). [ABSTRACT FROM AUTHOR]

This paper presents an investigation of the responsivity of a time-delay integration (TDI) charge-coupled device that employs anti-blooming clocking and uses a varying number of TDI stages. The influence of charge blooming caused by unused TDI stages in a TDI deployed selection scheme is shown experimentally, and an anti-blooming clocking mechanism is analyzed. The impact of blooming on sensor characteristics, such as the responsivity, the conversion gain, and the signal-to-noise ratio, is investigated. A comparison of the measurements with and without this anti-blooming clocking mechanism is presented and discussed in detail. [ABSTRACT FROM AUTHOR]

The dependency of RF performance on the local oscillator (LO) drive amplitude and DC bias is an important topic for RF mixers, especially as carrier frequency increases and generation of RF power thus becomes more complex. The prediction of mixer performance, without initial reliance on full circuit simulations, can provide important insights. In this work, mathematical models without the prior use of circuit simulation are developed, leading to a strategy to predict the conversion gain (Gc), DC current, 1 dB input compression point (IP1dB) and third order input intercept point (IIP3) for a SiGe bipolar transistor transconductance mixer. The models show the possibility to trade-off LO RF power and DC bias to achieve a desired performance. The concepts allow a prediction of the necessary DC bias required to support a chosen LO level and desired conversion transconductance or linearity. The mathematical model results, circuit simulation results, and measured hardware results from a 26 GHz prototype of a single-ended mixer are presented and compared, showing good agreement. In a lab-measured example, LO power reduction from +10 dBm to +3 dBm resulted in only a 1 dB reduction in conversion gain, by modifying the DC bias as predicted. The peak conversion gain predicted by the models is within 2.0 dB of circuit simulation and 2.5 dB of measured PCB results. The RMS error for predicted DC current, compared to circuit simulation, is 1.9 mA or better. [ABSTRACT FROM AUTHOR]

Global Navigation Satellite Systems (GNSS) is a satellite navigation system with global coverage. It refers to constellation of satellites that provide precise location and timing data to GNSS receivers via space signals. One of the critical components of the receiver is the mixer. The received Radio frequency (RF) signal after filtering and amplification is given to the mixer. The mixer at receiver downconverts to an Intermediate Frequency (IF) signal. This helps in the frequency band of interest to be moved down the spectrum so that the filter requirements and further processing on the signal become easy. The paper presents the designing of a Double Balanced (DB) mixer and an Inphase Quadrature (I/Q) mixer in 180 nm CMOS technology using Cadence Virtuoso SpectreRF. The mixers are to work in 1.8 V power supply, with 2.4 GHz RF signal and giving IF of 50 MHz. They are intended to have conversion gain > 5 dB, IP3 > -5 dBm, Noise figure< 20 dB. [ABSTRACT FROM AUTHOR]

A design of Cascode Low Noise Amplifier (CCLNA) circuit is proposed using standard 0.18 µm millimeter wave (mmW) CMOS technology. The proposed CMOS CCLNA circuit has achieved a maximum conversion gain of 17.4 dB, NF of dB and a power of 22.3 mW at mmW Ka band. The input and output reflection coefficients are well matched with less than – 10 dB at the Ka band frequency with good Voltage Standing Wave Ratio (VSWR). The reverse transmission coefficient S12 is less than – 12 dB, indicating that the LNA has improved isolation between input and output, the stability factor is greater than one for the amplifier realization. The SoC-based CCLNA design for circuit level examination with analytical equations also proved that the simulation outcomes were prone to the design suitable for nanoelectronic applications for an output power of 2 dBm, transition frequency (fT) of 64 GHz and maximum operation [ABSTRACT FROM AUTHOR]

This letter presents a 2.4-GHz high-gain, low-power, and low-noise complementary metal–oxide–semiconductor (CMOS) mixer using a current-reused bleeding amplifier. To reduce flicker noise, a resonant inductor and a current bleeding circuit are conventionally adopted, which also increases the conversion gain. In this letter, the conventional current bleeding circuit is modified to a current-reused bleeding amplifier to further increase the conversion gain, which also further decreases noise while consuming the same current, compared to the conventional circuit. Measurement results show a conversion gain of 14.64 dB, a noise figure of 9.17 dB at 10 kHz and 7.23 dB at 100 MHz, and an input third-order intercept point (IIP3) of −15.89 dBm. The proposed mixer has a power consumption of 3.82 mW from a 1.5-V supply voltage. It was fabricated by using a 65-nm CMOS process. [ABSTRACT FROM AUTHOR]

A low voltage, high linearity and gain withlow powerultra-wideband (UWB) CMOS mixer in the RF receiver is proposed. This mixer is designed for a standard of 802.11 for use in Wi-Fi communications. The linearization technique for the third-order transconductance (푔푚3) cancellation with modified derivativesuperposition (MDS) is utilized to enhance the linearity performance of the proposed mixer. The MDS technique employs anauxiliary PMOS transistor in parallel with the NMOS transistor in the lower tree (transconductance stage)for reducing the third-orderintermodulationdistortion (IMD3).Besides, a switched buffer stage and the active loads are employed to improve the conversion gain of the mixer. High gain and high linear mixer is designed by the MDS technique and switched buffer. The proposed mixer is analyzed, and simulated using a 0.18 μm CMOS TSMC process; The LNA achieves 9.1dB conversion gain, maximum input third-order intercept point (IIP3) of +15dBm, double side-band noise figure (DSB NF) of 15.6 dB. This module consumes 2.06 mW DC power from a 1.2 V power supply in the RF frequency of 10 GHz.

This article presents a 2.4-GHz 65-nm CMOS fully integrated nonlinear mixer-first receiver (RX) for the Internet of Things (IoT). To power efficiently improve the in-band interference resilience, we propose an inverter-based envelope-biased low noise amplifier (IBEB-LNA), which exploits dynamic biasing voltage generated from its input signal envelope to suppress the interferer in the amplitude domain. The achievable carrier-to-interference ratio (CIR) at ±3 and ±5 MHz is −45/−59 and −66/−65 dB, respectively. The proposed RX is suitable for ON–OFF keying (OOK) modulation with a 307-kb/s data rate, and the corresponding sensitivity is −83 dBm for keeping 0.1% bit error ratio (BER). The total power consumption is 2.05 mW. [ABSTRACT FROM AUTHOR]

The operational parameters of an alpha spectrometer equipped with a planar silicon semiconductor detector were characterized by measuring a mixed alpha source. The full width at half maximum (FWHM) decreased with increasing conversion gain (CG) and sample-to-detector distance (SDD) and was constant beyond an SDD of 21 mm. Although the FWHM was minimum at 4096 CG, peak-shape analysis showed that 1024 CG and 2048 CG are more appropriate than 4096 CG for alpha spectrum analysis. In practical measurement with SDD less than 5 mm, a sample thickness difference of 1 mm caused a relative error in detection efficiency of 11 %. [ABSTRACT FROM AUTHOR]

This paper presents an investigation of the responsivity of a time-delay integration (TDI) charge-coupled device that employs anti-blooming clocking and uses a varying number of TDI stages. The influence of charge blooming caused by unused TDI stages in a TDI deployed selection scheme is shown experimentally, and an anti-blooming clocking mechanism is analyzed. The impact of blooming on sensor characteristics, such as the responsivity, the conversion gain, and the signal-to-noise ratio, is investigated. A comparison of the measurements with and without this anti-blooming clocking mechanism is presented and discussed in detail.

A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal–oxide–semiconductor (CMOS) image sensors (APS) with at least four transistors is presented. This model, based on the fundamental principles of electronic noise, may provide a reliable calibration of the gain conversion, which is one of the most important parameters of CMOS Image Sensor pixels. The new model revisits the “gold standard” ratio method of the measured variance of the shot noise to the mean value. The model assumes that shot noise is the dominant noise source of the pixel. The microscopic random time-dependent voltage of any shot noise electron charging the junction capacitance C of the sensing node may have either an exponential form or a step form. In the former case, a factor of 1/2 appears in the variance to the mean value, namely, q/2C is obtained. In the latter case, the well-established ratio q/C remains, where q is the electron charge. This correction factor affects the parameters that are based on the conversion gain, such as quantum efficiency and noise. The model has been successfully tested for advanced image sensors with six transistors fabricated in a commercial FAB, applying a CMOS 180 nm technology node with four metals. The stochastic modeling is corroborated by measurements of the quantum efficiency and simulations with advanced software (Lumerical).

In this paper, an efficient photonics time-delayed mixer (PTDM) is proposed and demonstrated. It mainly consists of a dual-parallel Mach-Zehnder modulator (DPMZM) and a dispersion medium (DM). To eliminate the carrier component, the carrier-suppressed dual-sideband (CS-DSB) modulation is implemented without optical filters. Besides, the CS-DSB modulation is also the key to make the phase response is proportional to the converted frequency. Thanks to the controllable DC bias of the modulator, the power response of this PTDM is also tunable. Thus, this property also endows the PTDM able to resist the dispersion-induced power fading (DIPF) when considering the use of large dispersion medium. Experimental results verify the ability of wideband frequency up- and down-conversion. Moreover, a converted signal with linear phase-frequency response is also achieved, which implies the time delay capability. Time delay tuning is realized by altering the wavelength of the carrier with a stable power response. This structure is very compact and thus compresses the signal processing system volume, which is qualified to be integrated into a receiver/transmitter. [ABSTRACT FROM AUTHOR]

A low voltage, high linearity and gain with low power ultra-wideband (UWB) CMOS mixer in the RF receiver is proposed. This mixer is designed for a standard of 802.11 for use in Wi-Fi communications. The linearization technique for the third-order transconductance (gm3) cancellation with modified derivative superposition (MDS) is utilized to enhance the linearity performance of the proposed mixer. The MDS technique employs an auxiliary PMOS transistor in parallel with the NMOS transistor in the lower tree (transconductance stage) for reducing the third-order intermodulation distortion (IMD3). Besides, a switched buffer stage and the active loads are employed to improve the conversion gain of the mixer. High gain and high linear mixer is designed by the MDS technique and switched buffer. The proposed mixer is analyzed, and simulated using a 0.18 µm CMOS TSMC process; The LNA achieves 9.1dB conversion gain, maximum input third-order intercept point (IIP3) of +15dBm, double side-band noise figure (DSB NF) of 15.6 dB. This module consumes 2.06 mW DC power from a 1.2 V power supply in the RF frequency of 10 GHz. [ABSTRACT FROM AUTHOR]

A simple Cascaded double balanced mixer working at 2.4 GHz, for WLAN application was designed and using 90 nm CMOS technology. The proposed mixer incorprates minimum number of transistors in comparing with the gilbercell mixer. Staking LO stage just above the RF stage reducing the voltage headroom of mixer. Differential combination of RF stage has a common source node and the Differential combination of LO stage has common drain node. Differential combination for both RF and LO stage cancels the feed through error of higher order harmonic signals, improving the linearity of the mixer.Both RF and LO stage contributes to the overall transconductance of the mixer, improving the conversion gain of the mixer. The simulated response of the proposed mixer shows a Conversion gain of 12 dB, IIP3 point of 8.3 dBm and one dB compression point of 8.5 dBm. [ABSTRACT FROM AUTHOR]

This paper presents a down-conversion active mixer with improved performance for direct conversion receivers in wireless local area networks. The effect of negative admittance on the Gilbert cell mixer performance is investigated in terms of flicker noise, conversion gain, and linearity. The proposed negative admittance is implemented using a modified negative capacitance connected in parallel to a negative resistance, which exhibits a high degree of freedom to achieve high negative capacitance along with low negative resistance. The proposed mixer is designed and simulated using TSMC 0.18 µm CMOS technology in Cadence Spectre-RF at the input frequency of 2.4 GHz and intermediate frequency of 10 MHz. Post-layout simulation results show using the negative admittance can improve the flicker noise more than 16.7 dB at the frequency of 1 kHz. The proposed mixer exhibits a conversion gain of 19.3 dB and a flicker noise corner frequency of 5 kHz. The double-side band noise figure is 7.57 dB at the output frequency of 10 MHz, and the third-order intermodulation intercept point (IIP3) is − 7.5 dBm. The power dissipation is 13.6 mW from the power supply of 1.8 V. Moreover, the linearity of the proposed mixer can be enhanced by choosing the proper values for transconductance of switching quad and negative resistance so that it achieves the IIP3 of + 7.9 dBm with the conversion gain of 7.6 dB. [ABSTRACT FROM AUTHOR]

Designing an active mixer such as Gilbert mixer for applications at high frequencies is always a challenging task for the designers to deal with. In this article, a double-balanced mixer is proposed using 90-nm CMOS technology for the unlicensed spectrum of 7 GHz around 60 GHz. The design of a mixer for the same frequency range was studied by various authors using 130-nm CMOS technology, but for the purpose of low-power applications, a well-suited method is proposed. The proposed mixer showed very good response and isolation between various ports of mixing circuit. The isolation between RF and LO ports is very crucial for the up-conversion mixers, and in communication systems, the RF isolation will be a critical area to design successful transmitters. The double-balanced up-conversion mixer in this work achieved a better isolation of 40 dB within the range of 56–67 GHz and a conversion gain of 4 dB for the defined frequency range with a power consumption of only 18 mW. [ABSTRACT FROM AUTHOR]

Based on the structure of Gilbert，a 24 GHz up-conversion mixer was designed with three-piece balun circuit on-chip. Using the gm/I method to coordinate the transistor size to obtain better conversion gain, isolation degree and circuit dissipation power. The circuit implementation is adopted by the xiamen san-0.5 μm PHEMT process, 5 V voltage power supply, and the conversion gain is 9 dBm when this LO power is 0 dBm. When work at 24 GHz band, 1 dB compressed point is -20 dBm, the maximum output power of the mixer is -10 dBm, RF output port and the LO port isolation degree is more than 32 dB, the whole circuit DC power consumption of 40 MW，chip area is 1 mm ×1.3 mm.

A 60–113 GHz down-conversion mixer in 90 nm CMOS is demonstrated. The mixer adopts an RL core IF load, which is based on the series of a peaking inductor (L) and a parallel combination of the cross-coupled PMOS transistors (CCPT) and the diode-connected NMOS transistors (DCNT), i.e. L-CCPT–DCNT-based core IF load. Conversion gain (CG) can be significantly enhanced due to the increase of load impedance. The bandwidth can be improved due to the inductive peaking effect of the RL core IF load. The mixer consumes 3.2 mW and achieves RF-port input reflection coefficient of − 10 to − 31.2 dB for 82.8–97.2 GHz. The mixer attains CG of 16.8 ± 1.5 dB for 60–113 GHz. The corresponding 3 dB CG bandwidth is 53 GHz. Moreover, for 70–100 GHz, the mixer achieves CG of 17.4–18.3 dB and LO-RF isolation of 39.2–54.4 dB, one of the best CG and LO-RF isolation results ever reported for down-conversion mixers around 77 GHz or 94 GHz. These prominent results indicate that the down-conversion mixer is suitable for 77 GHz automobile radar and 94 GHz imaging radar systems. [ABSTRACT FROM AUTHOR]

This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device‐level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back‐side‐illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e−/µm2 equilibrium full‐well capacity. The conversion gain is 200 μV/e− and the signal‐to‐noise ratio is 37 dB. [ABSTRACT FROM AUTHOR]

This letter introduces a 5-transistors (5T) implementation of CMOS Image Sensors (CIS) pixels enabling the combination of deep sub-electron noise performance with wide dynamic range (DR). The 5T pixel presents a new technique to reduce the sense node capacitance without any process refinements or voltage level increase and features adjustable conversion gain (CG) to enable wide dynamic imaging. The implementation of the proposed 5T pixel in a standard 180nm CIS process demonstrates the combination of a measured high CG of 250 μ V/e− and low CG of 115 μ V/e−with a saturation level of about 6500 e− offering photo-electron counting capability without c0]ompromising the DR and readout speed. [ABSTRACT FROM AUTHOR]

This letter presents the integration of multiple active devices output port directly with the antenna for simultaneous active frequency multiplication and radiation. This eliminates the circuitry losses at the multiplied output frequency, which points to a significant advantage of the proposed unified integration space in addition to size reduction. Furthermore, active devices are configured in parallel to enhance the power handling capability of this unified module. Initially, the rectangular patch antenna is analyzed and presented as a potential design space for simultaneously accomplishing efficient radiation, output matching, and fundamental frequency suppression. Subsequently, a procedure to achieve the circuit–antenna unification is described through a prototype operating as a 14–28 GHz frequency doubler using two paralleled transistors. The fabricated prototype realizes the maximum conversion gain of 9 dB and fundamental frequency suppression of 14 dB from measurements. [ABSTRACT FROM AUTHOR]