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This paper proposes a digital logic circuit in the source driver for OLEDoS micro display which uses a novel data signal tree structure with clock gating logic to reduce power consumption. The proposed structure for 4096×4096 (4K) 144 Hz micro displays was verified using a CMOS 110 nm process. The power consumption was reduced by 69.6 % compared to the conventional data signal tree structure, enabling a low‐power design. [ABSTRACT FROM AUTHOR]

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed. [ABSTRACT FROM AUTHOR]

The diminution of power dissipation has recently become a paramount concern in contemporary VLSI design. Owing to the shrinking chip size and the gradual development of several micro-electronic reliabilities, low-power (LP) system design has become the utmost priority. Hence, this paper proposes an effective power reduction method that combines clock gating (CG) and a multi-bit flip flop (MBFF) approach. Initially, the CG and MBFF schemes were implemented separately in two standard Johnson counters, one involving a true single-phase clock (TSPC) LP D flip flop (DFF) with five transistors and the other involving a standard DFF with 32 transistors. Furthermore, a combined CG-MBFF scheme is proposed and implemented in 4-bit and 16-bit Johnson counters to illustrate the superiority of the proposed CG-MBFF scheme in terms of power diminution over the CG and MBFF methods when implemented separately. Additionally, an LP application employing a 4-bit Johnson counter was implemented with and without the proposed scheme. [ABSTRACT FROM AUTHOR]

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements. [ABSTRACT FROM AUTHOR]

Power management is becoming important aspect as the size of transistor is shrinking. For processor design, Reduced Instruction Set Computer (RISC) architecture is preferable as compared to Complex Instruction Set Computer (CISC) architecture because of its simplicity and availability. To design the low power RISC processor, there are a few techniques that had been used earlier, such as a) pipelining and b) Common Power Format language to generate power intent of RISC processor design. In the present work, for designing a 16-bit RISC processor with low power consumption, a multi-voltage design technique has been used. In this technique, different supply voltages are provided to different blocks of the design. This technique is implemented with the help of Unified Power Format (UPF). Further, various operations such as ADD, SUB, INVERT, AND, OR, Right Shift, Left Shift, and Less Than are verified on modelsim for the designed 16-bit RISC processor. [ABSTRACT FROM AUTHOR]

In several instances, the electronic appliances used in the Internet-on-Things (IoT) systems fail to perform according to their full capability. One of the main reasons pertaining to this issue is the IoT devices are usually controlled by clock-driven application-specific processors enabling them to communicate over the common network and accomplish given tasks. But these processor chips are mostly prone to supply noise and adversely affect the performance of the IoT systems. In this article, the problem of on-chip power supply noise (PSN) is discussed and how clock gating (CG) is a potential candidate to mitigate $$i(t)$$ i (t) and $${{di(t)} \over {dt}}$$ d i (t) d t which are the dominant factors of instigating the overall on-chip PSN. Majority of the CG schemes are examined and it is seen that LCT-CG implementation can potentially commit 84.44% less PSN compared to the non-gated peer as well as 55.21%, 54.45% and 74.47% lesser than the other CG schemes like LB-CG, NC2MOS-CG and DG-CG, respectively. In addition, it is also observed that with the inclusion of LCT-CG in IBM® i650 A-Z80 processor chip, the system lifetime is improved by 17.70% compared to the non-gated peer. In addition, the industry standard of implementing CG schemes in integrated circuit (IC) chips is reviewed and it is found quite different from the traditional methods. Therefore, an extensive study is performed to portray the possibility of LCT-CG can become an industry standard in the forthcoming days. [ABSTRACT FROM AUTHOR]

Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed. [ABSTRACT FROM AUTHOR]

Most of the system-level designs contain sequential circuits. Power optimization of these circuits at many levels is required to build a portable device with a long battery life. A dynamic clock gating technique was used in this work to reduce the power and temperature of a 16-bit counter. The simulation was performed on cadence SCL 180 nm technology, for a supply voltage of 1.8 V at a frequency of 500 MHz. With the proposed approach, a 77.16% power reduction was achieved at the cost of 14.83% in area overhead. Moreover, the layout of the circuits was also designed in the Innovus tool to obtain a more accurate silicon area and gate count. The Innovus output files ".flp file" and ".pptrace file" were used as inputs to the HotSpot tool for determining the absolute temperature of the integrated circuits (ICs). The obtained temperature results were compared with the ordinary 16-bit counter, and it was found that the proposed approach was able to reduce temperature by 14.34%.

Comprehensive neural network applications led to the customization of a scheme to accelerate the computation on ASIC implementation. Hence, the determination of activation function in a neural network is an indispensable requisite. However, the specific design architecture of an activation function in a digital network encounters several difficulties as these activation functions demand additional hardware resources due to their non-linearity. This paper proposed an efficient hyperbolic tangent (tanh) function, wholly based on stochastic Computing methodology. The Hyperbolic tangent implementation is backed by the clock gating technique to curtail the dynamic power dissipation. The results are derived by implementing two different clock gating techniques on the proposed hardware. In this work, the proposed clock gating-based stochastic design for the implementation of activation function is efficient in terms of performance parameters such as area, power, and delay with negligible accuracy loss. MNIST dataset has been used for checking accuracy on LeNeT benchmark architecture. Furthermore, post-synthesis results show that the proposed clock gating design area is reduced by ≈ 70.62 % , power is reduced by ≈ 58.19 % , and delay is reduced by ≈ 98.87 % compared to the state of the art. [ABSTRACT FROM AUTHOR]

In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously. [ABSTRACT FROM AUTHOR]

A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It is used to monitor the serial data flow and to avoid mismatch conditions. In general, the dual-ported memory cell array suffers from dynamic power dissipation. In this research article, a 128 x 128-bit Synchronous First-In-First-Out (FIFO) buffer is designed for dual-ported memory cell array with pipeline architecture using clock gating technique, which reduces power dissipation significantly. The FIFO-based dual-ported memory cell array will store a large amount of data and minimize the clock skew. A circular FIFO used in dual-ported memory is organized in a circular queue fashion with two pointers for write and read. Conventional FIFO designs use more power and hardware area on the silicon chip. The FIFO-based pipelining and clock gating approach will improve throughput while reducing dynamic power. The proposed FIFO design is simulated and implemented using the CadenceEncounter tool using 180nm and 45nm Technology. The parameters power consumption, cell utilization, and clock frequency have been analyzed. The synchronous FIFO design reduces the area by 70.3%, power dissipation by 10.6%, and operates at clock frequency up to 322 MHz.

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

With the emerging of Internet of Things (IoT) industry, applications like smart power plugs, security ID tags, home automation and wearable electronic devices all make the demand for low-power WiFi chips impendency. In this paper, a low-power 2.4 GHz 802.11b/g/n WiFi system-on-chip (SoC) is designed and implemented with 40-nm CMOS process, with area of 8.1 mm2. The low-power SoC integrates 32-bit microcontroller, 802.11b/g/n WiFi baseband, 2.4 GHz RF transceiver, ample memory space, ADC, 6-channel PWM, flexible I/O interfaces, multi-stage power management module, etc. It has several sleep modes with extremely low leakage current as 0.8 mA/12 µA in light/deep sleep mode and 0.4 µA in shutdown mode to reduce the power consumption. High performance is demonstrated, including Pout (−28 dB/-30 dB EVM) of 20.1 dBm/19.1 dBm and RX sensitivity of −76 dBm/-74 dBm meanwhile the total current of 148.5 mA/146.5 mA (TX) for 54 Mbps OFDM/HT20 MCS7. [ABSTRACT FROM AUTHOR]

The demand for low-power digital systems is increasing daily, especially for the multi-core design on SoC. Different IP cores of the existing multi-core memory controller need to communicate to achieve specific tasks on the same die. The system clock toggles each synchronous part of the multi-core memory controller system during the communication among different IPs. However, some synchronous parts of the multi-core memory controller system are not used at all the system clock time, leading to more dynamic power dissipation. In this paper, the intelligent clock gating (ICG) optimization technique is used to avoid unnecessary switching activity for different synchronous parts of the multi-core memory controller system, decrease the dynamic power, and improve the entire performance of the multi-core memory controller system. The dynamic power improvement for different multi-core memory controller systems is 26.32%, 30.43%, 33.33%, and 27.30% compared with the existing systems. The Multi-core memory controllers without/ with intelligent clock gating technique are successfully synthesized and implemented using the Vivado tool 2018.1 and FPGA ZedBoard (xc7z020clg484-l).

Based on equal precision frequency measurement and pulse counting technique, a multi-period synchronous frequency measurement method is proposed in this paper. A programmed cymometer is designed with a full frequency band with equal precision measurement and improved measurement accuracy. In addition to adopting a low-power gate-control clock technique, the strong stability of our design is also carried out through the filtering of interference signals. Finally, the designed circuit is implemented with FPGA. The experimental results show that the static power consumption of the programmable frequency meter testing platform designed after continuous operation for 100 h is only 0.56 W, and the input impedance is 1 M Ω/40 pF. At the same time, the errors of frequency, cycle measurement, duty cycle measurement, and time interval are within a reasonable range. In addition, the measurement accuracy requirements for various indicators can also be met at a maximum frequency of 100 MHz. Therefore, this work can provide a feasible design method for low-power consumption electrical systems that are easy to replicate. [ABSTRACT FROM AUTHOR]

A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It is used to monitor the serial data flow and to avoid mismatch conditions. In general, the dual-ported memory cell array suffers from dynamic power dissipation. In this research article, a 128 x 128-bit Synchronous First-In-First-Out (FIFO) buffer is designed for dual-ported memory cell array with pipeline architecture using clock gating technique, which reduces power dissipation significantly. The FIFO-based dual-ported memory cell array will store a large amount of data and minimize the clock skew. A circular FIFO used in dual-ported memory is organized in a circular queue fashion with two pointers for write and read. Conventional FIFO designs use more power and hardware area on the silicon chip. The FIFO-based pipelining and clock gating approach will improve throughput while reducing dynamic power. The proposed FIFO design is simulated and implemented using the Cadence-Encounter tool using 180nm and 45nm Technology. The parameters power consumption, cell utilization, and clock frequency have been analyzed. The synchronous FIFO design reduces the area by 70.3%, power dissipation by 10.6%, and operates at clock frequency up to 322 MHz. [ABSTRACT FROM AUTHOR]

This paper proposed a domino logic namely "Gated Clock and Revised Keeper (GCRK)" domino logic 16 nm CMOS technology. The proposed domino logic has a revised keeper circuitry to reduce the power consumption in the circuit. A multiplexer is added in the GCRK design for gating the clock signal during sleep mode while maintaining the state of the domino logic. Total power consumption, delay and power-delay-product (PDP) of 16-bit OR gate GCRK domino logic and existing domino logic designs are calculated and compared. The existing domino logic techniques considered in this paper are – Leakage tolerant multiphase keeper domino logic (LTMK), high-speed domino logic (HSD), clock delayed sleep mode domino logic (CDSMD), grounded pmos keeper domino logic (GPKD) and foot driven stack transistor domino logic (FDSTDL). The proposed design shows significant improvement in PDP with respect to the existing designs. The PDP of proposed design (LTMK) is improved to 99.98%, 88.75%, 11.54% and 37.11% as compared to LTMK, HSD, GPDK and FDSTDL designs, respectively. Noise analysis and Monte Carlo simulation show that the proposed design is immune to noise and reliable under different parametric variations. [ABSTRACT FROM AUTHOR]

A new method for the generation of pseudo-random bits, based on a coupled-linear congruential generator (CLCG) and two multistage variable seeds linear feedback shift registers (LFSRs) is presented. The proposed algorithm dynamically changes the value of the seeds of each linear congruential generator (LCG) by utilizing the multistage variable seeds LFSR. The proposed approach exhibits several advantages over the pseudo-random bit generator (PRBG) methods presented in the literature. It provides low hardware complexity and high-security strength while maintaining the minimum critical path delay. Moreover, this design generates the maximum length of pseudo-random bit sequence with uniform clock latency. Furthermore, to improve the critical path delay, one more architecture of PRBG is proposed in this work. It is based on the combination of coupled modified-LCG with two variable seeds multistage LFSRs. The modified LCG block is designed by the two-operand modulo adder and XOR gate, rather than the three-operands modulo adder and shifting operation, while it maintains the same security strength. The clock gating network (CGN) is also used in this work to minimize the dynamic power dissipation of the overall PRBG architecture. The proposed architectures are implemented using Verilog HDL and further prototyped on commercially available field-programmable gate array (FPGA) devices Virtex-5 and Virtex-7. The realization of the proposed architecture in this FPGA device accomplishes an improved speed of PRBG, which consumes low power with high randomness compared to existing techniques. The generated binary sequence from the proposed algorithms has been verified for randomness tests using NIST statistical test suites. [ABSTRACT FROM AUTHOR]

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and Q ¯ . The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give minimal power delay product (PDP) which is 35.7 × 10− 18 J and 29.6 × 10− 18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40∘C to 120 ∘C. The performance of all designs has been validated by functionality testing with variation in load cpacitance, diameter, number of tubes and pitch respectively. [ABSTRACT FROM AUTHOR]

In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8x8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to the said architecture can be somewhere between -(7.96872)10 to + (7.96872)10. The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as "block enabling" and "clock gating" are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors. [ABSTRACT FROM AUTHOR]

Cryptography is very important now-a-days for data security and integrity as the ecommerce and internet applications has increased. But, it has least importance in many cases because of extra memory and other requirements needed for the implementation. The main aim of this work is to implement Advanced Encryption Standard (AES) Encryption using Verilog. To protect data like electronics, cryptographic algorithms are used. The digital information can be encrypted and decrypted by the block cipher of AES algorithm. It can be implemented with the key length 128, 192, 256 bits. Each round of encryption associated with delay can be reduced by AES parallel design. For storing plain text, keys, and intermediate data, we construct two specific register banks, Key-Register and State-Register. Shift-Rows are inserted into the State-Register to save space. We build an efficient 8-bit block for Mix-Columns with four internal registers that take 8-bit and send out 8-bit to adapt the Mix-Column to an 8-bit data stream. For the key expansion and encryption phases, shared optimized Sub-Bytes are also used. We consolidate and simplify various Sub-Bytes to make them more efficient. The clock gating method is used in the design to decrease power consumption. This study provides a 256-bit AES architecture based on Image Cryptography. This design is built-in Verilog HDL on an FPGA XC3S 200 TQ-144, simulated using Modalism 6.4 c, and synthesized with the Xilinx tool. [ABSTRACT FROM AUTHOR]

Based on equal precision frequency measurement and pulse counting technique, a multi-period synchronous frequency measurement method is proposed in this paper. A programmed cymometer is designed with a full frequency band with equal precision measurement and improved measurement accuracy. In addition to adopting a low-power gate-control clock technique, the strong stability of our design is also carried out through the filtering of interference signals. Finally, the designed circuit is implemented with FPGA. The experimental results show that the static power consumption of the programmable frequency meter testing platform designed after continuous operation for 100 h is only 0.56 W, and the input impedance is 1 M Ω/40 pF. At the same time, the errors of frequency, cycle measurement, duty cycle measurement, and time interval are within a reasonable range. In addition, the measurement accuracy requirements for various indicators can also be met at a maximum frequency of 100 MHz. Therefore, this work can provide a feasible design method for low-power consumption electrical systems that are easy to replicate.

The paper concerns research on electronics-embedded safety systems. The authors focus on the optimization of the energy consumed by multitasking real-time systems. A new flexible and reconfigurable multi-core architecture based on pipeline processing is proposed. The presented solution uses thread-interleaving mechanisms that allow avoiding hazards and minimizing unpredictability. The proposed architecture is compared with the classical solutions consisting of many processors and based on the scheme using one processor per single task. Energy-efficient task mapping is analyzed and a design methodology, based on minimizing the number of active and utilized resources, is proposed. New techniques for energy optimization are proposed, mainly, clock gating and switching-resources blocking. The authors investigate two main factors of the system: setting the processing frequency, and gating techniques; the latter are used under the assumption that the system meets the requirements of time predictability. The energy consumed by the system is reduced. Theoretical considerations are verified by many experiments of the system's implementation in an FPGA structure. The set of tasks tested consists of programs that implement Mälardalen WCET benchmark algorithms. The tested scenarios are divided into periodic and non-periodic execution schemes. The obtained results show that it is possible to reduce the dynamic energy consumed by real-time applications' meeting their other requirements. [ABSTRACT FROM AUTHOR]

Due to semiconductor technology scaling, integrated circuits have become more sensitive to soft errors. To effectively tolerate multi-node-upsets caused by soft errors and reduce the power dissipation and delay of a latch, this paper proposes a novel triple-node-upset (TNU) self-recoverable latch design, namely, a highly robust TNU self-recoverable (HTNURE) latch, with many redundant nodes and cyclic storage based on 32-nm CMOS technology. The proposed latch uses the Muller C-element as a basic module and can recover all nodes after a TNU occurs. It has low power dissipation and delay due to the application of clock gating technology and high-speed transmission path technology. The proposed latch design was verified by simulations, and simulation results validate its advantages of low power and delay, and high robustness. In addition, compared with the state-of-the-art TNU-tolerant latches, the proposed latch reduces power dissipation, transmission delay, and power-delay-product by approximately 52%, 25%, and 34%, respectively, with a roughly 17% increase in the number of transistors. Furthermore, the proposed latch is the most cost-effective compared with the TNU-self-recoverable latches, and has less or equivalent sensitivity to the process, voltage, and temperature variation compared with the reference latches.

Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-based operation and vector-based operation, respectively. The dual image watermarking architecture data path consists of a 13-stage pipeline. Pipeline and parallelism mechanisms are used to improve throughput. To improve the performance in discrete cosine transform operations at the frequency domain, the shift-add technique replaces the conventional multipliers. The clock gating technique is employed to reduce the power by preventing unnecessary switching in a path. Hardware implementation of the algorithm is tested in Intel Cyclone FPGA with the device of EP4CGX22CF19C6, with which the throughput achieved is 1.27 Gbits/s with a total area utilization of 35 digital signal processing (DSP) blocks, 378 look-up tables (LUTs) and 486 registers. [ABSTRACT FROM AUTHOR]

Modern deep neural network (DNN) applications demand a remarkable processing throughput usually unmet by traditional Von Neumann architectures. Consequently, hardware accelerators, comprising a sea of multiplier-and-accumulate (MAC) units, have recently gained prominence in accelerating DNN inference engine. For example, tensor processing units (TPUs) account for a lion’s share of Google’s datacenter inference operations. The proliferation of real-time DNN predictions is accompanied by a tremendous energy budget. In quest of trimming the energy footprint of DNN accelerators, we propose Energy eFFicient and errOr Resilient TPU (EFFORT)—an energy optimized, yet high-performance TPU architecture, operating at the near-threshold computing (NTC) region. EFFORT promotes a better-than-worst case design by operating the NTC TPU at a substantially high frequency while keeping the voltage at the NTC nominal value. In order to tackle the timing errors due to such aggressive operation, we employ an opportunistic error mitigation strategy. In addition, we implement an in situ clock gating architecture, drastically reducing the MACs’ dynamic power consumption. Compared to a cutting-edge error mitigation technique for TPUs, EFFORT enables up to $2.5\times $ better performance at NTC with only 4% average accuracy drop across six out of eight DNN benchmarks. [ABSTRACT FROM AUTHOR]