Back to Search
Start Over
Power reduction using Unified techniques in Switch-tail Ring counter for sequential circuits.
- Source :
- Analog Integrated Circuits & Signal Processing; Apr2024, Vol. 119 Issue 1, p131-149, 19p
- Publication Year :
- 2024
-
Abstract
- The diminution of power dissipation has recently become a paramount concern in contemporary VLSI design. Owing to the shrinking chip size and the gradual development of several micro-electronic reliabilities, low-power (LP) system design has become the utmost priority. Hence, this paper proposes an effective power reduction method that combines clock gating (CG) and a multi-bit flip flop (MBFF) approach. Initially, the CG and MBFF schemes were implemented separately in two standard Johnson counters, one involving a true single-phase clock (TSPC) LP D flip flop (DFF) with five transistors and the other involving a standard DFF with 32 transistors. Furthermore, a combined CG-MBFF scheme is proposed and implemented in 4-bit and 16-bit Johnson counters to illustrate the superiority of the proposed CG-MBFF scheme in terms of power diminution over the CG and MBFF methods when implemented separately. Additionally, an LP application employing a 4-bit Johnson counter was implemented with and without the proposed scheme. [ABSTRACT FROM AUTHOR]
- Subjects :
- SEQUENTIAL circuits
SYSTEMS design
VERY large scale circuit integration
TRANSISTORS
Subjects
Details
- Language :
- English
- ISSN :
- 09251030
- Volume :
- 119
- Issue :
- 1
- Database :
- Complementary Index
- Journal :
- Analog Integrated Circuits & Signal Processing
- Publication Type :
- Academic Journal
- Accession number :
- 176251229
- Full Text :
- https://doi.org/10.1007/s10470-023-02226-z