Search

In this letter, 5 nm-thick HZO ultra-thin ferroelectric capacitors with excellent remanent polarization ( $\text{P}_{\mathrm {r}}$ ) and reliability are presented. The TiN/HZO/TiN metal-ferroelectric-metal (MFM) capacitor stack was deposited consecutively in the same atomic layer deposition (ALD) system without breaking the vacuum (i.e. “ in-situ ” like) to improve the interface quality between TiN electrodes and HZO ferroelectric layer. The samples show high $\text{P}_{\mathrm {r}}$ of $20.5~\mu \text{C}$ /cm2 (i.e. 2P $_{\mathrm {r}}= 41\,\,\mu \text{C}$ /cm2) under driving voltage of 3 V with low coercive voltage of approximately 0.6 V. The robustness of the MFM capacitor was presented by the outstanding endurance characteristics for keeping 2P $_{\mathrm {r}}$ value higher than $20~\mu \text{C}$ /cm2 after 1010 cycles at a high electric field of 5 MV/cm without breakdown, though the $\text{P}_{\mathrm {r}}$ values gradually degrade with cycles at low field (i.e. 2.4 MV/cm). The highly robust endurance characteristics of the 5nm-thick HZO MFM capacitor indicate the good interface quality achieved in this study.

In this work, a ferroelectric tunnel thin-film transistor (FeT-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric HfZrOx gate dielectric is demonstrated with analog memory characteristics for the application of synaptic devices. The FeT-TFT exhibits a much lower conduction current of ∼0.032 times in transfer characteristics and maximum conductance (Gd) of ∼ 0.14 to 0.2 times in potentiation and depression operation than the FeTFT due to FeT-TFT’s carrier transport mechanism: interband tunneling. This work employed pulse widths of 75, 150, and 300 ns to modulate Gd, and it was found that using a pulse width of 75 ns could achieve low asymmetry ∼ 1 and high Gd ratio ∼ 20.63 under the consideration of operation speed. When the pulse time is increased, the potentiation and depression voltages can be significantly decreased to maintain the low asymmetry, but the Gd ratio is also reduced. In addition, the endurance characteristic of poly-Si FeT-TFT is found to be strongly related to the degradation effect of subthreshold swing due to the dynamic stress effect in the endurance measurement. This result reveals that the reliability of ferroelectric devices is not only owing to the degradation of the remanent polarization.

In this paper, we achieved excellent variation control, endurance enhancement, and leakage reduction in zirconium (Zr)-doped hafnium oxide (Hf1–xZrxO2) based ferroelectric films by the germination ...

According to quantum transport simulations, source-to-drain tunneling (SDT) has been recognized as the main cause leading to subthreshold swing ( SS ) saturation and degradation of short-channel MOSFETs at cryogenic temperatures. Generally, at a given low temperature, the steeper constant SS of thermionic currents may be overwhelmed by less-steep SDT currents at lower gate bias, degrading the average SS . Our simulations show that the SS of SDT currents is insensitive to temperatures for a MOSFET with a given channel length, accounting for SS saturation as lowering temperature. This work reveals the key points differentiating the possible reasons (interface traps, band tail and SDT) of SS saturation at cryogenic temperatures. We also study the impacts of carrier effective masses, gate-SD underlapping and a tunneling barrier at the source junction on SS saturation. SDT may pose a potential challenge and limit for scaling cryogenic CMOS of a quantum processor.

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density ( ${D}_{\textit {it}}$ ) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO.

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

In this article, we investigate the four-level random telegraph noise (RTN) characteristics of a gate-all-around (GAA) nanowire (NW) transistor. The RTN-testing devices were fabricated with the sidewall spacer etching technique. The effective channel length and width are approximately 150 and 30 nm, respectively. By decoupling the four-level RTN, we are able to extract the time constants associated with the two traps. Circle-shaped approximations are used to mimic the triangular NW for evaluating the depths of the traps. The extracted depths of the two traps are very close to each other, which is consistent with the time-evolution measured results. We've also explored the probabilities of transitions between two specific current levels in the RTN characteristics, as well as the relative trapping/de-trapping frequencies.

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V PRG/V ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V PRG shows the imprint effect that the V TH in either PRG- or ERS-state reveals a decreasing trend. When the V ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.

The technology for scraped surface detection remains experimental. It is mainly performed visually by experienced technicians, which is neither objective nor standardized. Since the scraping technique is the key to the accuracy and the performance of the machine, a method to determine the characteristics of the scraping surface in a quick, objective way is proposed, in order to ensure the quality of scraping. The scraping surface is photographed using a smartphone, and an Android application is developed using a Java image processing algorithm. A square inch of image is then captured on the screen, the RGB image is isolated, and its histogram is read. Using a watershed algorithm, the background image is calculated from the boundary, and then binary, filter and morphological image processing algorithms are used. If the light is uniform, a split binary technique is used. The scraping appearance is then calculated and analyzed in points per inch (PPI) and percentage of points (POP). The experimental results indicated that the total area for recognition was approximately 1-in2; PPI = 13; and POP = 30.9%, and recognition time was less than 1 sec. The experimental analysis results in this study were compared to those of two scraping experts; the two errors were both lower than 5%.

Effective doping techniques that precisely and locally control the conductivity and carrier polarity, i.e., electron (n-type) or hole (p-type), play a vital role in the remarkable success of Si-based technology and thus are critical for developing useful devices based on two-dimensional layered transition-metal dichalcogenides (TMDs). In contrast to the previous approaches based on either chemical doping or phase transition that requires complex chemicals or a high thermal budget and shows limited tunability and reliability, we propose a simple yet effective electron-beam irradiation (EBI) technique as an alternative for facilitating polarity transformation and transport modulation in selected regions. The EBI process may generate a precise amount of native chalcogen defects in both MoS2 and MoTe2 by controlling the EBI dosage. First-principles simulations support that the presence of native chalcogen vacancies may substantially reduce the band gaps of TMDs. In MoTe2, the progressive evolution of p-type c...

HfO2-based ferroelectric (FE–HfO2) is a promising material for low-power and high-capacity memory technology. Since thinner ferroelectric films are required for low voltage operation, the impact of film thickness on the switching kinetics of FE–HfO2 needs to be studied in detail. In this paper, metal/ferroelectric/metal capacitors are fabricated with several thicknesses of HfZrO2 (HZO) films and characterized to study the switching kinetics based on the nucleation limited switching (NLS) model. Thinner HZO capacitors show slower polarization switching and asymmetry in program and erase operation, although low-frequency polarization charge density is nearly the same for all thicknesses. Slow switching is due to the large variability of the activation field of FE domains and grain boundaries among small FE grains. The asymmetry is caused by the asymmetric interface property at the top and bottom interfaces. High-resolution TEM and electron diffraction mapping methods provide physical evidence for the above discussions.

Ferroelectric HfO2-doped compounds, which are well-known CMOS compatible dielectric materials, have the promising applications in memory, logic and neuromorphic devices [1]. Based on typical metal ferroelectric insulator semiconductor (MFIS) capacitor structure with the sub-5nm ferroelectric layer, the ferroelectric characterization becomes the challenge since the presence of tunneling leakage or screening effects from surface charge traps dramatically reduce the signal to noise ratio. Since the devices obtain a weak signal from polarization (P) itself, this leads to the complicated evaluation of ferroelectric properties of such ultrathin layers [2]–[3]. In this study, we fabricated 5 nm and 2 nm Hf0.5Zr0.5O2 (HZO) MFIS capacitors and demonstrate alternative vacuum-based piezoresponse force microscopy (PFM) characterization, which is still enables to see P-response in ultrathin films due to increased quality factor of the tip-surface resonance. Electrical measurements such as polarization-voltage (P-V) and capacitance-voltage (C-V) characterristics gives additional information about remnant and saturated polarizations: Pr and Ps, respectively.

The nanowire transistors on silicon-on-insulator (SOI) substrate embedded with ferroelectric hafnium-zirconium-oxide (HfZrO2) are elaborately probed when the devices are illuminated with the ultraviolet (UV) laser. The basic functionality of the ferroelectric nanowire transistor can be verified by monitoring the drain current hysteresis during the bidirectional gate voltage scan. Therefore, this study mainly analyzes and summarizes the electrical response of the device to ultraviolet (UV) irradiation; the main emphases will be placed on the rotational direction of the hysteresis window and the width of the hysteresis window when components of different dimensions are compared with one another. To administer the comparisons impartially, the pertinent surface-to-volume ratios of these nanowire transistors are used as the gauging parameters. As the device measurements would demonstrate, Hysteresis rotating in a clockwise direction is attributed to the oxide layer defects, while the counterclockwise direction is induced by the ferroelectric effect. Needless to say, the quality of the device itself is still contingent upon the gate oxide robustness and the quality of its adjacent interfaces. And last but not least, the threshold voltage shift is also used as an indicator to illuminate the impact of changing polarization effect on the nanoscale devices. Through the effective modulation of the hysteretic window by irradiating the nanowire FETs with a UV laser, we believe many unique applications involving the optical modulation and photodetection that are commonly found in silicon photonics can be realized.

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

This paper reports detailed analysis on switching dynamics and device variability over a wide range of temperatures for deeply scaled (40nm gate length) tri-gate ferroelectric FETs with 10nm HZO fabricated using gate first process on SOI wafers. Our experimental results manifest, 99% ferroelectric switching at room temperature and at 233K. A memory window over 5V and strong gate length dependence of memory window is observed. Highly linear and symmetric multilevel switching characteristics makes our ferroelectric FETs suitable for neuromorphic applications, as demonstrated with neural network online training simulations.

In this paper, a novel gate-all-around (GAA) junctionless (JL) nanowire (NW) transistor with dual gate was proposed, fabricated and characterized. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end.

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS

In this work, the synaptic characteristics together with 5 bits (32 states) operation based on polycrystalline-silicon (poly-Si) ferroelectric thin-film transistor (FeTFT) with HfZrO x gate dielectric are demonstrated for the first time. A 1.2 V threshold voltage shift of memory window is obtained. The impacts of pulse time on the potentiation and depression states are studied by a modulation scheme with incremental pulse voltages. The potentiation and depression rates of the conductance (G d) states of FeTFTs are found to be asymmetric and become more severe when increasing the pulse time. In order to realize high recognition rate and accuracy of neuromorphic computing, low asymmetric nonlinearity of potentiation ( α p ) and depression ( α d ) of poly-Si FeTFTs can be achieved with the reduction of operation voltage. Low asymmetry α p − α d = 0.71 and high G d ratio ∼40 of FeTFTs are obtained based on the small pulse time of 50 ns and low average potentiation/depression voltages of 2.63/–2.69 V. When the pulse time is increased from 50 to 150 ns, the average potentiation/depression voltages can be further reduced to ∼1.59/–1.69 V for low asymmetry α p − α d = 0.25 due to the enhanced G d potentiation and depression rates, and the G d ratio is also reduced to 9.96 with the reduction of potentiation/depression voltages. The small pulse time and potentiation/depression voltages of FeTFTs are responsible for the polarization switching of the ferroelectric layer following the minor operation-loop. Compared to the depression state, it leads to more stable retention and endurance behavior of the potentiation state due to the different depolarization electric fields.

Two-dimensional semiconductors, such as MoS2 are known to be highly susceptible to diverse molecular adsorbates on the surface during fabrication, which could adversely affect device performance. To ensure high device yield, uniformity and performance, the semiconductor industry has long employed wet chemical cleaning strategies to remove undesirable surface contaminations, adsorbates, and native oxides from the surface of Si wafers. A similarly effective surface cleaning technique for two-dimensional materials has not yet been fully developed. In this study, we propose a wet chemical cleaning strategy for MoS2 by using N-methyl-2-pyrrolidone. The cleaning process not only preserves the intrinsic properties of monolayer MoS2, but also significantly improves the performance of monolayer MoS2 field-effect-transistors. Superior device on current of 12 μA·μm–1 for a channel length of 400 nm, contact resistance of 15 kΩ·μm, field-effect mobility of 15.5 cm2·V–1·s–1, and the average on–off current ratio of 108 were successfully demonstrated

This paper presents an approach to enhance Hf0.5Zr0.5O2 (HZO) ferroelectric orthorhombic phase (O-phase) formation via in situ NH3 plasma treatment. High-resolution non-disruptive hard x-ray photoelectron spectroscopy confirmed that O-phase formation can be enhanced by suppressed interfacial diffusion between HZO and the top TiN electrode. Additional N-bonding facilitated by NH3 treatment was shown to suppress the interaction between TiN and HZO, thereby reducing the formation of oxygen vacancies within HZO. It was shown to improve the reliability and ferroelectric performance (examined by the leakage current and positive-up-negative-down measurements) of HZO devices. After cyclic operations, NH3-treated ferroelectric FETs (FeFETs) exhibited stable transfer characteristics and memory windows, whereas untreated devices presented unstable behaviors. Our results demonstrate the efficacy of the proposed in situ NH3-treatment scheme in enhancing the stability of HZO-based FeFETs.

Novel physical properties not seen in their individual layers are obtained from stacked layers of materials. In this report, using the first-principles calculations, we study the electronic band structures of heterostructures composed of graphitic (graphene-like) bilayers of g-ZnO/ZnX (X = S, Se, and Te) semiconductors. The g-ZnO layer is largely planar, but the ZnX layer is somewhat corrugated. Our calculations reveal on the stable formations of a type-II band alignment in bilayers with an AB stacking order of OZnO-ZnZnX and ZnZnO-XZnX. The optical bandgaps are much lowered as compared to the monolayers of ZnO and ZnX constituents, with the conduction band contributed by g-ZnO and valence band by ZnX. There is a quadratic dependence of the bandgap on the external electric biases applied in perpendicular to the interface. This nonlinearity manifests an superposed effect of an interlayer orbital hybridization and associated charge transferring, along with the coexistence of an electric dipole and a quadrupole. There is an overall charge transfer of valence electrons from the ZnX layer to the g-ZnO layer, leading to a pair of highly charge polarized surfaces along with a large built-in potential. The already lowered bandgaps further change with the external bias. This tunability of Eg for g-ZnO/ZnX bilayer heterostructures holds promises for optoelectronic applications covering a wider spectral range of the solar spectrum.

High-density (∼ 80/um2) vertical InAs nanowires (NWs) with small diameters (∼ 28 nm) were grown on bare Si (111) substrates by means of two-step metal organic chemical vapor deposition. There are two critical factors in the growth process: (1) a critical nucleation temperature for a specific In molar fraction (approximately 1.69 × 10−5 atm) is the key factor to reduce the size of the nuclei and hence the diameter of the InAs NWs, and (2) a critical V/III ratio during the 2nd step growth will greatly increase the density of the InAs NWs (from 45 μm−2 to 80 μm−2) and at the same time keep the diameter small. The high-resolution transmission electron microscopy and selected area diffraction patterns of InAs NWs grown on Si exhibit a Wurtzite structure and no stacking faults. The observed longitudinal optic peaks in the Raman spectra were explained in terms of the small surface charge region width due to the small NW diameter and the increase of the free electron concentration, which was consistent with the TCAD program simulation of small diameter (

This work demonstrates the germanium nanosheet channel with negative capacitance in gate-all-around field-effect-transistor (Ge NS NC-GAAFET) to reduce the subthreshold slope (SS). The Ge NS NC-GAAFET device structure, fabrication, and electrical are analysis were studied. Moreover, the Ge NS NC-FET reveals high driving current, and high I on /I off ratio (>106). The novel Ge NS NC-FET could suit for future low-power integrated circuit applications.

In this paper, we present the fabrication and characterization of gate-all-around (GAA) junctionless (JL) poly-Si nanowire (NW) transistors with a dual-gated configuration, in which a sub-gate is placed over a shorter main-gate in order to control the NW potential for the offset regions between the main-gate and S/D regions. The fabricated transistors exhibit well-behaved performance with on/off current ratio of ~106 and subthreshold swing of 76 mV/decade. Inevitable misalignment of lithographic patterning for the main-gate structure leads to asymmetrical channel offsets between the main-gate to source pad and to drain pad, respectively. That is, the length of un-gated NW close to the source pad differs from that to the drain pad. An important finding of notes is that when drain bias is applied to the end of the NW with a longer channel offset, the drain current is lower than that applied to the shorter end. Such a trend become less profound as the sub-gate bias increases.

TiN/Hf0.5Zr0.5O2 (HZO) is a popular heterostructure for HZO-based ferroelectric devices. In this study, in-situ synchrotron X-ray techniques were used to examine the ferroelectric wake-up effect of HZO in relation to TiN electrodes. TiN was shown to favor orthorhombic (O)/ferroelectric phase of HZO, while promoting the reconstruction of the TiN/HZO interface through the formation of oxygen vacancy ( V O ′ ′ ) states. Real-time changes in polarization under an applied voltage (electrical stress) indicated that V O ′ ′ regulates the observed ferroelectric wake-up effects. The changes observed using in-situ X-ray analysis included an intensification of the V O ′ ′ signal and the breaking of Hf-O bonds under electrical stress over a period of 1000 s. Stress-driven V O ′ ′ increased polarization without degrading the interface, as indicated by the capacitance–voltage (C-V) characteristics of the device. It appears that V O ′ ′ woke up HZO polarization without introducing any structural transitions. Despite the fact that V O ′ ′ formed concomitantly with the O-phase following TiN capping, it appears that V O ′ ′ plays an independent role in regulating polarization under an applied electrical field. Thus, V O ′ ′ creates a trade-off between polarization wake-up enhancement and trap states. Furthermore, the results of cyclic polarization-voltage (P-V) measurement show that stress-induced V O ′ ′ near the TiN/HZO interface is conducive to enhancing the ferroelectricity with fewer wake-up operation cycles.

A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS2 FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.

In this work, polarization-dependent time-dependent dielectric breakdown in ferroelectric HZO Ge MOSCAPs is presented. First, ferroelectric HZO Ge MOSCAPs with and without in-situ NH3 plasma interfacial layer treatment exhibit the two distinct remnant polarization (Pr). Secondly, the device with a larger Pr shows a higher gate leakage current and smaller time-to-breakdown (tBD) compared to the device with a smaller Pr. Then, a physical model based on the high probability of the electron tunneling accelerating the formation of the percolation path is proposed. Finally, the device with large Pr shows a lower extrapolated operating voltage. However, more than 1.5 V of the extracted operation voltage for 1% failure of 10 year lifetime in the device with large Pr still can be obtained.

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MoS2) 2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 {\mu}A/{\mu}m, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied., Comment: 23 pages, 14 figures

In this paper, we report that a nearly defect free In 0.71 Ga 0.29 As fin structure can be selectively grown inside oxide nano-trenches on a Ge template by using composition-graded InGaP as a buffer layer. A growth model is proposed to explain the strain energy accommodation behavior from Ge to In 0.70 Ga 0.30 P and then to In 0.71 Ga 0.29 As. This model offers a guideline for developing high quality high indium content InGaAs materials by hetero-epitaxy as required for the fabrication of novel III–V/Ge CMOS on Si substrates in the future.

In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices.