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International audience; Thyristors able to block 4 kV have been fabricated and characterised. The experimental forward current is 1.3 A @ V-AK = 10 V for a 9 mA gate current during 550 ns. The device active area is 2.3 mm(2). The devices and their edge terminations have been designed using numerical simulations. Two different edge terminations have been envisaged (mesa and a combination of mesa and JTE). A SiO2 passivation layer also improves the forward blocking voltage depending on the sign and the magnitude of the effective charge density in the oxide. The mesa protection is not enough to allowing the thyristor to block 5 kV, due to the low etching rate in SiC. Thus, a mesa/JTE protection has been used. The influence of the etching depth, the JTE dose and length on the forward blocking voltage of the thyristor has been studied in details. Simulation results have allowed designing the devices, not far from the optimal structure. The best results of the forward blocking voltage are 4 kV for the mesa protected thyristor, while the mesa/JTE combination yields 3.6 M Furthermore, experimental results confirm the simulations concerning the influence of the oxide thickness on the forward blocking voltage. The better results for the mesa protected thyristor are due to a lower interface SiC/SiO2 charge density provided by the different oxidation processes (at different foundries). In addition, the comparison between experiments and simulations allows estimate the effective charge density of the SiO2 layer in 10(12)-5 x 10(12) cm(-2) range for the two fabricated thyristors. The improvement in the forward blocking voltage must pass through an improvement of the passivation layer. Passivation still remains a technological key step to obtain SiC high-voltage devices. (c) 2006 Elsevier Ltd. All rights reserved.

International audience; The aim of this study is to propose an analysis of the parasitic lateral bipolar triggering into a single finger grounded gate n-MOS transistor under Transmission Line Pulse (TLP) stress. The experimental values are compared to numerical results issued from 3D simulation. Emission Microscopy for Multi-layer Inspection (EMMI) views and physical extractions for analysis during this electrical stress reveal similar results. Thus, it appears that the triggering is different for two ElectroStatic Discharge (ESD) current levels. (C) 2004 Elsevier Ltd. All rights reserved.

Wafer bonding technologies have been recognized to provide new substrates structures suitable for the development of Si power devices. Among the multiple examples that could be listed, the possibility to generate PN junctions without thick epitaxial growth and lateral devices onto dielectrically isolated substrates such as SOI (Silicon On Insulator) are significant examples of the interest proposed by wafer bonding. Thin film substrates obtained with the Smart-Cut® technology such as SiCOI (SiC On Insulator) substrates for lateral devices and QUASIC substrates for vertical power devices have already been demonstrated. In this article, we review the recent developments in the field of SiC power devices using these two kinds of SiC Smart-Cut substrates. Lateral and vertical Schottky diodes have been processed onto SiCOI and QUASIC substrates as a demonstration of feasibility. Simulations, results and prospects are presented in this article.

International audience; SiC-based devices are very suitable for high current and high voltage applications [H. Matsunami, Progress in wide bandgap semiconductor SiC for power devices, Invited Paper, ISPSD'00 22-25 May 2000, Toulouse]. Nevertheless, SiC material has some limitations that constrain the capability of these devices. This work is devoted to the design and fabrication of a new etched VJFET, which implements both gate and source in buried layers. This technological approach enables more flexibility in the basic cell layout design (square cells) than the conventional surface gate implementation. Therefore, various geometrical layouts have been investigated in order to find a trade-off between current density, driving ability and current limiting capability. The minimum lithography feature, reactive ion etching and the minimum spacing between adjacent implantations were key points in setting-up the design rules. I-V curves of the designed structures for a gate-to-source bias of 0 and -30 V has been performed at room temperature. All devices exhibit a current saturation at an on-state voltage higher than 10 V. The dependence of the internal access gate resistance on the layout has been checked by means of transconductance measurements. Transconductance has been estimated for each type of structure, being in the range of 57.8-672 mS/mm.. Nevertheless, a new figure of merit (the transconductance per active area) allows to find out the most suitable layout in terms of output current density and gate resistance. A comparison in terms of current and transconductance per source gives the best solution in terms of output saturation current and gate resistance. The results of those measurements are discussed with future perspectives for implementation of the most appropriated layout in an integrated system.

International audience; Based on numerical simulations we fabricated thyristors on SiC with respect to different pulsed power applications. In order to achieve high breakover voltages we developed and investigated various types of terminations (MESA, EGR, JTE). Thyristors, terminated by epitaxial guard rings (EGR), showed breakover voltage of up to about 1900 V. By dynamic electrical characterisations of the devices a reliable turn-on and turn-off could be demonstrated

International audience; 4H-SiC P + NN + structures have been fabricated following Medici TM software simulation in order to block voltages as high as 6 kV. In particular, these diodes are realized by surrounding the emitter by a Aluminum-implanted ring called Junction Termination Extension (JTE). Electrical characterizations under reverse bias at room temperature and in various environments (air, SF 6) show a premature breakdown of the diodes. This breakdown is localized at the emitter periphery. OBIC (Optical Beam Induced Current) measurements show a peak of photocurrent at the emitter junction edge, indicating the presence of a high electric field. These results involve an effectiveness of 60 % of the JTE. This is probably related to a low electrical activation of the implanted aluminum during the post-implantation annealing and to the presence of positive charges at the surface of the devices. Introduction.

International audience; Keyword : Current limiter, JFET, serial protection device, high voltage. Abstract : Considering fault current limiters for serial protection, a lot of structures exist, from regulation to other complex systems such as circuit breakers, mechanical switches or more conventional system : fuses. Up to now, only few semiconductor current limiter structures were described in papers [1]. Although Current Regulative Diode components exist [2, 3], the voltage and current capabilities (V BR =100 V, I max =10 mA), do not allow to use them in power systems. A comparison of a silicon Current Regulative Diode (CRD) and an equivalent SiC one demonstrates the thermal and electrical limitations of silicon. This paper deals with a novel bi-directional current limiter structure based on a vertical α-SiC VJFET, with both buried gate and source. This device was designed for short circuit protections. Simulations were performed with ISE-TCAD [4] to evaluate static and transient electrical characteristics of the VJFET, according to several specifications : voltage capability, current rating, time during which the device can sustain a short circuit. Simulations allow geometrical design and doping profile estimation as well as the technological process to realize such a component. Both 6H and 4H-SiC Controlled Current Limiter (CCL) have been realized. Electrical characterizations of fabricated devices underline the limiting effect and the command ability.

International audience; Due to its good electrical properties, mainly a high critical electric field and a large bandgap, silicon carbide has demonstrated potentialities for high power devices. We have designed and realised bipolar diodes to sustain a reverse voltage of about 1.3 kV. We present below the experimental breakdown voltage we achieved, and results of OBIC measurements.

International audience; Recently INFINEON and other companies announced the market introduction of their SiC Schottky rectifiers in the range of 600 V several amperes. This announcement allows the design of power electronic systems with a cooling effort drastically reduced than required before, which is a great improvement for electronics in terms of cost and efficiency. However SiC components are still checked by an expensive substrate supplying and by the small 3 inches size of the SiC wafers.SiCOI substrate presents the capability of large sized handle wafers, allowing the utilization of 4,6 or 8 inches facilities. In addition the fabrication of numerous SiCOI substrates requires a single SiC substrate as illustrated in figure 1. This later point should make SiCOI a low cost SiC substrate. The purpose of this article is to give the first electrical characteristics of a Schottky rectifier on that promising substrate.

International audience; Most of silicon devices such as Schottky diode, MOSFET, MESFET have been realized in SiC and show good electrical and thermal characteristics [1]. Considering fault current limiters for serial protection, a lot of structures exists [2, 3], from conventional fuses to other complex systems such as circuit breakers, mechanical switches. Up to now, few specific SiC-current limiter were described [4, 5]. This paper presents experimental characterization of a bi-directional current limiter structure based on a vertical SiC VJFET.

International audience; Considering fault current limiters for serial protection, a lot of structures exist, from regulation to other complex systems such as circuit breakers, mechanical switches or more conventional system : fuses. Up to now, only few semiconductor current limiter structures were described in papers [1]. Although Current Regulative Diode components exist [2, 3], the voltage and current capabilities (VBR=100 V, Imax=10 mA), do not allow to use them in power systems. A comparison of a silicon Current Regulative Diode (CRD) and an equivalent SiC one demonstrates the thermal and electrical limitations of silicon. This paper deals with a novel bi-directional current limiter structure based on a vertical a-SiC VJFET, with bothburied gate and source. This device was designed for short circuit protections. Simulations were performed with ISE-TCAD [4] to evaluate static and transient electrical characteristics of the VJFET, according to several specifications : voltage capability, current rating, time during which the device can sustain a short circuit. Simulations allow geometrical design and doping profile estimation as well as the technological process to realize such a component. Both 6H and 4H-SiC Controlled Current Limiter (CCL) have been realized. Electrical characterizations of fabricated devices underline the limiting effect and the command ability.

International audience; 4H-SiC P+NN+ structures have been fabricated following MediciTM software simulation in order to block voltages as high as 6 kV. In particular, these diodes are realized by surrounding the emitter by a Aluminum-implanted ring called Junction Termination Extension (JTE). Electrical characterizations under reverse bias at room temperature and in various environments (air, SF6) show a premature breakdown of the diodes. This breakdown is localized at the emitter periphery. OBIC (Optical Beam Induced Current) measurements show a peak of photocurrent at the emitter junction edge, indicating the presence of a high electric field. These results involve an effectiveness of 60 % of the JTE. This is probably related to a low electrical activation of the implanted aluminum during the post-implantation annealing and to the presence of positive charges at the surface of the devices.

International audience; The first experimental results of a 600 V 4H-SiC current limiting device are shown. This device limits the current as the bias voltage increases. The forward conduction is ensured by an N type implanted channel (doping species: nitrogen) on top of a P+ implanted layer (doping species: aluminum). The prototypes reach a saturation current density of 900 A.cm-2, with a specific on-resistance of 13 mcm². The 4H-SiC current limiting devices belong to the best set of Accu-MOSFETs devices reported in the literature.

International audience; Silicon carbide has received an important attention for high-power, high-temperature and high-speed electronic fields. Ion implantation, the only method to locally dope SiC, seems to be a delicate point especially to obtain p-type silicon carbide regions. High temperature post-implantation annealings in particular conditions (high heating ramp, silicon and carbide overpressure) are needed to achieve well activated layers in a well preserved crystalline state. In a first time an optimized post-annealing process was obtained. A SiC dedicated furnace was used to anneal room temperature (RT) and 300°C aluminum (Al) implanted 6H-SiC samples. Recrystallization and surface preserving were investigated by physico-chemical analyses like: Rutherford Backscattering Spectrometry (RBS), X-Ray Photoelectron Spectroscopy (XPS) and Atomic Force Microscopy (AFM). Systematic Secondary Ion Mass Spectroscopy (SIMS) analyses were carried out before and after annealing. Well recrystallized samples were found even if ion implantations (at room temperature) have lead to amorphous layers, in terms of RBS results, with an annealing at 1700°C during 30 min. A relatively important roughness (14.4 nm rms) was found by AFM analyses. SIMS investigations show that the doping profile is preserved and no Al diffusion occurs 1. Four-point probe measurements prove a high electrical dopant activation, in terms of Al incorporation in SiC active lattice sites. 50% (respectively 100%) activation was found after an annealing at 1700°C during 30 min for RT (respectively 300°C) implanted samples. This process has been applied to fabricate 4H-and 6H-SiC bipolar power diodes, on n-type epitaxial layers purchased from Cree Research (40 µm, 1.1x10 15 cm-3 epitaxial doping for 4H-SiC wafers and 10 µm, 6x10 15 cm-3 epitaxial doping for 6H-SiC wafers). A Junction Termination Extension (JTE) structure was chosen after physical and electrical simulations using ISE TCAD and MEDICI program softwares. Several electrical test-structures were added to investigate dopant preservation and activation, the quality of the ohmic contact metallization and lithographic process. Hall effect in a Van der Pauw geometry and TLM (Transmission Line Model) measurements confirm the dopant activation and 5x10-4 W cm 2 contact resistance was found at 300K for an Al-Ti process metallization on p-type doped zones (4x10-19 cm-3 Al implanted box profile). Forward current density obtained by I-V measurements at 300 K on JTE bipolar diodes is 50 A/cm 2 at 5V drop voltage. In reverse bias these diodes have shown blocking voltage capabilities up to 1kV for 6H-SiC wafer and 2.3 kV for the 4H-SiC one.

International audience; 4H- and 6H-SiC small samples were implanted by keV Al+ ions at room temperature and annealed in an induction heating furnace, at the center of the susceptor, for different temperatures and times in the range 1600-1800°C and 5-60 min, respectively. The implanted layers were amorphous but the SiC crystalline structures were recovered after annealing, as measured by Rutherford Back-Scattering analyses in Channeling geometry.Al+ electrical activation determined by sheet resistance and Hall effect measurements increases with the annealing temperature or time, on both polytypes. When whole SiC wafers were annealed in the same induction heating furnace, sheet resistance mapping systematically presented a radial gradient from the center to the periphery of the wafer. The measured linear dependence between sheet resistance and temperature allowed us to rebuild the radial temperature gradient at the crucible-susceptor furnace during the annealing process.

Some new device structures are developed to take advantage of the superiority of silicon carbide over silicon for high voltage and high temperature conditions. That’s the case of the JBS rectifier (junction barrier Schottky) and the VJFET (vertical junction field effect transistor) who exhibit very interesting characteristics: JBS with low voltage drop (1V) and high breakdown voltage (2.5 kV), and VJFET with a RON close to 15 m.cm² and VBR=1800V. The aim of this paper is to show the first experimental results of our 4H-SiC current limiting device. This device limits the current which flows through it as the bias voltage between its two contacts increases. The static curves obtained (T=300 K) show a current limitation ability with a saturation voltage ranging from 10V to 15V. The electrical device characterization shows a RON150 m.cm² and a current density of 100 A/cm² under 50V. The forward conduction is assumed by an N type implanted channel (doping species: nitrogen) over an P+ implanted layer (doping species: aluminum). The post-implantation annealing of 1700 °C/30 mn leads to a good electrical activation (80%) of the NCHANNEL/P+ layer (analyzed by C(V) and SIMS methods) and a good channel mobility (100 cm2.V-1.s-1 for a 31017 cm-3 N compensated doping concentration).

International audience; Five-fold Al implantations at both room temperature and 300°C ranging from 25 keV to 300 keV and a total fluence of 1.75x10 15 cm-2 , have been performed in 6H-SiC epilayers to create p +-n junctions. The samples have been annealed at 1700°C during 30 mn in an inductively heated furnace especially configured. Surface effects, recrystallization, dopant distribution and electrical activation are investigated by XPS, RBS, SIMS and sheet resistance measurements. For both RT and 300°C-implanted samples, good recrystallization and surface stoichiometry are found as well as no dopant loosing and an interesting electrical activation (46% and 99%, respectively). Introduction p +-n junctions in SiC power devices must be realized by ion implantation due to very low diffusion coefficients of dopants in silicon carbide. SiC high density and its structural crystallinity involve a delicate post-implantation annealing. The implantation temperature, annealing environment, time and temperature of annealing and the heating rate are the essential parameters to reorder the crystal damage induced by ion implantation and to activate the dopants by migrating in SiC atomic sites. Initially, after ion implantation, almost all Al dopants are distributed in interstitial sites, where they are not electrically active. We utilized a JIPELEC TM rf induction furnace. This technique of annealing has significant advantages such as the very high rising slope in temperature and the very localized zone of heating (the susceptor). But this one implies high temperature variations, vertically in the enclosure and laterally on the surface of the SiC wafers. These temperature gradients may cause an etching of, or a layer deposition on the SiC surface. Moreover, Si is known to volatilize towards 1400°C at one atmosphere pressure, and in lack of a Si supersaturating vapor the carbonization of the surface is inevitable. This paper presents the results of an optimized thermal rf annealing, which avoids these problems.

International audience; New models for the high frequency capacitance-voltage, C(V) and forward curreat-voltage, I-F(V-F) characteristics of a large area 6H-SiC boron compensated pn junction have been developed and implemented in an optimal parameter extraction program. The C(V) model and SIMS measurements confirm the presence of two type regions (p(-) and n(-)) in the quasi-intrinsic layer induced by boron doping. The extracted values of the net doping of these zones (6-10 x 10(12) cm(-3)) are in good agreement with previously reported data. In contrast, the thickness of the quasi-intrinsic layer, about twice the epilayer width, proves the expansion of the quasi-intrinsic region in the substrate. The I-F(V-F) modeling includes a square law dependence of the forward current on VF, at high injection level. For the first time in the literature, saturation currents of SIC pn diodes is reported. The extracted saturation currents increase linearly with area, evidencing the beneficial effect of boron diffusion for obtaining predictable large area devices. The temperature behavior is also investigated. At high temperatures, the boron compensation effect is reduced.

International audience; Bipolar diodes, protected with junction termination extensions, were processed in 6H-SiC. A 5-fold aluminum implantation was carried out for the main p(+)-n junction creation, which led to the material amorphization. The recrystallization variation with the annealing temperature and duration is examined in this paper. We performed the Al implantations with apposite energy orders, in order to study their influence on the diode electrical characteristics. The increasing order led to a better forward conduction. and reverse leakage currents more important.

International audience; Les exigences toujours plus grandes des utilisateurs de composants de puissance entraînent la recherche des meilleurs compromis pour des structures en silicium. Les limites de ce matériau amènent le développement de composants dans d'autres matériaux tels que le carbure de silicium. Les progrès réalisés en microélectronique permettent d'intégrer des fonctions de plus en plus complexes avec les composants de puissance et les fabricants de semiconducteurs fournissent aujourd'hui des fonctions intégrées. Enfin la conception des systémes de puissance exige le développement de modèles multi-domaines (électrique, thermique, mécanique) pour les composants et les systèmes. Cet article, après une présentation des généralités sur les composants de puissance mettant en évidence la nécessité des compromis, donne un aperçu de l'état de l'art des composants en silicium avant d'aborder les nouveaux matériaux et l'intégration des systèmes. Il se termine par une brève description des méthodes de modèlisation et de simulation des circuits électroniques de puissance. ABSTRACT. The always-stronger demands of power device users impose the search for better trade-offs regarding silicon device structures. The limitations of silicon lead to the development of devices with other materials like silicon carbide. The improvements in microelectronics enable to integrate more and more complex functions along with power parts and semiconductor device manufacturers already offer such integrated systems. Finally, the design of power electronic systems demands the development of multi-domain models (electrical, thermal, magnetic) for components and systems. The present paper covers generalists of power semiconductor devices enlightening the necessity of new trade-offs. Then the paper discusses a state-of-the art of silicon devices, new materials and system integrations. Finally, it is covered briefly the modeling method and simulation techniques of power electronic circuit. MOTS-CLES : composants de puissance à semiconducteur, silicium, carbure de silicium,circuits intégrés de puissance, modélisation, simulation, modèles moyens, électronique de puissance.

International audience; Boron diffusion can be used to compensate the n-type layer of a p(+)nn(+) 6H-silicon carbide structure in order to increase its high-voltage capabilities. Measurements under reverse biases for a current range from 10 to 500 mu A show that this process is very efficient for working temperatures about 300 K. Indeed we obtained a voltage of 670 V for a reverse current of 10 mu A instead of the 120 V calculated for a structure without boron diffusion. Nevertheless, the breakdown voltage decreases rapidly when the temperature increases. Capacitance measurements show that the measured doping level in the n-type layer evolves in the same way as the temperature (it ranges from 10(13) cm(-3) at 300 K to 10(17) cm(-3) at 500 K). A great concentration of boron seems to be responsible for this doping variation with temperature. Admittance spectroscopy reveals the presence of D centers at 0.62 eV above the valence band associated to boron at concentration similar or superior to nitrogen concentration in the n-type layer. The increase of the doping level with the temperature is responsible for this decrease of the breakdown voltage.

International audience; The concepts of state variable modeling have been applied to obtain a general circuit like model for the power PIN diode. The main aim of this paper is to demonstrate the feasibility of the state variable modeling approach for the PIN diode. From simplified semiconductor device differential equations, the model is built with the corresponding variational equation using an internal approximation. With a special choice of the decomposition functional basis of such internal approximation, it was possible to get efficient and reliable models for the reverse recovery. A simple model of three state variables that has only six parameters, most of which are technological, represented a major improvement in describing circuit/device waveforms during reverse recovery.

International audience; The use of silicon as the basic semiconductor for power electronics represents a limitation for the rise in device operating temperature. The great increase in leakage currents is a major obstacle for the rise in junction temperature. To avoid this drawback, wide bandgap semiconductors must be considered. Among them, silicon carbide is a promising material thanks to its physical properties more suitable for power applications than those of silicon or gallium arsenide, and its technological progress becoming more and more industrially applicable, which is not yet the case for diamond.