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In this study, we present the design, simulation, and implementation of a DC-DC synchronous buck converter utilizing IISB's 2 μ m 4H-silicon carbide (SiC) complementary metal–oxide–semiconductor (CMOS) technology. The converter is designed to meet the demands of modern integrated circuits, particularly in the field of integrated power management. The SiC technology offers enhanced performance and reliability at high temperatures, making it especially suitable for applications that operate in these conditions, including automotive systems, and aerospace, among others. The power transistors and gate drivers are fully integrated on-chip, optimizing efficiency and minimizing footprint. Additionally, the study contributes to the understanding of SiC technology and its application in integrated circuit design. Simulation results demonstrate a peak efficiency of 86.6% at 120 mA load current and 84.8% at 300 mA load current, showing the converter performance under different operating conditions. Furthermore, at high temperatures (295 °C), the converter achieves an efficiency of 89.6%, demonstrating its robustness and versatility in extreme environments. These findings contribute to the advancement of integrated circuit design and facilitate advancements in more efficient and robust power management solutions. [ABSTRACT FROM AUTHOR]

With the advancement of CMOS technology, the susceptibility of SRAM to single node upset (SNU), double node upset (DNU), and multiple node upset (MNU) induced by radiation has increased. To address this issue, various cutting-edge solutions, such as radiation hardened sextuple cross coupled (RHSCC)-16T and DNU-completely-tolerant memory (DNUCTM) cells, have been proposed. While the RHSCC-16T cell is robust against SNU, it may be vulnerable to DNU. The DNUCTM cell is resistant to both SNU and DNU, but it remains susceptible to MNU. In this paper, we propose a radiation hardened read-stability and speed enhanced (RHRSE)-20T SRAM, which is immune to all potential cases of SNU, DNU, and MNU. Additionally, the proposed design demonstrates improvements in read and write delays compared to conventional SRAM designs. Experimental results confirm that the RHRSE-20T SRAM maintains stability under various charge levels for SEU, DNU, and MNU. The proposed integrated circuit is implemented in a 90-nm CMOS process and operates on a 1 V supply voltage, offering significant advantages for next-generation radiation-hardened memory applications. [ABSTRACT FROM AUTHOR]

It is anticipated that the downsizing of the CMOS device will end soon, but Moore’s law will continue for several more generations. In recent technology nodes, the performance improvement and higher density of CMOS integrated circuits depended on the smaller footprint resulting from a larger fin height of FinFETs. As device scaling approaches its end, every possible method to increase chip density has been extensively explored. These include the introduction of nanosheet or forksheet structures, better arrangement of power rails and three-dimensional stacking technologies from the device level to the system level. In this review, we highlight various strategies for extending Moore’s law. We discuss the challenges of nanosheet transistors, which are believed to be the ultimate MOS structure and will be implemented in the next technology node. We also discuss some alternative ultimate MOS structures. Nevertheless, from the technological and economic points of view, the mainstream technology in the coming decades should be 3D stacking technology such as CFET at the device level and monolithic 3D technology for system integration. [ABSTRACT FROM AUTHOR]

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions. [ABSTRACT FROM AUTHOR]

The emergence of neuromorphic computing, inspired by the structure and function of the human brain, presents a transformative framework for modelling neurological disorders in drug development. This article investigates the implications of applying neuromorphic computing to simulate and comprehend complex neural systems affected by conditions like Alzheimer's, Parkinson's, and epilepsy, drawing from extensive literature. It explores the intersection of neuromorphic computing with neurology and pharmaceutical development, emphasizing the significance of understanding neural processes and integrating deep learning techniques. Technical considerations, such as integrating neural circuits into CMOS technology and employing memristive devices for synaptic emulation, are discussed. The review evaluates how neuromorphic computing optimizes drug discovery and improves clinical trials by precisely simulating biological systems. It also examines the role of neuromorphic models in comprehending and simulating neurological disorders, facilitating targeted treatment development. Recent progress in neuromorphic drug discovery is highlighted, indicating the potential for transformative therapeutic interventions. As technology advances, the synergy between neuromorphic computing and neuroscience holds promise for revolutionizing the study of the human brain's complexities and addressing neurological challenges. [ABSTRACT FROM AUTHOR]

The performance of CMOS transmitters and receivers operating at the submillimeter electromagnetic wave frequencies have sufficiently improved for use in active transmission and reflection-mode imaging applications that have the potential for broad deployment and utilization. Imaging integrated circuits have the potential to be large in area to support a high number of pixels along with digital backend processing circuits. For high volume imaging applications that may eventually be included in automobiles, smartphones, laptops, tablets, and others, a large manufacturing capacity to support the volume of large area ICs is necessary. For this, the use of CMOS technologies with a much larger manufacturing capacity is favored. It should be possible to improve the performance of CMOS circuits to increase the range, and operation margin and frequency. The electronically steerable submillimeter-wave reflector technology holds the promise for improving the performance and energy efficiency of submillimeter-wave imaging systems by multiple orders of magnitude, and it is a critical research area. Increasing the operating frequency from 430 to 850 GHz using CMOS integrated circuits to improve the angular resolution by 2X at a given form factor (∼0.15° for a reflector diameter of 15 cm) can make the submillimeter-wave imaging competitive to the LIDAR angular-resolution performance, while providing superior capabilities in visually impaired conditions and making the imaging devices more affordable. [ABSTRACT FROM AUTHOR]

In this paper, a robust fault detection methodology for complex analog CMOS integrated filters is presented. It is based on combining the two types of testing methodologies, Oscillation-Based Testing (OBT) and IDDQ testing, i.e., measuring of the power-supply current ( I D D ). The proposed methodology is applied to the Bi-quad Sallen–Key band-pass (BP) filter cell with relatively complex, two-stage, class-AB-output, operational amplifier (opamp) topology. The filter is custom designed targeting the 180-nm CMOS technology. Hundreds of time-domain simulations and analyses of the circuit output signal are performed in order to obtain the fault dictionary. The presented results show that the proposed hybrid OBT–IDDQ methodology is significantly more efficient in the defects coverage than any of the particular test methodologies alone. Subsequently, the specific algorithm for the defects classification is proposed. Based on the classification, certain degree of diagnosis of the individual defect, or a group of defects, can be achieved. [ABSTRACT FROM AUTHOR]

The electrical and physical properties of MOS device structures (capacitor, field-effect transistor with an insulated gate and induced channel, CMOS integrated circuit) when exposed to unmodulated laser radiation are studied. The static and dynamic characteristics are measured. The theoretical study is carried out using the developed SPICE models and numerical experiments. An expression is obtained for the volt-ampere characteristics (VACs) of a field-effect transistor operating in a mode with constant optical illumination. It is shown that the characteristics of structures are determined by the generation and recombination of nonequilibrium charge carriers, the field effect, and the photovoltaic effect in p–n-junctions, the Dember effect, and the tunneling of charge carriers through the gate dielectric. The results of the study are of interest in terms of creating high-speed transistors and integrated circuits of a new type. [ABSTRACT FROM AUTHOR]

This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology. [ABSTRACT FROM AUTHOR]

This letter presents a wirelessly powered LED driving circuit for a smart contact lens system. Since photobiomodulation has been investigated for ocular disease treatment by irradiating light with a specific wavelength, a smart contact lens equipped with a µLED and its controller IC can be utilized as a phototherapy system. The proposed circuit design facilitates constant‐current generation to drive the LED and incorporates a wirelessly powered system. The system can be turned on and off in synchronization with an external wireless power source, providing controllability for the LED's irradiation period and intensity. The IC is fabricated in the 180‐nm CMOS process with a die area of 1.0 mm2 and integrated into the smart contact lens with an external loop antenna and a far red/NIR LED. The measurement demonstrates the irradiation period of the LED is successfully controlled by the external source, with current levels from 0.53 mA to 1.4 mA, thereby confirming the feasibility of the phototherapy system. [ABSTRACT FROM AUTHOR]

Diamond holds the highest figure‐of‐merits among all the known semiconductors for next‐generation electronic devices far beyond the performance of conventional semiconductor silicon. To realize diamond integrated circuits, both n‐ and p‐channel conductivity are required for the development of diamond complementary metal‐oxide‐semiconductor (CMOS) devices, as those established for semiconductor silicon. However, diamond CMOS has never been achieved due to the challenge in n‐type channel MOS field‐effect transistors (MOSFETs). Here, electronic‐grade phosphorus‐doped n‐type diamond epilayer with an atomically flat surface based on step‐flow nucleation mode is fabricated. Consequently, n‐channel diamond MOSFETs are demonstrated. The n‐type diamond MOSFETs exhibit a high field‐effect mobility around 150 cm2 V−1 s−1 at 573 K, which is the highest among all the n‐channel MOSFETs based on wide‐bandgap semiconductors. This work enables the development of energy‐efficient and high‐reliability CMOS integrated circuits for high‐power electronics, integrated spintronics, and extreme sensors under harsh environments. [ABSTRACT FROM AUTHOR]

The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C2P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C2N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C2P-C2N, DMR-C2P and DMR-C2N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C2N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, OOK-modulated, impulse-radio ultra-wideband (IR-UWB) transmitter. The pulse generation method is derived from a filtered combined edge technique, where narrow pulses are produced by a delay-and-logic gate and shaped with a filter to generate UWB pulses compliant with the FCC standard. The pulse-shaping filter and antenna driving circuit are co-designed and combined into one, that is, a pulse amplifying and shaping circuit that operates in the C-class state, resulting in extremely low complexity, low power, and small circuit area. The proposed IR-UWB transmitter was implemented and fabricated using a standard 0.18- μ m complementary metal oxide semiconductor (CMOS) 1p6m process. The power supply voltage is 1.5 V and the targeted maximal data rate is 250 Mbps. The chip measurement results show that the output UWB signal covers 3.1–6.0 GHz frequency band, the power spectrum density conforms to the FCC spectrum masks, and the peak-to-peak voltage of the output UWB pulses is 183 mV. In addition, the core area of the chip is 0.098 mm2 and the transmitter power consumption is 2.48 pJ per pulse. [ABSTRACT FROM AUTHOR]

This paper presents for the first time a quad-core oscillator based on a very compact interstacked transformer that tightly couples the four cores without oscillation mode ambiguity thanks to its strong magnetic coupling factor. As a proof of concept, a 19.125 GHz oscillator for a narrowband 77 GHz radar system was designed in 28 nm fully depleted silicon-on-insulator CMOS technology with a general purpose back-end-of-line. The soundness of the proposed quad-core oscillator topology is demonstrated by comparison with state-of-the-art quad-core solutions, highlighting a significant advantage in terms of area occupation and power consumption. The proposed topology can be profitably exploited in several RF/mm-wave applications, such as radar and wireless communication systems. [ABSTRACT FROM AUTHOR]

Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are potentially applicable in artificial and spiking neural networks, memory arrays, and many other devices and circuits for artificial intelligence. In this paper, a complete electronic realization of an analog circuit model of the modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in the LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an important step towards the forthcoming design of complex memristor-based neural networks for artificial intelligence, for implementation in very high-density integrated circuits and chips. [ABSTRACT FROM AUTHOR]

This document is an editorial for a special issue of the journal Micromachines on the topic of state-of-the-art CMOS and MEMS devices. The editorial highlights the importance of CMOS and MEMS devices in emerging research fields such as artificial intelligence, 5G communication, the Internet of Things, and satellite communication. It mentions that the research in this field is focused on design, modeling, fabrication, and application of CMOS and MEMS devices. The special issue contains 10 published articles that address the demand for high-performance silicon ICs and MEMS devices and explore device and circuit design techniques, performance optimization methods, and system integration strategies. The editorial concludes by acknowledging the challenges and obstacles that remain in the field and expressing hope that the articles in the special issue will be interesting and inspiring for readers. [Extracted from the article]

In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was $11.6\pm 0$ .8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was $11.9\pm 1$ .1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.

In this paper, a quad-core oscillator is presented, which exploits a novel stacked two-port inductor topology to couple four oscillator cores. The topology guarantees excellent low-phase-noise performance, while overcoming the drawbacks of multi-core oscillators in terms of power consumption and silicon area occupation. Three different 19.125-GHz quad-core VCOs were designed in a fully depleted silicon on insulator CMOS technology to demonstrate the high design flexibility of the proposed solution that allows power consumption and area occupation to be traded off according to the specific requirements. Although the quad-core VCO design was aimed at 77-GHz automotive radar, the proposed topology can be profitably exploited in RF/mm-wave wireless communication systems.

Abstract A 0.45‐V low‐power wideband image‐rejection low‐noise amplifier (LNA) using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS process has been proposed. The supply voltage, power consumption and chip area of the proposed LNA can be reduced using forward body biasing, folded cascode topology and a feedback capacitor. Moreover, a wideband gain‐enhancement‐and‐image‐rejection (WGEIR) circuit including a variable resonant LC tank and a common‐gate amplifier has been developed. The inductance of the variable resonant LC tank can enlarge the gain of the proposed LNA. The capacitance of the variable resonant LC tank can achieve the image rejection. Using the WGEIR circuit, gain enhancement and wideband image rejection can be achieved simultaneously. The variable inductors and capacitors are developed for suppressing wideband image signals and good image rejection ratio (IRR). The combination of the variable inductors and capacitors can achieve eight image‐reject frequencies under three control voltages. The proposed LNA shows the measured results including a 10‐dB power gain, a 3‐dB noise figure (NF) and a −11‐dBm input third‐order intercept point (IIP3) at 2.4 GHz, respectively. The measured IRR ranges from 18 to 23 dBc around 3.6–4.5 GHz, which is 900‐MHz image‐reject bandwidth. The measured proposed LNA using the mentioned techniques consumes 0.8‐mW power.

The last two decades have witnessed a dramatic increase in research on low‐dimensional material with exceptional optoelectronic properties. While low‐dimensional materials offer exciting new opportunities for imaging, their integration in practical applications has been slow. In fact, most existing reports are based on single‐pixel devices that cannot rival the quantity and quality of information provided by massively parallelized mega‐pixel imagers based on complementary metal‐oxide semiconductor (CMOS) readout electronics. The first goal of this review is to present new opportunities in producing high‐resolution cameras using these new materials. New photodetection methods and materials in the field are presented, and the challenges involved in their integration on CMOS chips for making high‐resolution cameras are discussed. Practical approaches are then presented to address these challenges and methods to integrate low‐dimensional material on CMOS. It is also shown that such integrations could be used for ultra‐low noise and massively parallel testing of new material and devices. The second goal of this review is to present the colossal untapped potential of low‐dimensional material in enabling the next‐generation of low‐cost and high‐performance cameras. It is proposed that low‐dimensional materials have the natural ability to create excellent bio‐inspired artificial imaging systems with unique features such as in‐pixel computing, multi‐band imaging, and curved retinas. [ABSTRACT FROM AUTHOR]

Velocity-selective recording (VSR) of electroneurogram (ENG) signals is a frequently utilized technology in the field of neural recording with applications in clinical medicine and neuroprosthetics. VSR classifies excited axon populations in terms of their conduction velocities using multiple recordings of the same ENG signal and addition of the recording channels after introducing controlled time delays. This paper describes the first fully integrated analogue realization of the complete delay-and-add process with nine channels. The proposed approach uses switched-capacitor (SC) circuits and avoids the need for ADCs at the inputs of the delay-and-add circuit to achieve a small size and low power implementation. Simulated and measured results obtained from chips fabricated in 0.35 µm CMOS technology are reported. The system occupies a 1.16 mm2 active area and consumes 798 µW from a 3 V supply, while achieving a wide velocity detection range of 10–300 m/s with a precise relative velocity resolution down to 0.003. Intrinsic velocity spectra measured from synthetic ENG inputs confirm the operation of the system. [ABSTRACT FROM AUTHOR]

A 0.45‐V low‐power wideband image‐rejection low‐noise amplifier (LNA) using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS process has been proposed. The supply voltage, power consumption and chip area of the proposed LNA can be reduced using forward body biasing, folded cascode topology and a feedback capacitor. Moreover, a wideband gain‐enhancement‐and‐image‐rejection (WGEIR) circuit including a variable resonant LC tank and a common‐gate amplifier has been developed. The inductance of the variable resonant LC tank can enlarge the gain of the proposed LNA. The capacitance of the variable resonant LC tank can achieve the image rejection. Using the WGEIR circuit, gain enhancement and wideband image rejection can be achieved simultaneously. The variable inductors and capacitors are developed for suppressing wideband image signals and good image rejection ratio (IRR). The combination of the variable inductors and capacitors can achieve eight image‐reject frequencies under three control voltages. The proposed LNA shows the measured results including a 10‐dB power gain, a 3‐dB noise figure (NF) and a −11‐dBm input third‐order intercept point (IIP3) at 2.4 GHz, respectively. The measured IRR ranges from 18 to 23 dBc around 3.6–4.5 GHz, which is 900‐MHz image‐reject bandwidth. The measured proposed LNA using the mentioned techniques consumes 0.8‐mW power. [ABSTRACT FROM AUTHOR]

Abstract A push–pull low‐dropout regulator based on flipped voltage follower is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The push‐current mode with 1.2‐V input and 1‐V output effectively drives load circuits that are sensitive to supply noise. The pull‐current one with 1.2‐V input and 0.2‐V output effectively drives load circuits that are sensitive to ground noise. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns transient response time over load current (IL) of 10 µA to 20 mA. The presented design achieves a fast transient response and a high‐frequency PSR with a low‐gain fast loop (loop‐I), and enhances the low‐frequency PSR and the line/load regulation with a high‐gain slow loop (loop‐II). Furthermore, the circuit features a load regulation less than 0.09 mV/mA over IL of 10 µA to 20 mA and a line regulation less than 0.01 mV/mV, within a 120‐mV ripple applied to supply/ground. This design consumes a 58‐µA quiescent current (IQ) in both push‐current and pull‐current modes. The low‐dropout regulator works well over the load capacitor (CL) of 0 to 30 pF.

This letter presented a symmetric 8T2R NVSRAM with autosave function. By efficiently multiplexing the node voltages, the control of the nonvolatile memristor and the isolation of the data node from the memristor are achieved, which ensures an instantaneous transition to the memristor state. Store and restore can be achieved within 66.1ps and 2.97 ps in case of VDD is 1 V for the worst case. In addition, the 8T2R structure performs well at lower supply voltages as 243.3 mV for STORE and 411.8 mV for RESTORE. When a 10%‐dimensional error of the devices and 10% memristance mismatch are taken into account, the 8T2R still shows high stability. [ABSTRACT FROM AUTHOR]

A push–pull low‐dropout regulator based on flipped voltage follower is proposed and designed in 65 nm CMOS, which has a push‐current mode and a pull‐current one. The push‐current mode with 1.2‐V input and 1‐V output effectively drives load circuits that are sensitive to supply noise. The pull‐current one with 1.2‐V input and 0.2‐V output effectively drives load circuits that are sensitive to ground noise. Both operating modes feature full‐spectrum power supply rejection (PSR) below −12 dB and achieve 2.4‐ns transient response time over load current (IL) of 10 µA to 20 mA. The presented design achieves a fast transient response and a high‐frequency PSR with a low‐gain fast loop (loop‐I), and enhances the low‐frequency PSR and the line/load regulation with a high‐gain slow loop (loop‐II). Furthermore, the circuit features a load regulation less than 0.09 mV/mA over IL of 10 µA to 20 mA and a line regulation less than 0.01 mV/mV, within a 120‐mV ripple applied to supply/ground. This design consumes a 58‐µA quiescent current (IQ) in both push‐current and pull‐current modes. The low‐dropout regulator works well over the load capacitor (CL) of 0 to 30 pF. [ABSTRACT FROM AUTHOR]

Abstract In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self‐timing CMOS first‐edge take‐all (FETA) circuit architecture, which examines two overlapping signals’ requests, and outputs only the leading‐edge signal while the lagging‐edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First‐In‐First‐Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network‐on‐Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self‐timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D‐Type Flip‐Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features.

A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit. [ABSTRACT FROM AUTHOR]

The Atmospheric Remote‐Sensing Infrared Exoplanet Large‐survey (ARIEL) space mission is dedicated to the study of the exoplanets' atmosphere. To do so, the payload module is made of two instruments. The ARIEL InfraRed Spectrometer instruments is one them, it will perform spectroscopic measurements from the near‐infrared domain to the long‐wave infrared domain. The instrument relies on the use of two H1RG detectors. During early phases of instrument development dark current measurements have been done on an 8 μ$$ \mu $$m cutoff detector operated in window mode. These measurements revealed an unexpected level of dark current. This observation triggered a joint series of tests at the European Space Agency technical center and at the Astrophysics Department of the Atomic Energy Commission. As demonstrated in this paper, the excess of dark current originates from the collection, by the photosenstive layer, of light emitted by the source follower transistor of the pixel unit cell. This effect is referred as glow. Based on experimental results, this glow is studied as a function of the detector operating conditions (temperature, biases, timing diagram). These results also show that for the range of operating temperatures considered, the dark current performance of the detector is limited by the glow. [ABSTRACT FROM AUTHOR]

Variants of the circuitry of storage cells with analog-to-digital conversion in focal plane arrays (FPAs) of the long-wavelength IR range are considered. The necessity of a multiple increase in the charge capacity of the storage cell to improve the threshold characteristics of the FPA is substantiated. A new version of the storage cell with analog-to-digital conversion, which has several advantages in comparison with analogues (high linearity, low consumption, and low noise) is proposed. The results of the study of a test crystal of a CMOS integrated readout circuit manufactured using the HCMOS8D technology of Mikron JSC with a design standard of 0.18 micrometers are presented. [ABSTRACT FROM AUTHOR]

Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today's high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided. [ABSTRACT FROM AUTHOR]

Abstract A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.

One of the threats to nanometric CMOS analog circuit reliability is circuit performance degradation due to transistor aging. To extend circuit operating life, the bias of the main devices within the circuit must be adjusted while the aging degradation process affects them by using a monitor circuit that tracks the evolution of the circuit performance. In this paper, we propose the use of DC temperature measurements in the proximity of the circuit to perform the monitoring of circuit performance degradation and as an observable variable to adjust the bias of the main devices to restore the degraded performance to the original values. To this end, we present experimental results obtained from nine samples of a standard CMOS integrated circuit containing a high-frequency class-A power amplifier and a differential temperature sensor. After accelerated aging, the gain of the amplifier is degraded up to 50%. We propose two different procedures to perform DC temperature measurements that allow tracking of the amplifier gain degradation due to aging and, by uniquely observing temperature readings, automatically set a new bias for the amplifier devices that restores the original amplifier gain. Whereas one of the procedures is able to restore the gain up to a certain limit, the second allows full gain restoration. [ABSTRACT FROM AUTHOR]

Noninvasive remote monitoring of hemodynamic variables is essential in optimizing treatment opportunities and predicting rehospitalization in patients with congestive heart failure. The objective of this study is to develop a wearable bioimpedance-based device, which can provide continuous measurement of cardiac output and stroke volume, as well as other physiological parameters for a greater prognosis and prevention of congestive heart failure. The bioimpedance system, which is based on a robust and cost-effective measuring principle, was implemented in a CMOS application specific integrated circuit, and operates as the analog front-end of the device, which has been provided with a radio-frequency section for wireless communication. The operating parameters of the proposed wearable device are remotely configured through a graphical user interface to measure the magnitude and the phase of complex impedances over a bandwidth of 1 kHz to 1 MHz. As a result of this study, a cardiac activity monitor was implemented, and its accuracy was evaluated in 33 patients with different heart diseases, ages, and genders. The proposed device was compared with a well-established technique such as Doppler echocardiography, and the results showed that the two instruments are clinically equivalent. [ABSTRACT FROM AUTHOR]

In this work, a tunable pseudo-resistor was designed, simulated, and tested using a 0.35 µm CMOS technology. The proposal used a compact voltage bias circuit free of body-effect, allowing a constant resistance value over the pseudo-resistor's dynamic range, improving its linearity. A fabricated cell was characterized providing a resistance value from 300 kΩ to 10 GΩ with a THD from <2.5% to 1 GΩ. Additionally, the pseudo-resistor was incorporated into a high-pass OTA filter showing a THD below 0.2% for input voltages in the range ≤ 0.3 Vp. The simulations were compared with experimental measurements in a CMOS-fabricated cell, which verified the proposal's feasibility. [ABSTRACT FROM AUTHOR]

Complementary metal‐oxide‐semiconductor (CMOS) field‐effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µe than silicon but suffers from a much lower hole mobility µh (µe/µh = 80), thus unsuited to CMOS application with a single material. Through the accurate ab initio quantum‐transport simulations, the performance gap between the NMOS and PMOS is significantly narrowed is predicted and even vanished in the sub‐2‐nm‐diameter gate‐all‐around (GAA) InAs nanowires (NW) FETs because the inversion of the light and heavy hole bands occurs when the diameter is shorter than 3 nm. It is further proposed several feasible strategies for further improving the performance symmetry in the GAA InAs NWFETs. Short‐channel effects are effectively depressed in the symmetric n‐ and p‐type GAA InAs NWFETs till the gate length is scaled down to 2 nm according to the standards of the International Technology Roadmap for Semiconductors. Therefore, the ultrasmall GAA InAs NWFETs possess tremendous prospects in CMOS integrated circuits. [ABSTRACT FROM AUTHOR]

A survey on ultra-wideband complementary metal-oxide semiconductor (CMOS) power amplifiers for wireless body area network (WBAN) applications is presented in this paper. Formidable growth in the CMOS integrated circuits technology enhances the development in biomedical manufacture. WBAN is a promising mechanism that collects essential data from wearable sensors connected to the network and transmitted it wirelessly to a central patient monitoring station. The ultra-wideband (UWB) technology exploits the frequency band from 3.1 to 10.6 GHz and provides no interference to other communication systems, low power consumption, low-radiated power, and high data rate. These features permit it to be compatible with medical applications. The demand target is to have one transceiver integrated circuit (IC) for WBAN applications, consequently, UWB is utilized to decrease the hardware complexity. The power amplifier (PA) is the common electronic device that employing in the UWB transmitter to boost the input power to the desired output power and then feed it to the antenna of the transmitter. The advance in the design and implementation of ultra-wideband CMOS power amplifiers enhances the performance of the UWB-transceivers for WBAN applications. A review of recently published CMOS PA designs is reported in this paper with comparison tables listing wideband power amplifiers' performance. [ABSTRACT FROM AUTHOR]

Over the past decade, significant progress in quantum technologies has been made, and hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant, and/or extensible systems than would be otherwise feasible. In this article—written by a consortium of early contributors to the field—we provide a review of some of the early integrated circuits for the quantum information sciences. Complementary metal--oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) integrated circuits for nuclear magnetic resonance, nitrogen-vacancy-based magnetometry, trapped-ion-based quantum computing, superconductor-based quantum computing, and quantum-dot-based quantum computing are described. In each case, the basic technological requirements are presented before describing proof-of-concept integrated circuits. We conclude by summarizing some of the many open research areas in the quantum information sciences for CMOS designers.

Abstract This article presents the design and optimisation of a sub‐1 GHz class‐F ultra‐low power (ULP) power amplifier (PA) in 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. An envelope tracking (ET) supply biasing technique is adopted to improve the efficiency of class‐F PA. The ET consist of a pre‐amp right before the detector in order to enhance the efficiency and save adequate amount of dc power consumption. The PA consists of two cascode cells terminated as class‐F with gate‐to‐drain feedback in order to enhance linearity and limit any harmonic component from the input signal. The novel design consumes a dc power of 3.75 mW, power added efficiency of 37.1%, operating at 915–925 MHz unlicensed band and total saturated output power of 22 dBm including 14 dBm power gain at PA, which qualifies under long‐range low power wireless local area network IEEE 802.11ah standard. The inductor‐less design for ET supply bias reduces the chip layout size to 0.13 mm2 only.

The rapid advancements of CMOS integrated circuits technologies lead designers to cascade structures and avoiding cascode amplifiers. As a result, frequency compensation becomes the most important issue since multi-stage amplifiers are highly potential to instability. Here in this work, two differential stages are exploited to form frequency compensation network. These stages realize four Miller loops and share each Miller capacitor in two loops simultaneously. This intensifies Miller effect to improve frequency response due to pole-zero cancellation. The proposed three stage amplifier is modeled symbolically via a transfer function (TF) while 0.18um CMOS technology is used for circuit simulation. Good agreement between theoretical calculation and simulation results shows validity and accuracy of the TF. Also ample simulations are performed to exhibit the proposed amplifier performance against parameters mismatches. The proposed three stage amplifier expresses 105 dB as DC-gain, 4.8 MHz as Gain Band Width and 72 degree as Phase Margin. The amplifier consumes 360 uW as power consumption. This performance obviously is an improvement of Nested Miller Compensation (NMC) while Figure of Merits (FoMs) are enhunced. [ABSTRACT FROM AUTHOR]

A low‐power negative‐positive‐negative (NPN)‐based bandgap voltage reference (BGR) over an ultra‐wide temperature range is presented. The conventional NPN‐based BGRs cannot maintain a low‐temperature coefficient (TC) with low power consumption in an ultra‐wide temperature range due to its inherent reverse junction saturation current of NPN bipolar junction transistors (BJT) in the high‐temperature range. This work introduces a new NPN‐based BGR unaffected by such saturation current. Based on Vanguard International Semiconductor Corporation (VIS) 0.18 μm/0.15 μm complementary metal oxide semiconductor (CMOS) Bipolar‐CMOS‐DMOS (BCD) process, the BGR receives the best 1.25‐mV deviation over the temperature range of −40°C to 150°C, much less than 38.5 mV from Brokaw‐type BGR. Meanwhile, the proposed BGR with the stacked NPNs for higher output voltage was fabricated. It consumes about 2 uA from a 5‐V power supply, and its average temperature coefficient is 14.89 ppm/°C. Also, the average line sensitivity is 0.039%/V. [ABSTRACT FROM AUTHOR]

In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self‐timing CMOS first‐edge take‐all (FETA) circuit architecture, which examines two overlapping signals' requests, and outputs only the leading‐edge signal while the lagging‐edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First‐In‐First‐Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network‐on‐Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self‐timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D‐Type Flip‐Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features. [ABSTRACT FROM AUTHOR]

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications. [ABSTRACT FROM AUTHOR]

Low-power current integrating infinite impulse response filter having flat-passband for sensor read-out integrated circuit is proposed. In a current integrating filter, passband flatness degradation is inevitable due to sinc-like filtering characteristics. In this paper, by proposing a high order infinite impulse response filter architecture, flat-passband characteristic can be achieved. By implementing a filter architecture with a flat passband, the required sampling frequency can be lowered, which in turn can reduce power consumption. Moreover, the proposed high order infinite impulse response filter architecture has a high degree of freedom on adjusting input sample weights. The proposed integrated circuit is implemented in TSMC 65-nm CMOS process and operated on 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

A true‐time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1–5 GHz applications is presented. Process variations, ageing effects, field variations, and other non‐idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor‐less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non‐idealities, while delay variation improves more than 3× times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S11 and S22 parameters are lower than −10 dB in the 1–5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. [ABSTRACT FROM AUTHOR]

The design of memristor-based electronic circuits and devices gives researchers opportunities for the engineering of CMOS-memristor-based electronic integrated chips with ultra-high density and various applications. Metal-oxide memristors have good compatibility with the present CMOS integrated circuits technologies. The analysis of new electronic circuits requires suitable software and fast-functioning models. The main purpose of this paper is to propose the application of several modified, simplified, and improved metal-oxide memristor models in electronic devices and provide a comparison of their behavior, basic characteristics, and properties. According to this, LTSPICE is utilized in this paper because it is a free software product with good convergence. Several memristor-based electronic circuits, such as non-volatile passive and hybrid memory crossbars, a neural network, and different reconfigurable devices–filters, an amplifier, and a generator are analyzed in the LTSPICE environment, applying several standards and modified metal-oxide memristor models. After a comparison of the operation of the considered schemes, the main advantages of the modified metal-oxide memristor models, according to their standard analogs, are expressed, including fast operation, good accuracy, respectable convergence, switching properties, and successful applicability in complex electronic circuits. [ABSTRACT FROM AUTHOR]

With the progress of the semiconductor process miniaturization, delay degradation by aging increases and threatens the reliability of the fabricated chips. The amount of the delay degradation is known to be circuit and workload dependent, but previous evaluations are based on the simulations, and the delay degradation measurement of real circuit under realistic workload has not been reported yet. The authors have already proposed a real circuit delay measurement method, which can achieve enough accuracy to measure the circuit and workload dependent delay degradation. This paper reports the measurement results utilizing the proposed method. The measured degradation is approximated by the log and the power-law functions. Methods to correct the environmental condition variation effect, and to mitigate the approximation inaccuracy caused by the random delay variation has been developed. The measurement results show large degradation amount variation, which can be attributed to the dependence on the circuits and the workloads. On the other hand, correlation of the degradation amount between different chips is rather weak. This leads to the conclusion that the temperature dependence and the random variation of the degradation amount between different transistors have large effect on the degradation amount variation. [ABSTRACT FROM AUTHOR]

The Nanoelectromechanical (NEM) switches are a promising candidate to overcome the physical limitations of the complementary metal‐oxide‐semiconductor (CMOS) switches due to their quasi‐zero leakage behavior, sub‐thermal switching, and suitability to operate in harsh environments. The main obstacles affecting NEM switches are their irreversible switch‐contact stiction, the large switching voltage, and its hysteretic loop. In this study, the irreversible static friction is overcome by employing the weak van der Waals (vdW) bonding of graphene‐hexagonal boron nitride (hBN) contact in the Graphene NEM (GNEM) switches. These vdW switches show sub‐0.5 V switching voltage with an ON/OFF ratio higher than 105 and nearly zero hysteretic window characteristics with a high endurance of over 50 000 switching cycles. These remarkable performances are achieved by exploiting graphene's monolayer thickness, high Young's modulus, cubic mechanical restoring force, and low vdW binding energy characteristics. As chemical vapor deposition graphene and hBN are used in these GNEM switches, it exhibits the prospect for large‐scale graphene NEM system applications. These GNEM switches can be potentially used in ultralow‐power CMOS integrated circuits, hybrid NEM‐CMOS systems, logic devices, NEM resonator mass sensing, and single‐molecule sensors. [ABSTRACT FROM AUTHOR]

A gain-enhanced low hardware complexity charge-domain read-out integrated circuit is implemented. By adopting a sampled charge redistribution technique, low hardware complexity is achieved, which in turn saves 10% of the die area and provides 33% gain enhancement compared to the conventional topology. In particular, a charge-domain discrete-time filter with inherent reconfigurability is a key building block, which can also act as an anti-aliasing filter before the analog-to-digital converter. The measurement results show good agreement with the intended frequency response. The proposed filter is implemented using a 0.11 μm CMOS process and occupies 0.15 mm2. [ABSTRACT FROM AUTHOR]

Inductor-less CMOS filters with bandwidth exceeding several GHz are required in high-speed data converter applications. This paper introduces two complementary biquad filters, one N-based and the other P-based, utilizing the well-established flipped voltage follower (FVF) stage. These filters exhibit more than 7 GHz cut-off frequency and a low power consumption of 0.54 mW/pole for the N-type biquad, and 0.3 mW/pole for the P-type one, demonstrating impressive figures-of-merit (FOMs) even considering bandwidth and dynamic range. The implementation of these biquads in the STMicroelectronics FD-SOI 28-nm CMOS process, along with extensive simulations, ensures stable performance under process, supply voltage and temperature (PVT) variations and mismatches, as confirmed by post-layout simulations. Notably, the area occupied by each biquad is merely 246 μm2 for N-type biquad and 193 μm2 for P-type, marking one of the smallest footprints in the existing literature. The achieved figures-of-merit are noteworthy, showcasing excellent power efficiency, minimal area occupation, and commendable dynamic range. [ABSTRACT FROM AUTHOR]