Search

CMOS image sensors in optical payloads are susceptible to single-event effects when irradiated by high-energy protons from the spatial radiation environment. Single-event transients in images primarily manifest as bright spots, and the characteristics of transient bright spots generated under different incident conditions exhibit some differences. In this study, we conducted proton irradiation experiments on CMOS image sensors at different energy levels and incident angles. The characteristics of single-event transient bright spots generated under various incident conditions were extracted and analysed in detail. Furthermore, the abnormal phenomena of different functional modules of CMOS image sensors observed during proton irradiation experiments were investigated. The results of this study establish the foundation for classifying the detected targets and transient bright spots, indicating that the validation of CMOS image sensor radiation reliability should account for functional abnormalities resulting from high-energy proton irradiation. [ABSTRACT FROM AUTHOR]

Silicon is the dominant material in complementary metal-oxide-semiconductor (CMOS) imaging devices because of its outstanding electrical and optical properties, well-established fabrication methods, and abundance in nature. However, with the ongoing trend toward electronic miniaturization, which demands smaller pixel sizes in CMOS image sensors, issues, such as crosstalk and reduced optical efficiency, have become critical. These problems stem from the intrinsic properties of Si, particularly its low absorption in the long wavelength range of the visible spectrum, which makes it difficult to devise effective solutions unless the material itself is changed. Recent advances in optical metasurfaces have offered new possibilities for solving these problems. In this study, we propose color arrestor pixels (CAPs) as a new class of color image sensors whose composite spectral responses directly mimic those of the human eye. The key idea is to employ linearly independent combinations of standardized color matching functions. These new basis functions allow our device to reproduce colors more accurately than the currently available image sensors with red-green-blue filters or other metasurface-based sensors, demonstrating an average CIEDE2000 color difference value of only 1.79 when evaluating 24 colors from the Gretag-Macbeth chart under standard illuminant D65. Owing to their high fidelity to the human eye response, CAPs consistently exhibit exceptional color reproduction accuracy under various spectral illumination compositions. With a small footprint of 860 nm height and 221 nm full-color pixel pitch, the CAPs demonstrated high absorption efficiencies of 79 %, 81 %, and 63 % at wavelengths of 452 nm, 544 nm, and 603 nm, respectively, and good angular tolerance. With such a high density of pixels efficiently capturing accurate colors, CAPs present a new direction for optical image sensor research and their applications. [ABSTRACT FROM AUTHOR]

In this study, we developed and demonstrated a millimeter-wave electric field imaging system using an electro-optic crystal and a highly sensitive polarization measurement technique using a polarization image sensor, which was fabricated using a 0.35-µm standard CMOS process. The polarization image sensor was equipped with differential amplifiers that amplified the difference between the 0° and 90° pixels. With the amplifier, the signal-to-noise ratio at low incident light levels was improved. Also, an optical modulator and a semiconductor optical amplifier were used to generate an optical local oscillator (LO) signal with a high modulation accuracy and sufficient optical intensity. By combining the amplified LO signal and a highly sensitive polarization imaging system, we successfully performed millimeter-wave electric field imaging with a spatial resolution of 30 × 60 µm at a rate of 1 FPS, corresponding to 2400 pixels/s. [ABSTRACT FROM AUTHOR]

The resolution of Si complementary metal–oxide–semiconductor field-effect transistor (C-MOSFET) image sensors (CISs) has been intensively enhanced to follow the technological revolution of smartphones, AI devices, autonomous cars, robots, and drones, approaching the physical and material limits of a resolution increase in conventional Si CISs because of the low quantum efficiency (i.e., ~40%) and aperture ratio (i.e., ~60%). As a novel solution, a hybrid organic–Si image sensor was developed by implementing B, G, and R organic photodiodes on four n-MOSFETs for photocurrent sensing. Photosensitive organic donor and acceptor materials were designed with cost-effective small molecules, i.e., the B, G, and R donor and acceptor small molecules were Coumarin6 and C_60, DMQA and MePTC, and ZnPc and TiOPc, respectively. The output voltage sensing margins (i.e., photocurrent signal difference) of the hybrid organic–Si B, G, and R image sensor pixels presented results 17, 11, and 37% higher than those of conventional Si CISs. In addition, the hybrid organic–Si B, G, and R image sensor pixels could achieve an ideal aperture ratio (i.e., ~100%) compared with a Si CIS pixel using the backside illumination process (i.e., ~60%). Moreover, they may display a lower fabrication cost than image sensors because of the simple image sensor structure (i.e., hybrid organic–Si photodiode with four n-MOSFETs). [ABSTRACT FROM AUTHOR]

With the application of stitching technology in CMOS image sensors of large arrays, the traditional clock tree synchronization design method is not suitable for the two-side drive circuit of pixel arrays, resulting in the serious problems of DC penetration and bad row of the two-side drive of pixel arrays in the same row. In this paper, in terms of the idea of self-adaptive correction on chip, a consistency driving method which can be applied to stitching pixel arrays is proposed. The method can be adapted to the change of chip working environment, and has the characteristics of simple structure and high reliability. Based on 55 nm technology, the present method is applied and verified in a large array CMOS image sensor with 150M pixel size and 77 mm×84 mm chip area of 12 288×12 288. The experimental results show that, under a master clock of 500 MHz and a row clock of 125 kHz, the inconsistency of bilateral row drive is reduced from 17.5 ns to less than 2 ns (one clock period), and the consistency is improved by above than 9 times, ensuring that the frame frequency of the super-array image sensor with a scale of 100 million pixels can reach more than 10 frames.

With the electromagnetic environment becoming increasingly complex, it is crucial to address the risk posed by electromagnetic pulse, which critically impairs the performance and reliability of electronic systems based on complementary metal oxide semiconductor (CMOS) image sensors. In this context, research on the failure types of CMOS image sensors in a high-power electromagnetic environment, caused by strong electromagnetic pulses and the rapid evaluation method of interference immunity, has garnered significant interest. This paper conducts electromagnetic pulse simulation experiments on CMOS image sensors to first study their failure types, such as image abnormalities and functional interruption, and then identify the corresponding failure criteria. Furthermore, this study builds on the small sample test evaluation method to investigate the interference threshold of functional interruptions in CMOS image sensors by calculating the failure probability at different field strengths. The obtained data were combined with the Weibull distribution function for fitting, the results of which found the interference threshold to be at 40.4 kV/m. The findings of this study provide a basis for evaluating the survivability of CMOS image sensors and their associated reinforcement technology in high-power electromagnetic environments.

Summary This paper introduces an area‐effective and low‐power readout circuit structure tailored for high dynamic range (HDR) CMOS image sensors (CISs) utilizing dual conversion gain (DCG) imaging technology. A switched capacitor amplifier, which is applied at the comparator input port of the column‐parallel single‐slope analog‐to‐digital converter (SS ADC), is proposed to compensate for the charge injection and clock feed‐through introduced when the pixel switches between high conversion gain (HCG) and low conversion gain (LCG) modes. The proposed SS ADC is supplemented by the integration of a configurable counter, and the counter is specifically crafted for performing the A/D conversion of the readout voltage within a DCG pixel. Compared to the conventional DCG readout circuit, the proposed readout circuit use only one ADC for A/D conversion of HCG signals and LCG signals, which greatly reduces the area and power consumption of the readout circuit. Simulation results under 110 nm CMOS technology illustrate that the proposed 10‐bit SS ADC has a DNL of +0.78/−0.91 LSB and an INL of +1.91/−1.69 LSB, with a SNR of 57.2 dB and a SNDR of 55.95 dB, corresponding to an ENOB of 9 bits. The power consumption of the proposed SS ADC is 56.4 μW per column with a conversion time of 12 μs, and the simulation results show that the power consumption is 23.35% lower than the conventional structure and the area is saved by 24.69%. [ABSTRACT FROM AUTHOR]

This paper presents an innovative readout scheme that utilizes a pair of differential‐clocks‐assisted time‐to‐digital converter (DCA‐TDC) in CMOS image sensors (CISs). The DCA‐TDC utilizes only half the number of ordinary TDC delay chain units by employing a binary‐weighted search algorithm to determine the most significant bit (MSB) for fine quantization of a single‐slope analog‐to‐digital converter (SS ADC). Additionally, the layout area and dynamic power introduced by the improved DCA‐TDC delay chain are halved compared to an ordinary TDC delay chain. The proposed SS ADC is designed and simulated using the 0.11  μ$$ \upmu $$m standard CMOS proces, achieving an 11‐bit ADC with a column‐level power consumption of 65.4  μ$$ \upmu $$W, and a row conversion time of 2.72  μ$$ \upmu $$s, within a design environment featuring an analog voltage of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and a temporal resolution of 500 ps. Furthermore, this design achieves an effective number of bits (ENOB) of 10.71 and a figure of merit (FoM) of 110.5 fJ/step. By interpolating a DCA‐TDC, the quantization speed is enhanced compared to traditional SS ADCs, presenting an effective solution for high‐frame‐rate CIS implementations. [ABSTRACT FROM AUTHOR]

CMOS image sensor (CIS) semiconductor products are integral to mobile phones and photographic devices, necessitating ongoing enhancements in efficiency and quality for superior photographic outcomes. The presence of white pixels serves as a crucial metric for assessing CIS product performance, primarily arising from metal impurity contamination during the wafer production process or from defects introduced by the grinding blade process. While immediately addressing metal impurity contamination during production presents challenges, refining the handling of defects attributed to grinding blade processing can notably mitigate white pixel issues in CIS products. This study zeroes in on silicon wafer manufacturers in Taiwan, analyzing white pixel defects reported by customers and leveraging machine learning to pinpoint and predict key factors leading to white pixel defects from grinding blade operations. Such pioneering practical studies are rare. The findings reveal that the classification and regression tree (CART) and random forest (RF) models deliver the most accurate predictions (95.18%) of white pixel defects caused by grinding blade operations in a default parameter setting. The analysis further elucidates critical factors like grinding load and torque, vital for the genesis of white pixel defects. The insights garnered from this study aim to arm operators with proactive measures to diminish the potential for customer complaints. [ABSTRACT FROM AUTHOR]

CMOS image sensor (CIS) plays a crucial role in diverse optical applications by facilitating the capture of images in the visible and near-infrared spectra. The enhancement of image resolution in CIS by an increase in pixel density is becoming more significant and realizable with the recent progress of nanofabrication. However, as pixel size decreases towards the diffraction limit, there is an inevitable trade-off between the scale-down of pixel size and the enhancement of optical sensitivity. Recently, to overcome this, an entirely new concept of spectral sensing using a nanophotonic-based color router has been proposed. In this work, we present a metasurface-based spectral router to effectively split the spectrum from visible to near-infrared and redirect through the four optical channels to the targeted pixel surfaces. We optimize the metasurface that simultaneously controls the phases of the transmitted light of targeted spectra, i.e. red (R), green (G), blue (B), and near-infrared (NIR), which is the largest number of channels reported based on a single layered metasurface and has an optical efficiency that surpasses the efficiency of conventional color filter systems. [ABSTRACT FROM AUTHOR]

We explore the use of smartphones to decode data transmitted from LEDs to smartphone cameras in visible light communication (VLC) applied to indoor positioning applications. The LEDs—modified to enable rapid on-off keying—transmit identification codes or optically encoded location data imperceptible to human perception. Equipped with a camera, the smartphone employs a single framed image to detect the presence of the luminaires in the image, decode their transmitted identifiers or locations, and determine the smartphone's position and orientation relative to the luminaires. The camera captures and processes images continuously. The following fundamental issues are addressed in this research: (i) analyzing the camera parameters on smartphones that affect data decoding results; (ii) exploiting the rolling shutter effect of the CMOS image sensor to receive multiple bits of data encoded in the optical communication line with a single frame shot; (iii) advancing research in developing algorithms to process data from multiple LEDs simultaneously. We conduct experiments to evaluate and analyze feasibility, as well as the challenges of the design, through scenarios varying in distance, transmission frequency, and data length. [ABSTRACT FROM AUTHOR]

In this work, an exhaustive analysis of the partial discharges that originate in the bubbles present in dielectric mineral oils is carried out. To achieve this, a low-cost, high-resolution CMOS image sensor is used. Partial discharge measurements using that image sensor are validated by a standard electrical detection system that uses a discharge capacitor. In order to accurately identify the images corresponding to partial discharges, a convolutional neural network is trained using a large set of images captured by the image sensor. An image classification model is also developed using deep learning with a convolutional network based on a TensorFlow and Keras model. The classification results of the experiments show that the accuracy achieved by our model is around 95% on the validation set and 82% on the test set. As a result of this work, a non-destructive diagnosis method has been developed that is based on the use of an image sensor and the design of a convolutional neural network. This approach allows us to obtain information about the state of mineral oils before breakdown occurs, providing a valuable tool for the evaluation and maintenance of these dielectric oils. [ABSTRACT FROM AUTHOR]

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an "on-the-ramp processing" technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW. [ABSTRACT FROM AUTHOR]

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy. [ABSTRACT FROM AUTHOR]

We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 μm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively. [ABSTRACT FROM AUTHOR]

Summary: Correlated multiple sampling (CMS) technique is often used to reduce random noise in complementary metal oxide semiconductor (CMOS) image sensor, but as the number of samples increases, the suppression of 1/f noise by standard CMS based on averaging sampling gradually decreases. Therefore, in this paper, a 1/f noise optimized correlated multiple sampling (NOCMS) technique based on differentiated sampling weights is proposed. Transfer functions of standard CMS and NOCMS for analyzing the suppression effect of random noise respectively are derived based on the Fourier transform theory. And NOCMS shows a dramatic advantage in the suppression of 1/f noise. In addition, a circuit structure based on single‐slope analog‐to‐digital converter (SSADC) for implementing NOCMS is suggested. Ramp generator provides multiple sets of ramps with different slopes to quantify the reset and signal voltages of pixel output. Sampling weights are increased with the decrease of ramp slopes. The last reset and first signal values are weighted more due to their potentially higher correlations which highlights the principle of assigning weights. Simulation results under 110 nm CMOS technology illustrate that the input‐referred random noise is 142.9 μ V rms under standard CMS and 120.9 μ V rms under NOCMS when the number of samples equals 8. The noise reduction effect is improved by 15%. NOCMS makes it possible to further reduce 1/f noise of CMOS image sensor. [ABSTRACT FROM AUTHOR]

The potential of VLP is increasing with the rise of indoor mobile machine applications. In this paper, a 3D indoor VLP system based on machine learning and optical camera communications is presented. The system uses electronically controlled LED luminaires as reference points and a rolling shutter CMOS sensor as the receiver. The LED luminaires are modulated using On-Off Keying with unique frequencies. YOLOv5 is used for classification and estimation of the position of each LED luminaire in the image. The pose of the receiver is estimated using a perspective-n-point algorithm. The system was validated using a real-world sized setup containing eight LED luminaires, and achieved an average positioning error of 3.5 cm. The average time to compute the camera pose is approximately 52 ms, which makes it suitable for real-time positioning. To the best of our knowledge, this is the first application of the YOLOv5 algorithm in the field of VLP for indoor environments.

The resolution of Si complementary metal–oxide–semiconductor field-effect transistor (C-MOSFET) image sensors (CISs) has been intensively enhanced to follow the technological revolution of smartphones, AI devices, autonomous cars, robots, and drones, approaching the physical and material limits of a resolution increase in conventional Si CISs because of the low quantum efficiency (i.e., ~40%) and aperture ratio (i.e., ~60%). As a novel solution, a hybrid organic–Si image sensor was developed by implementing B, G, and R organic photodiodes on four n-MOSFETs for photocurrent sensing. Photosensitive organic donor and acceptor materials were designed with cost-effective small molecules, i.e., the B, G, and R donor and acceptor small molecules were Coumarin6 and C_60, DMQA and MePTC, and ZnPc and TiOPc, respectively. The output voltage sensing margins (i.e., photocurrent signal difference) of the hybrid organic–Si B, G, and R image sensor pixels presented results 17, 11, and 37% higher than those of conventional Si CISs. In addition, the hybrid organic–Si B, G, and R image sensor pixels could achieve an ideal aperture ratio (i.e., ~100%) compared with a Si CIS pixel using the backside illumination process (i.e., ~60%). Moreover, they may display a lower fabrication cost than image sensors because of the simple image sensor structure (i.e., hybrid organic–Si photodiode with four n-MOSFETs).

In this study, we developed and demonstrated a millimeter-wave electric field imaging system using an electro-optic crystal and a highly sensitive polarization measurement technique using a polarization image sensor, which was fabricated using a 0.35-µm standard CMOS process. The polarization image sensor was equipped with differential amplifiers that amplified the difference between the 0° and 90° pixels. With the amplifier, the signal-to-noise ratio at low incident light levels was improved. Also, an optical modulator and a semiconductor optical amplifier were used to generate an optical local oscillator (LO) signal with a high modulation accuracy and sufficient optical intensity. By combining the amplified LO signal and a highly sensitive polarization imaging system, we successfully performed millimeter-wave electric field imaging with a spatial resolution of 30×60 µm at a rate of 1 FPS, corresponding to 2400 pixels/s.

This paper presents a novel technique for dark current compensation of a CMOS image sensor (CIS) by using in-pixel temperature sensors (IPTSs) over a temperature range from −40 °C to 90 °C. The IPTS makes use of the 4T pixel as a temperature sensor. Thus, the 4T pixel has a double functionality, either as a pixel or as a temperature sensor. Therefore, the dark current compensation can be carried out locally by generating an artificial dark reference frame from the temperature measurements of the IPTSs and the temperature behavior of the dark current (previously calibrated). The artificial dark current frame is subtracted from the actual images to reduce/cancel the dark signal level of the pictures. In a temperature range from −40 °C to 90 °C, results show that the temperature sensors have an average temperature coefficient (TC) of 1.15 mV/°C with an inaccuracy of ±0.55 °C. Parameters such as conversion gain, gain of the amplifier, and ADC performance have been analyzed over temperature. The dark signal can be compensated in the order of 80% in its median value, and the nonuniformity is reduced in the order of 55%. [ABSTRACT FROM AUTHOR]

In this paper, the light intensity and charge holding time dependence of pinned photodiode (PD) full well capacity (FWC) are studied for our pixel structure with a buried overflow path under the transfer gate. The formulae for PDFWC derived from a simple analytical model show that the relation between light intensity and PDFWC is logarithmic because PDFWC is determined by the balance between the photo-generated current and overflow current under the bright condition. Furthermore, with using pulsed light before a charge holding operation in PD, the accumulated charges in PD decrease with the holding time due to the overflow current, and finally, it reaches equilibrium PDFWC. The analytical model has been successfully validated by the technology computer-aided design (TCAD) device simulation and actual device measurement. [ABSTRACT FROM AUTHOR]

We present the first reported use of a CMOS-compatible single photon avalanche diode (SPAD) array for the detection of high-energy charged particles, specifically pions, using the Super Proton Synchrotron at CERN, the European Organization for Nuclear Research. The results confirm the detection of incident high-energy pions at 120 GeV, minimally ionizing, which complements the variety of ionizing radiation that can be detected with CMOS SPADs. [ABSTRACT FROM AUTHOR]

We are developing a 70-dB SNR 1,000 frame-per-second absorption imaging system, and it enables us to visualize gas concentration distribution in a vacuum chamber for semiconductor manufacturing. This article presents the measurement and analysis of temporal and steady-state NO2 gas concentration distribution using this system. In the steady-state gas flow condition which supplied from a shower plate, the spectrometry of NO2 gas shows a good linear relationship between the absorbance and the partial pressure with the system. The system enables the visualization of steady-state of NO2 gas concentration distribution which supplied from one hole of shower plate, and the results are compared with simulation to discuss the reasonability of the measurement. The system also enables to visualize the temporal NO2 gas concentration distribution supplied from a single nozzle, and the advantages of the system’s features of 70-dB and 1,000 fps are discussed. [ABSTRACT FROM AUTHOR]

We present a 2D-stitched, 316MP, 120FPS, high dynamic range CMOS image sensor with 92 CML output ports operating at a cumulative date rate of 515 Gbit/s. The total die size is 9.92 cm × 8.31 cm and the chip is fabricated in a 65 nm, 4 metal BSI process with an overall power consumption of 23 W. A 4.3 µm dual-gain pixel has a high and low conversion gain full well of 6600e- and 41,000e-, respectively, with a total high gain temporal noise of 1.8e- achieving a composite dynamic range of 87 dB. [ABSTRACT FROM AUTHOR]

In this study, we developed a miniaturized observation system for rat brain imaging using an implantable imager. A small data-acquisition device was designed to be mounted on the back of an adult rat, reducing the disturbance to the output of the imager caused by a long cable. With a weight of approximately 6.8 g, the movement of adult rats with an average weight of 200 g was unrestricted. The readout characteristics were evaluated at the light level. The in vivo experiments were performed using mice and freely moving rats. Using the developed data analysis pipeline, blood flow in the vessels was observed. [ABSTRACT FROM AUTHOR]

Optical and electrophysiological measurements help us understand mouse brain functions. One type of device available for optical measurements is an implantable complementary metaloxide-semiconductor (CMOS) image sensor (ICIS). However, an ICIS alone cannot directly measure the electrical signals emitted by mouse brain neurons. Considering this limitation, we have developed an implantable multimodal sensor that can simultaneously make optical and electrophysiological measurements of the neural activity in the brains of mice. The proposed device integrates a CMOS image sensor and a neural amplifier with a recording electrode into a single chip, making it no more invasive than a conventional implantable CMOS image sensor. The proposed device is based on a 0.35-µm CMOS standard process and occupies an area of 0.50 × 5.0 mm2. Furthermore, a hybrid filter is fabricated on the imaging pixel array to remove the excitation light and selectively detect fluorescence. From electrophysiological measurements, we confirm that the neural amplifier features a mid-band gain of 39 dB from 500 mHz to 4 kHz, which is the bandwidth that includes local field and action potentials. Crosstalk noise is observed because of the digital signal used to control the image sensor. However, in vivo experiments demonstrate that the device is capable of simultaneously measuring and processing optical and electrophysiological signals when the amplitude spectrum has a peak of less than 1 µV. [ABSTRACT FROM AUTHOR]

A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal–oxide–semiconductor (CMOS) image sensors (APS), assuming stationary conditions was recently presented in this journal. In this study, we extend the stochastic approach to non-stationary conditions. Non-stationary conditions occur in gated imaging applications. This new stochastic model, which is based on fundamental physical considerations, enlightens us with new insights into gated CMOS imaging, regardless of the sensor. The Signal-to-Noise Ratio (SNR) is simulated, allowing optimized performance. The conversion gain should be determined under stationary conditions. [ABSTRACT FROM AUTHOR]

CMOS image sensor (CIS) semiconductor products are integral to mobile phones and photographic devices, necessitating ongoing enhancements in efficiency and quality for superior photographic outcomes. The presence of white pixels serves as a crucial metric for assessing CIS product performance, primarily arising from metal impurity contamination during the wafer production process or from defects introduced by the grinding blade process. While immediately addressing metal impurity contamination during production presents challenges, refining the handling of defects attributed to grinding blade processing can notably mitigate white pixel issues in CIS products. This study zeroes in on silicon wafer manufacturers in Taiwan, analyzing white pixel defects reported by customers and leveraging machine learning to pinpoint and predict key factors leading to white pixel defects from grinding blade operations. Such pioneering practical studies are rare. The findings reveal that the classification and regression tree (CART) and random forest (RF) models deliver the most accurate predictions (95.18%) of white pixel defects caused by grinding blade operations in a default parameter setting. The analysis further elucidates critical factors like grinding load and torque, vital for the genesis of white pixel defects. The insights garnered from this study aim to arm operators with proactive measures to diminish the potential for customer complaints.

We explore the use of smartphones to decode data transmitted from LEDs to smartphone cameras in visible light communication (VLC) applied to indoor positioning applications. The LEDs—modified to enable rapid on-off keying—transmit identification codes or optically encoded location data imperceptible to human perception. Equipped with a camera, the smartphone employs a single framed image to detect the presence of the luminaires in the image, decode their transmitted identifiers or locations, and determine the smartphone’s position and orientation relative to the luminaires. The camera captures and processes images continuously. The following fundamental issues are addressed in this research: (i) analyzing the camera parameters on smartphones that affect data decoding results; (ii) exploiting the rolling shutter effect of the CMOS image sensor to receive multiple bits of data encoded in the optical communication line with a single frame shot; (iii) advancing research in developing algorithms to process data from multiple LEDs simultaneously. We conduct experiments to evaluate and analyze feasibility, as well as the challenges of the design, through scenarios varying in distance, transmission frequency, and data length.

We analyze several factors that affect the linear output range of CMOS image sensors, including charge transfer time, reset transistor supply voltage, the capacitance of integration capacitor, the n-well doping of the pinned photodiode (PPD) and the output buffer. The test chips are fabricated with 0.18 μm CMOS image sensor (CIS) process and comprise six channels. Channels B1 and B2 are 10 μm pixels and channels B3–B6 are 20 μm pixels, with corresponding pixel arrays of 1 × 2560 and 1 × 1280 respectively. The floating diffusion (FD) capacitance varies from 10 fF to 23.3 fF, and two different designs were employed for the n-well doping in PPD. The experimental results indicate that optimizing the FD capacitance and PPD design can enhance the linear output range by 37% and 32%, respectively. For larger pixel sizes, extending the transfer gate (TG) sampling time leads to an increase of over 60% in the linear output range. Furthermore, optimizing the design of the output buffer can alleviate restrictions on the linear output range. The lower reset voltage for noise reduction does not exhibit a significant impact on the linear output range. Furthermore, these methods can enhance the linear output range without significantly amplifying the readout noise. These findings indicate that the linear output range of pixels is not only influenced by pixel design but also by operational conditions. Finally, we conducted a detailed analysis of the impact of PPD n-well doping concentration and TG sampling time on the linear output range. This provides designers with a clear understanding of how nonlinearity is introduced into pixels, offering valuable insight in the design of highly linear pixels.

Summary: In this paper, a 256 × 256 CMOS image sensor is introduced in which the pixel signals are read and converted into digital data in a completely differential mode. This technique helps to obtain pixel signals with higher linearity and accuracy compared with conventional methods. Improving the linearity and accuracy of the image sensor has a direct impact on increasing the quality of the generated images. The simulation results of the proposed pixel readout circuit show that the THD, SINAD, SNR, and SFDR are 0.45%, 47 dB, 66 dB, and 46 dB, respectively. The voltage gain of the proposed readout circuit is about 1, causing it to read the photodetector signals more accurately than the conventional methods. A full differential single‐slope ADC with a working frequency of 50 Mhz has the task of converting the pixel signal to 10 bits of digital data. The total power consumption of a column of sensors is about 80 μW. All the circuits are designed and implemented using 0.18‐μm CMOS technology in Virtuoso and simulated by the SPECTRE. [ABSTRACT FROM AUTHOR]

High-energy particles in space often induce single event effects in CMOS image sensors, resulting in performance degradation and functional failure. This paper focuses on the formation and morphology of transient bright spots in CMOS image sensors and analyzes the formation process of transient bright spots by conducting heavy ion irradiation experiments to obtain the variation law of transient bright spots with heavy ion linear energy transfer values and background gray values; in addition, we classify the single event upset that occurred in the experiments according to the state of transient bright spots and extract the characteristics of different single event upsets. The failure mechanisms of different single event upsets are analyzed according to their characteristics and are combined with the information given by transient bright spots. This provides an essential reference for rapidly evaluating single event effects and the reinforcement design of CMOS image sensors. [ABSTRACT FROM AUTHOR]

The nuclear industry and other high-radiation environments often need remote monitoring equipment with advanced cameras to achieve precise remote control operations. CMOS image sensors, as a critical component of these cameras, get exposed to γ-ray irradiation while operating in such environments, which causes performance degradation that adversely affects camera resolution. This study conducted total ionizing dose experiments on CMOS image sensors and camera systems and thoroughly analyzed the impact mechanisms of the dark current, Full Well Capacity, and quantum efficiency of CMOS image sensors on camera resolution. A quantitative evaluation formula was established to evaluate the impact of Full Well Capacity and quantum efficiency of the CMOS image sensor on camera resolution. This study provides a theoretical basis for the evaluation of the radiation resistance of cameras in environments with strong nuclear radiation and the development of radiation-resistant cameras. [ABSTRACT FROM AUTHOR]

We fabricated Al/Al2O3/SiO2/Si and Al/HfO2/Si structures to optimize the passivation layer of a backside-illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS), with the key properties of the newly developed high- $k$ passivation layer analyzed via border traps, interface traps, and fixed charges. In the first experiment using Al2O3/SiO2 bilayer-based structures, different thicknesses of SiO2 were applied from 0 to 15 nm. The improvement in their properties was confirmed by applying forming gas annealing (FGA), a type of post-treatment, to all experimental systems. The first experiment results indicated that both the SiO2 layer and FGA were effective for chemical passivation. However, a tradeoff occurred in the degree of improvement of the interface trap density ( $\text{D}_{\mathrm {it}}$ ) and fixed-charge density ( $\text{Q}_{\mathrm {f}}$ ) according to the SiO2 layer thickness. Subsequently, in the second experiment using HfO2 single-layer-based structures, FGA improved the border trap to a relatively poor extent compared to the first experiment. Nevertheless, FGA improved the electrical characteristics of the HfO2 films without any side effects and results in optimal $\text{D}_{\mathrm {it}}$ and $\vert \text{Q}_{\mathrm {f}}/\text{q}\vert $ values of $2.59 \times 10^{11}$ eV $^{-1}$ cm $^{-2}$ and $1.00 \times 10^{12}$ cm $^{-2}$ , respectively, demonstrating its potential for the passivation layer in BSI CIS applications.

This article presents a high-performance, low-power analog convolutional neural network (CNN) circuit integrated into a CMOS image sensor (CIS) for face detection applications. The main block of the proposed in-column analog CNN circuits is an analog multiplication-and-accumulation (MAC) circuit consisting of an operational transconductance amplifier-based switched capacitor circuit enabling the programmable weight function. With the proposed MAC, a 3-layer analog CNN processor is implemented into the column-parallel readout circuit in conventional CIS. Furthermore, for low-power CNN operations, we use a low-resolution analog-to-digital converter with the proposed nonlinear quantization method resulting in an increase in the accuracy of face detection from 92.8% to 98.75% at 120 frame rates with 2.8 V/1.5 V supply voltage. A prototype sensor with $160\times120$ effective image resolution was fabricated using a 110 nm CMOS image sensor process. The measurement results showed that the maximum power consumption was 0.57 mW and 4.02 mW at 1 and 120 frame rates, respectively.

A lateral overflow integration capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensor can realize high-dynamic-range (HDR) imaging with combination of a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for electron-referred noise floor. However, LOFIC-CMOS image sensor requires a two-channel read-out chain for LCG and HCG signals whose polarities are inverted. In order to provide an area-efficient LOFIC-CMOS image sensor, a one-channel read-out chain that can process both HCG and LCG signals is presented in this paper. An up/down double-sampling circuit composed of an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals can reduce the area of the read-out chain by half compared to the conventional two-channel read-out chain. A test chip is fabricated in a 0.18 μ m CMOS process with a metal–insulator–metal (MIM) capacitor, achieving a readout noise of 130 μ V rms for the HCG signal and 1.19 V for the LCG input window. The performance is equivalent to 103 dB of the dynamic range with our previous LOFIC pixel in which HCG and LCG conversion gains are, respectively, 160 μ V / e − and 10 μ V / e − . [ABSTRACT FROM AUTHOR]

Star sensors are widely used by satellites for their precise pointing accuracy. However, protons in space will cause cumulative effects and single-event transients in the imaging systems of star sensors. These effects will affect the success rate of star map recognition of star sensors. In this paper, proton irradiation experiments and field tests were carried out in turn, and three typical star recognition algorithms were used to recognize the star maps. The results showed that cumulative effects led to a decrease in the number of identifiable stars, which greatly affected the recognition success rate of the grid algorithm. Hot pixels caused by displacement damage effects increased the star centroid positioning error, leading to a decrease in the recognition success rate of the triangle algorithm and pyramid algorithm. Single-event transients produced by protons hitting the image sensor are similar to the grayscale value and shape of a star, and were recognized as "false stars", which had a significant impact on the success rate of the three recognition algorithms. In general, the pyramid algorithm was more effective than the other two algorithms in identifying the affected star map, and the recognition success rate of the grid algorithm was significantly reduced. [ABSTRACT FROM AUTHOR]

In the very large array CMOS image sensor (CIS), the very large parasitic resistors and capacitors on the column bus cause very slow charging and discharging speeds and affect the readout speed seriously. In order to solve the problem, this work proposed a high-speed readout circuit that can be applied to the very large array of column parallel readout mechanism CIS. Based on 55 nm CIS special process, on the premise of not produce additional bus, by tracking the analog signal settling process in real time, self-acceleration is realized in the terminal of the column bus, then the speed of charging and discharging are improved greatly. In the work, the column bus parasitic parameters of 42,624 × 24,000 pixels CMOS image sensor with 4 μm pixel pitch are analyzed in detail and a method for establishing self-acceleration of column bus is proposed. The experimental results show that the charging time is shortened from 4μs to 790 ns, and the discharging time is shortened from 22.43μs to 1.17μs under 38.3 pF parasitic capacitance and 26.5 kΩ parasitic resistance in the column bus. On the one hand, the frame per second (FPS) of the 1Gpixel CMOS image sensor reach 10FPS, on the other hand, the column bus tail current can be reduced to 1.5 μA, which reducing the power consumption of pixel array, and the sampling interval time of the correlation double sampling (CDS) is compressed, so broadened the frequency of noise suppression. While realizing self-acceleration, the additional power consumption single column is less than 10 μA. • The parasitic effect of large array CMOS image sensor on readout speed. • A circuit that increases the speed of charging and discharging parasitic capacitors. • An adaptive acceleration architecture with low power consumption and strong robustness. • The frames per second of 1G pixel CMOS image sensor is accelerated to 10FPS. [ABSTRACT FROM AUTHOR]

In this work, an exhaustive analysis of the partial discharges that originate in the bubbles present in dielectric mineral oils is carried out. To achieve this, a low-cost, high-resolution CMOS image sensor is used. Partial discharge measurements using that image sensor are validated by a standard electrical detection system that uses a discharge capacitor. In order to accurately identify the images corresponding to partial discharges, a convolutional neural network is trained using a large set of images captured by the image sensor. An image classification model is also developed using deep learning with a convolutional network based on a TensorFlow and Keras model. The classification results of the experiments show that the accuracy achieved by our model is around 95% on the validation set and 82% on the test set. As a result of this work, a non-destructive diagnosis method has been developed that is based on the use of an image sensor and the design of a convolutional neural network. This approach allows us to obtain information about the state of mineral oils before breakdown occurs, providing a valuable tool for the evaluation and maintenance of these dielectric oils.

For radiation-hardened CMOS image sensors (CIS), 4H-SiC 64 pixel array CIS were developed, and real time imaging with an operation frequency of 30 Hz was demonstrated. Two types of pixel arrays with a 3-transistor active pixel sensor (3T-APS) and a 4-transistor active pixel sensor (4T-APS) were fabricated with SiC MOSFETs, UV photodiodes and 3-layered Al interconnections. The SiC pixel arrays were combined with peripheral circuits and an optical lens, and SiC 64 pixel CIS with 3T-/4T-APS arrays were developed.

We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 μm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively.

Image sensors such as single-photon avalanched diode (SPAD) arrays typically adopt in-pixel quenching and readout circuits, and the under-illumination first-stage readout circuits often employs high-threshold input/output (I/O) or thick-oxide metal-oxide-semiconductor field-effect transistors (MOSFETs). We have observed reliability issues with high-threshold n-channel MOSFETs when they are exposed to strong visible light. The specific stress conditions have been applied to observe the drain current (Id) variations as a function of gate voltage. The experimental results indicate that photo-induced hot electrons generate interface trap states, leading to Id degradation including increased off-state current (Ioff) and decreased on-state current (Ion). The increased Ioff further activates parasitic bipolar junction transistors (BJT). This reliability issue can be avoided by forming an inversion layer in the channel under appropriate bias conditions or by reducing the incident photon energy.

We present a 640 × 480 CMOS image sensor (CIS) with in-circuit bi-directional gamma correction with a proposed digital-correlated double sampling (CDS) structure. To operate the gamma correction in the CIS, the transfer function of the analog-to-digital converter can be changed by controlling the clock frequency of the counter using analog CDS. However, the analog CDS is vulnerable to capacitor mismatch, clock feedthrough, etc. Therefore, we propose a digital-CDS method with a hold-and-go counter structure to operate the bi-directional gamma correction in the CIS. The proposed CIS achieves a 10-bit resolution using a global log-exponential counter and configurable column reset counter with a resolution of 8/9 bits. The sensor was fabricated in a 0.11 μm CIS process, and the full chip area was 5.9 mm × 5.24 mm. The measurement results showed a maximum SNR improvement of 10.41% with the proposed bi-directional gamma-corrected digital-CDS with the hold-and-go counter. The total power consumption was 6.3 mW at a rate of 16.6 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively. [ABSTRACT FROM AUTHOR]

Reducing performance verification time is significant in product launch and production costs. This is especially true because aligning the optical stacks of off-axis pixels is a time-consuming task, but it is important to maintain sensitivity. In this paper, a numerical method to align the optical stacks of off-axis pixels is suggested in order to reduce performance test time. The components of the numerical method are the optical stack height, refractive index, and chief ray angle in order to calculate the optical stacks' optimal shift distance. The proposed method was investigated to confirm effectiveness by using optical simulation. The sub-micron backside illumination (BSI) pixels were simulated, having 2 × 2 microlens, quad-color filter array, and in-pixel deep trench isolation (DTI). Moreover, the proposed method was evaluated for various pixel pitches, microlens shapes, and CRAs. As a result, the optical stacks were optimized by using the numerical method and validated via optical simulation. Therefore, the proposed numerical method is expected to help reduce the time and cost. [ABSTRACT FROM AUTHOR]

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS [ABSTRACT FROM AUTHOR]

This paper presents a novel technique for dark current compensation of a CMOS image sensor (CIS) by using in-pixel temperature sensors (IPTSs) over a temperature range from −40 °C to 90 °C. The IPTS makes use of the 4T pixel as a temperature sensor. Thus, the 4T pixel has a double functionality, either as a pixel or as a temperature sensor. Therefore, the dark current compensation can be carried out locally by generating an artificial dark reference frame from the temperature measurements of the IPTSs and the temperature behavior of the dark current (previously calibrated). The artificial dark current frame is subtracted from the actual images to reduce/cancel the dark signal level of the pictures. In a temperature range from −40 °C to 90 °C, results show that the temperature sensors have an average temperature coefficient (TC) of 1.15 mV/°C with an inaccuracy of ±0.55 °C. Parameters such as conversion gain, gain of the amplifier, and ADC performance have been analyzed over temperature. The dark signal can be compensated in the order of 80% in its median value, and the nonuniformity is reduced in the order of 55%.