A 1Gpixel 10FPS CMOS image sensor using pixel array high-speed readout technology.

In the very large array CMOS image sensor (CIS), the very large parasitic resistors and capacitors on the column bus cause very slow charging and discharging speeds and affect the readout speed seriously. In order to solve the problem, this work proposed a high-speed readout circuit that can be applied to the very large array of column parallel readout mechanism CIS. Based on 55 nm CIS special process, on the premise of not produce additional bus, by tracking the analog signal settling process in real time, self-acceleration is realized in the terminal of the column bus, then the speed of charging and discharging are improved greatly. In the work, the column bus parasitic parameters of 42,624 × 24,000 pixels CMOS image sensor with 4 μm pixel pitch are analyzed in detail and a method for establishing self-acceleration of column bus is proposed. The experimental results show that the charging time is shortened from 4μs to 790 ns, and the discharging time is shortened from 22.43μs to 1.17μs under 38.3 pF parasitic capacitance and 26.5 kΩ parasitic resistance in the column bus. On the one hand, the frame per second (FPS) of the 1Gpixel CMOS image sensor reach 10FPS, on the other hand, the column bus tail current can be reduced to 1.5 μA, which reducing the power consumption of pixel array, and the sampling interval time of the correlation double sampling (CDS) is compressed, so broadened the frequency of noise suppression. While realizing self-acceleration, the additional power consumption single column is less than 10 μA. • The parasitic effect of large array CMOS image sensor on readout speed. • A circuit that increases the speed of charging and discharging parasitic capacitors. • An adaptive acceleration architecture with low power consumption and strong robustness. • The frames per second of 1G pixel CMOS image sensor is accelerated to 10FPS. [ABSTRACT FROM AUTHOR]