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1. Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs

Author

Slaheddine Aridhi, Karol Desnos, Maxime Pelcat, Jean-Francois Nezan, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), CIV Texas Instruments, Texas Instruments, Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Nantes Université (NU)-Université de Rennes 1 (UR1)

Subjects
Flat memory model, Computer science, Multiprocessing, Parallel computing, MPSoC, Static memory allocation, Theoretical Computer Science, Non-uniform memory access, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, multiprocessor, system-on-chip, Computing with Memory, Multi-core processor, Hardware_MEMORYSTRUCTURES, business.industry, Cache-only memory architecture, Uniform memory access, [INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV], stereo vision, synchronous dataflow, Memory management, Shared memory, Hardware and Architecture, Control and Systems Engineering, Modeling and Simulation, Embedded system, [INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV], Signal Processing, Memory footprint, memory allocation, Distributed memory, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], business, Cache coherence, Information Systems
Abstract

International audience; The majority of applications, ranging from the low complexity to very multifaceted entities requiring dedicated hardware accelerators, are very well suited for Multiprocessor Systems-on-Chips (MPSoCs). It is critical to understand the general characteristics of a given embedded application: its behavior and its requirements in terms of MPSoC resources.This paper presents a complete method to study the important aspect of memory characteristic of an application. This method spans the theoretical, architecture-independent memory characterization to the quasi optimal static memory allocation of an application on a real shared-memory MPSoC. The application is modeled as an Synchronous Dataflow (SDF) graph which is used to derive a Memory Exclusion Graph (MEG) essential for the analysis and allocation techniques. Practical considerations, such as cache coherence and memory broad-casting, are extensively treated. Memory footprint optimization is demonstrated using the example of a stereo matching algorithm from the computer vision domain. Experimental results show a reduction of the memory footprint by up to 43% compared to a state-of-the-art minimization technique, a throughput improvement of 33% over dynamic allocation, and the introduction of a tradeoff between multi-core scheduling flexibility and memory footprint.

Published
2015
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2. Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching Application

Author

Muriel Pressigout, Julien Heulot, Jean-Francois Nezan, Luce Morin, Slaheddine Aridhi, Judicael Menant, Maxime Pelcat, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Institut de Recherche Technologique b-com (IRT b-com), CIV Texas Instruments, Texas Instruments, ANR-11-INSE-0012,COMPA,Conception Orientée Modèle de calcul pour multi-Processeurs Adaptables(2011), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Subjects
Digital signal processor, Multi-core processor, business.industry, Computer science, Dataflow, Multiprocessing, 02 engineering and technology, Parallel computing, MPSoC, 030218 nuclear medicine & medical imaging, 03 medical and health sciences, 0302 clinical medicine, Shared memory, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, business, Real-time operating system, Digital signal processing
Abstract

International audience; This demonstration paper presents a multicore Real Time Operating System (RTOS) that schedules a param-eterized dataflow Model of Computation (MoC) onto a multicore Digital Signal Processor (DSP) at runtime. This RTOS called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPIDER) exploits the Parameterized and Interfaced Synchronous Dataflow (PiSDF) MoC and its features at runtime to identify locally static regions and to optimize their execution onto multicore platforms. The RTOS is used to dispatch a stereo matching algorithm tasks with a varying range of disparities. The platform used for this demonstration is a Texas Instruments Keystone II Multiprocessor System-on-Chip (MPSoC) device composed of 8 DSP cores, 4 ARM cores, a shared memory sub-system, Multicore Navigator and multiple dedicated accelerators.

Published
2014

3. SPIDER: A Synchronous Parameterized and Interfaced Dataflow-Based RTOS for Multicore DSPs

Author

Julien Heulot, Karol Desnos, Jean-Francois Nezan, Maxime Pelcat, Slaheddine Aridhi, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), CIV Texas Instruments, Texas Instruments, ANR-11-INSE-0012,COMPA,Conception Orientée Modèle de calcul pour multi-Processeurs Adaptables(2011), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Université de Nantes (UN)-Université de Rennes 1 (UR1)

Subjects
Digital signal processor, Multi-core processor, business.industry, Dataflow, Computer science, 05 social sciences, 050301 education, Parameterized complexity, 02 engineering and technology, Parallel computing, 020202 computer hardware & architecture, Scheduling (computing), [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, 0202 electrical engineering, electronic engineering, information engineering, Benchmark (computing), [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, business, 0503 education, Real-time operating system, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Digital signal processing
Abstract

International audience; This paper introduces a novel Real-Time Operating System (RTOS) based on a parameterized dataflow Model of Computation (MoC). This RTOS, called Synchronous Parameterized and Interfaced Dataflow Embedded Runtime (SPiDER), aims at efficiently scheduling Parameterized and Interfaced Synchronous Dataflow (PiSDF) graphs on multicore architectures. It exploits features of PiSDF to locate locally static regions that exhibit predictable application behavior. This paper uses a multicore signal processing benchmark to demonstrate that the SPiDER runtime can exploit more parallelism than a conventional multicore task scheduler. By comparing experimental results of the SPiDER runtime on an 8-core Texas Instruments Keystone I Digital Signal Processor (DSP) with those obtained from the OpenMP framework, latency improvements of up to 26% are demonstrated.

Published
2014

4. PREESM: A Dataflow-Based Rapid Prototyping Framework For Simplifying Multicore DSP Programming

Author

Maxime Pelcat, Julien Heulot, Slaheddine Aridhi, Karol Desnos, Clement Guy, Jean-Francois Nezan, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), CIV Texas Instruments, Texas Instruments, Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Nantes Université (NU)-Université de Rennes 1 (UR1)

Subjects
Multi-core processor, Digital signal processor, Computer science, Dataflow, Dataflow programming, Multiprocessing, 02 engineering and technology, 020202 computer hardware & architecture, Parallel processing (DSP implementation), Computer architecture, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Code generation, Algorithm design, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

International audience; The high performance Digital Signal Processors (DSP) currently manufactured by Texas Instruments are heterogeneous multiprocessor architectures. Programming these architectures is a complex task often reserved to specialized engineers because the bottlenecks of both the algorithm and the architecture need to be deeply understood in order to obtain a fairly parallel execution. The PREESM framework objective is to simplify the programming of multicore DSP systems by building on dataflow programming methods. The current functionalities of this scalable framework cover memory and time analysis, as well as automatic deadlock-free code generation. Several tutorials are provided with the tool for fast initiation of C programmers to multicore DSP programming. This paper demonstrates PREESM capabilities by comparing simulation and execution performances on a stereo matching algorithm prototyped on the TMS320C6678 8-core DSP device.

Published
2014
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5. PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration

Author

Jean-Francois Nezan, Shuvra S. Bhattacharyya, Karol Desnos, Slaheddine Aridhi, Maxime Pelcat, Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), University of Maryland [College Park], University of Maryland System, CIV Texas Instruments, Texas Instruments, Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Université de Nantes (UN)-Université de Rennes 1 (UR1)

Subjects
Reconfigurable, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Computer science, Design space exploration, Dataflow, Model of computation, Modeling, Control reconfiguration, 020206 networking & telecommunications, Context (language use), 02 engineering and technology, Parallel computing, MPSoC, Pipeline (software), [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, 020202 computer hardware & architecture, Metamodeling, 0202 electrical engineering, electronic engineering, information engineering, Meta-Model, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], Embedded Systems
Abstract

International audience; —Dataflow models of computation are widely used for the specification, analysis, and optimization of Digital Signal Processing (DSP) applications. In this paper a new meta-model called PiMM is introduced to address the important challenge of managing dynamics in DSP-oriented representations. PiMM extends a dataflow model by introducing an explicit parameter dependency tree and an interface-based hierarchical compositionality mechanism. PiMM favors the design of highly-efficient heterogeneous multicore systems, specifying algorithms with customizable trade-offs among predictability and exploita-tion of both static and adaptive task, data and pipeline paral-lelism. PiMM fosters design space exploration and reconfigurable resource allocation in a flexible dynamic dataflow context.

Published
2013
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6. Applying the Adaptive Hybrid Flow-Shop Scheduling Method to Schedule a 3GPP LTE Physical Layer Algorithm onto Many-Core Digital Signal Processors

Author

Jani Boutellier, Jean-Francois Nezan, Slaheddine Aridhi, Maxime Pelcat, Julien Heulot, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Machine Vision Group (MVG), University of Oulu, Université européenne de Bretagne - European University of Brittany (UEB), CIV Texas Instruments, Texas Instruments, ANR-11-INSE-0012,COMPA,Conception Orientée Modèle de calcul pour multi-Processeurs Adaptables(2011), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Université de Nantes (UN)-Université de Rennes 1 (UR1)

Subjects
Multi-core processor, 021103 operations research, business.industry, Computer science, 0211 other engineering and technologies, 020206 networking & telecommunications, 02 engineering and technology, Flow shop scheduling, Round-robin scheduling, Fair-share scheduling, Scheduling (computing), Fixed-priority pre-emptive scheduling, Two-level scheduling, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], business, Digital signal processing
Abstract

International audience; Currently, Multicore Digital Signal Processor (DSP) platforms are commonly used in telecommunications baseband processing. In the next few years, high performance DSPs are likely to combine many more DSP cores for signal processing with some General-Purpose Processor (GPP) cores for application control. As the number of cores increases in new DSP platform designs, scheduling of applications is becoming a complex operation. Meanwhile, the variability of the scheduled applications also tends to increase as applications become more sophisticated. Such variations require runtime adaptivity of application scheduling. This paper extends the previous work on adaptive scheduling by using the Hybrid Flow-Shop (HFS) scheduling method, which enables the device architecture to be modeled as a pipeline of Processing Elements (PEs) with multiple alternate PEs for each pipeline stage. HFS scheduling is applied to the scheduling of 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) telecommunication standard Uplink Physical Layer data processing (PUSCH). The experiments, conducted on an ARM Cortex-A9 GPP, show that an HFS scheduling algorithm has an overhead that increases very slowly with the number of PEs. This makes the method suitable for executing the adaptive scheduling in less than 1 ms for the 501 actors of a LTE PUSCH dataflow description executed on a 256-core architecture.

Published
2013

7. Pre- and post-scheduling memory allocation strategies on MPSoCs

Author

Desnos, Karol, Pelcat, Maxime, Nezan, Jean François, Aridhi, Slaheddine, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université européenne de Bretagne - European University of Brittany (UEB), CIV Texas Instruments, Texas Instruments, Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and Nantes Université (NU)-Université de Rennes 1 (UR1)

Subjects
multiprocessing systems, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], data flow graphs, system-on-chip, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, scheduling, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], storage allocation
Abstract

6 pages; International audience; This paper introduces and assesses a new method to allocate memory for applications implemented on a shared memory Multiprocessor System-on-Chip (MPSoC). This method first consists of deriving, from a Synchronous Dataflow (SDF) algorithm description, a Memory Exclusion Graph (MEG) that models all the memory objects of the application and their allocation constraints. Based on the MEG, memory allocation can be performed at three different stages of the implementation process: prior to the scheduling process, after an untimed multicore schedule is decided, or after a timed multicore schedule is decided. Each of these three alternatives offers a distinct trade-off between the amount of allocated memory and the flexibility of the application multicore execution. Tested use cases are based on descriptions of real applications and a set of random SDF graphs generated with the SDF For Free (SDF3) tool. Experimental results compare several allocation heuristics at the three implementation stages. They show that allocating memory after an untimed schedule of the application has been decided offers a reduced memory footprint as well as a flexible multicore execution.

Published
2013

8. Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB

Author

Maxime Pelcat, Jean-Franois Nezan, Slaheddine Aridhi, Jonathan Piat, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université européenne de Bretagne - European University of Brittany (UEB), CIV Texas Instruments, Texas Instruments, Institut d'Electronique et de Télécommunications de Rennes (IETR), Centre National de la Recherche Scientifique (CNRS)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Multi-core processor, Dataflow, Computer science, Distributed computing, Physical layer, 020206 networking & telecommunications, 02 engineering and technology, Load balancing (computing), Porting, 020202 computer hardware & architecture, Scheduling (computing), EnodeB, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, 0202 electrical engineering, electronic engineering, information engineering, Systems design, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

International audience; Base stations developed according to the 3GPP Long Term Evolution (LTE) standard require unprecedented processing power. 3GPP LTE enables data rates beyond hundreds of Mbits/s by using advanced technologies, necessitating a highly complex LTE physical layer. The operating power of base stations is a significant cost for operators, and is currently optimized using state-of-the-art hardware solutions, such as heterogeneous distributed systems. The traditional system design method of porting algorithms to heterogeneous distributed systems based on test-and-refine methods is a manual, thus time-expensive, task. Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach provides a clear introduction to the 3GPP LTE physical layer and to dataflow-based prototyping and programming. The difficulties in the process of 3GPP LTE physical layer porting are outlined, with particular focus on automatic partitioning and scheduling, load balancing and computation latency reduction, specifically in systems based on heterogeneous multi-core Digital Signal Processors. Multi-core prototyping methods based on algorithm dataflow modeling and architecture system-level modeling are assessed with the goal of automating and optimizing algorithm porting. With its analysis of physical layer processing and proposals of parallel programming methods, which include automatic partitioning and scheduling, Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach is a key resource for researchers and students. This study of LTE algorithms which require dynamic or static assignment and dynamic or static scheduling, allows readers to reassess and expand their knowledge of this vital component of LTE base station design.

Published
2012
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9. Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph

Author

Slaheddine Aridhi, Maxime Pelcat, Jean-Francois Nezan, Karol Desnos, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université européenne de Bretagne - European University of Brittany (UEB), CIV Texas Instruments, Texas Instruments, Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Wait-for graph, Theoretical computer science, Computer science, Multiprocessing, Graph theory, 02 engineering and technology, Parallel computing, MPSoC, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, 01 natural sciences, Synchronous Data Flow, 020202 computer hardware & architecture, Scheduling (computing), IEEE, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, Shared memory, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Systems architecture, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], Memory Bounds, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

International audience; This paper presents an application analysis technique to define the boundary of shared memory requirements of Multiprocessor System-on-Chip (MPSoC) in early stages of development. This technique is part of a rapid prototyping process and is based on the analysis of a hierarchical Synchronous Data-Flow (SDF) graph description of the system application. The analysis does not require any knowledge of the system architecture, the mapping or the scheduling of the system application tasks. The initial step of the method consists of applying a set of transformations to the SDF graph so as to reveal its memory characteristics. These transformations produce a weighted graph that represents the different memory objects of the application as well as the memory allocation constraints due to their relationships. The memory boundaries are then derived from this weighted graph using analogous graph theory problems, in particular the Maximum-Weight Clique (MWC) problem. Stateof-the-art algorithms to solve these problems are presented and a heuristic approach is proposed to provide a near-optimal solution of the MWC problem. A performance evaluation of the heuristic approach is presented, and is based on hierarchical SDF graphs of realistic applications. This evaluation shows the efficiency of proposed heuristic approach in finding near optimal solutions.

Published
2012
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10. Building a RTOS for MPSoC Dataflow Programming

Author

Yaset Oliva, Jean-Francois Nezan, Maxime Pelcat, Slaheddine Aridhi, Jean-Christophe Prévotet, Institut d'Electronique et de Télécommunications de Rennes (IETR), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Centre National de la Recherche Scientifique (CNRS), CIV Texas Instruments, Texas Instruments, Centre National de la Recherche Scientifique (CNRS)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Université de Rennes 1 (UR1), and Université de Rennes (UNIV-RENNES)

Subjects
business.industry, Dataflow, Computer science, Dataflow programming, 020206 networking & telecommunications, Multiprocessing, 02 engineering and technology, ComputerSystemsOrganization_PROCESSORARCHITECTURES, Load balancing (computing), MPSoC, 020202 computer hardware & architecture, Computer architecture, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, Symmetric multiprocessing, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], business, Real-time operating system, [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing
Abstract

International audience; Multiprocessor Systems-on-Chip (MPSoC) are becoming the standard high performance Digital Signal Processing (DSP) systems. Hardware complexity abstraction is needed to enable efficient MPSoC programming. A major challenge of MPSoC programming is efficiently handling the combination of new features necessary in a MPSoC operating system: load balancing and efficient use of the parallel resources, with the more traditional features of Real-Time Operating Systems (RTOS): resource sharing between applications, task priorities and reactivity to events. This paper presents a method to combine dataflow methods and RTOS features. The resulting system prototypes an RTOS for symmetric multiprocessing MPSoCs whose inputs are dataflow graphs of applications. The prototype is built on the uC/OS-II RTOS. Experimental results are given on a 3GPP Long Term Evolution algorithm executed on a 4-core MPSoC.

Published
2011

11. A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems

Author

Pelcat, Maxime, Nezan, Jean François, Piat, Jonathan, Croizer, Jerome, Aridhi, Slaheddine, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Institut d'Electronique et de Télécommunications de Rennes (IETR), Centre National de la Recherche Scientifique (CNRS)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES), CIV Texas Instruments, Texas Instruments, Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]
Abstract

International audience; Modern embedded systems tend to consist of multiple processors like multicore DSP (Digital Signal Processor) or MPSoC (Multiprocessor System-on-Chip). Static task scheduling for rapid prototyping of parallel embedded systems is different from the dynamic monocore scheduling problem. The communication between cores has a very high impact on the scheduling and the resulting use of hardware resources. Taking into account communication costs and competition can increase excessively the time spent in the prototyping. The System-Level Architecture Model proposed in this paper aims to provide simple system-level descriptions of architectures. The model is expressive enough to enable simulation of modern architecture behaviors. It also reduces the complexity of static mapping-scheduling by precalculating routes between elements.

Published
2009

12. Scalable Compile-Time Scheduler for Multi-core Architectures

Author

Pelcat, Maxime, Menuet, Pierrick, Nezan, Jean François, Aridhi, Slaheddine, Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Institut d'Electronique et de Télécommunications de Rennes (IETR), Centre National de la Recherche Scientifique (CNRS)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES), CIV Texas Instruments, Texas Instruments, Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Centre National de la Recherche Scientifique (CNRS), and Université de Nantes (UN)-Université de Rennes 1 (UR1)

Subjects
0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM], 020206 networking & telecommunications, 020201 artificial intelligence & image processing, 02 engineering and technology, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]
Abstract

International audience; As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing interest. This scheduling consists of statically distributing the tasks that constitute an application between available cores in a multi-core architecture in order to minimize the final latency. This problem has been proven to be NP-complete. A static scheduling algorithm is usually described as a monolithic process, and carries out two distinct functionalities: choosing the core to execute a specific function and evaluating the cost of the generated solutions. This paper describes a scheduling module which splits these functionalities into two sub-modules. This division produces an advanced scalability in terms of schedule quality and computation time, and also separates the heuristic complexity from the architecture model precision.

Published
2009

13. Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm

Author

Pelcat, Maxime, Aridhi, Slaheddine, Nezan, Jean François, Institut d'Électronique et des Technologies du numéRique (IETR), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), CIV Texas Instruments, Texas Instruments, Institut d'Electronique et de Télécommunications de Rennes (IETR), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Centre National de la Recherche Scientifique (CNRS), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Centre National de la Recherche Scientifique (CNRS)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES), and Université de Nantes (UN)-Université de Rennes 1 (UR1)

Subjects
FOS: Computer and information sciences, Computer Science - Distributed, Parallel, and Cluster Computing, [INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing, [INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM], Distributed, Parallel, and Cluster Computing (cs.DC), [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], [SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing, Computer Science - Multimedia, Multimedia (cs.MM)
Abstract

International audience; Embedded real-time applications in communication systems require high processing power. Manual scheduling devel-oped for single-processor applications is not suited to multi-core architectures. The Algorithm Architecture Matching (AAM) methodology optimizes static application implementation on multi-core architectures. The Random Access Channel Preamble Detection (RACH-PD) is an algorithm for non-synchronized access of Long Term Evolu-tion (LTE) wireless networks. LTE aims to improve the spectral efficiency of the next generation cellular system. This paper de-scribes a complete methodology for implementing the RACH-PD. AAM prototyping is applied to the RACH-PD which is modelled as a Synchronous DataFlow graph (SDF). An efficient implemen-tation of the algorithm onto a multi-core DSP, the TI C6487, is then explained. Benchmarks for the solution are given.

Published
2008
Full Text
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14. On Modeling the RapidIO communication link using the AAA Methodology

Author

Moreau, Sylvain, Aridhi, Slaheddine, Raulet, Mickael, Nezan, Jean François, Institut d'Electronique et de Télécommunications de Rennes (IETR), Centre National de la Recherche Scientifique (CNRS)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES), CIV Texas Instruments, Texas Instruments, Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Eurasip, Université de Nantes (UN)-Université de Rennes 1 (UR1), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Ecole Supérieure d'Electricité - SUPELEC (FRANCE)-Centre National de la Recherche Scientifique (CNRS), Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO.INFO-MM]Computer Science [cs]/Multimedia [cs.MM]
Abstract

International audience; Embedded real-time applications in communication systems have significant time constraints, thus requiring high processing power. One time manual scheduling developed for single-processor applications is not suited for multiprocessor architectures: manual data transfers and synchronizations quickly become very complex, leading to wasted time and potential deadlocks. We aim to develop a fast and automatic prototyping process optimized for parallel architectures particularly suited to static executives. The process is based on AAA methodology which improves algorithm implementation on multiprocessor architectures by finding the best match between algorithms and architectures. This paper presents an automatic code generation approach for architectures using the RapidIO media. A new communication model which optimizes data transfers in the generated code is depicted. Finally, we demonstrate the effectiveness of the approach with a Locally Adaptive Resolution (LAR) coding (PC-driven) application deployed on a multi-DSP platform.

Published
2007

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