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Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs
- Source :
- Journal of Signal Processing Systems, Journal of Signal Processing Systems, Springer, 2015, 80 (1), pp.19-37. ⟨10.1007/s11265-014-0952-6⟩, Journal of Signal Processing Systems, 2015, 80 (1), pp.19-37. ⟨10.1007/s11265-014-0952-6⟩
- Publication Year :
- 2015
- Publisher :
- HAL CCSD, 2015.
-
Abstract
- International audience; The majority of applications, ranging from the low complexity to very multifaceted entities requiring dedicated hardware accelerators, are very well suited for Multiprocessor Systems-on-Chips (MPSoCs). It is critical to understand the general characteristics of a given embedded application: its behavior and its requirements in terms of MPSoC resources.This paper presents a complete method to study the important aspect of memory characteristic of an application. This method spans the theoretical, architecture-independent memory characterization to the quasi optimal static memory allocation of an application on a real shared-memory MPSoC. The application is modeled as an Synchronous Dataflow (SDF) graph which is used to derive a Memory Exclusion Graph (MEG) essential for the analysis and allocation techniques. Practical considerations, such as cache coherence and memory broad-casting, are extensively treated. Memory footprint optimization is demonstrated using the example of a stereo matching algorithm from the computer vision domain. Experimental results show a reduction of the memory footprint by up to 43% compared to a state-of-the-art minimization technique, a throughput improvement of 33% over dynamic allocation, and the introduction of a tradeoff between multi-core scheduling flexibility and memory footprint.
- Subjects :
- Flat memory model
Computer science
Multiprocessing
Parallel computing
MPSoC
Static memory allocation
Theoretical Computer Science
Non-uniform memory access
[INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing
multiprocessor
system-on-chip
Computing with Memory
Multi-core processor
Hardware_MEMORYSTRUCTURES
business.industry
Cache-only memory architecture
Uniform memory access
[INFO.INFO-CV]Computer Science [cs]/Computer Vision and Pattern Recognition [cs.CV]
stereo vision
synchronous dataflow
Memory management
Shared memory
Hardware and Architecture
Control and Systems Engineering
Modeling and Simulation
Embedded system
[INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV]
Signal Processing
Memory footprint
memory allocation
Distributed memory
[INFO.INFO-ES]Computer Science [cs]/Embedded Systems
[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC]
business
Cache coherence
Information Systems
Subjects
Details
- Language :
- English
- ISSN :
- 19398018 and 19398115
- Database :
- OpenAIRE
- Journal :
- Journal of Signal Processing Systems, Journal of Signal Processing Systems, Springer, 2015, 80 (1), pp.19-37. ⟨10.1007/s11265-014-0952-6⟩, Journal of Signal Processing Systems, 2015, 80 (1), pp.19-37. ⟨10.1007/s11265-014-0952-6⟩
- Accession number :
- edsair.doi.dedup.....281a09a33caa9f388cf7d977a5e55d3e
- Full Text :
- https://doi.org/10.1007/s11265-014-0952-6⟩