Search

In order to fabricate nonvolatile 4 Mb ferroelectric random access memory (FRAM) for the application to portable electronic devices, we proposed two noble techniques; (1) shared sense amplifier arrangement structure for reducing a chip size, active current, and power consumption, and (2) address transition detection (ATD) control scheme for asynchronous operation and limited address skew-free. We successfully developed 4 Mb FRAM with the address access time of 90 ns, read/write cycle time of 100 ns, and limited address skew-free of 20 ns at 2.7 V and 85 °C.

Nonvolatile 32-Mb ferroelectric random access memory (FRAM) with-a 0.25-/spl mu/m design rule was developed by using an address transition detector (ATD) control scheme for the application to SRAM and applying a common plate folded bit-line cell scheme with current forcing latch sense amplifier (CFLSA) for increasing sensing margin, and adopting a dual bit-line reference voltage generator (DBRVG) for high noise immunity. Compared to a conventional FRAM device, the total chip size is reduced by 10.87%, which was achieved by using a single section data line (SSDL) and removing large gate-oxide capacitors, which is typically used for reference voltage generator for 1T1C FRAM. Furthermore, the imbalance of reference bit-line capacitance and main bit-line capacitance was resolved by using the CFLSA technique.

The charge distribution of memory cells is an important issue in high-density ferroelectric RAM (FRAM). Using memory cells as the reference cells provides an optimum reference voltage level, which automatically tracks the main memory cell properties. However, when memory cells are used as reference cells, the reference cells experience more access cycling than normal cells. Therefore, the endurance of the FRAM devices is determined by reference cells rather than by normal cells. Another issue is that, when the memory cells are used as reference cells, reference voltage level fluctuation cannot be avoided, especially in high-density FRAM, because variations of PZT film grain size and dimensions of the capacitor become serious. A variable reference bit line voltage scheme overcomes these problems. Unfortunately, the reference bit-line voltage scheme is not useful for all memory cells, because the reference voltage level is determined by a limited number of cells, not by all memory cells. This bit-line reference scheme is optimized with all of the memory cell charge information. Data protection is also used for unintentional power-off. An optimum read pulse width is suggested for high-speed FRAM.

This paper presents, for the first time, a 4-Mb ferroelectric random access memory, which has been designed and fabricated with 0.6-/spl mu/m ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to unstable cell capacitors are proposed: (1) double-pulsed plate read/write-back scheme; (2) complementary data preset reference circuitry; (3) relaxation/fatigue/imprint-free reference voltage generator; (4) open bitline cell array; (5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency a selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75 ns access time and 21-mA active current at 3.3 V, 25/spl deg/C, 110-ns minimum cycle. The die size is 116 mm/sup 2/ using 9 /spl mu/m/sup 2/, one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology.

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

An embedded ferroelectric random access memory (eFRAM) with an electrical fuse (e-fuse) repair scheme, in which the repair information can be electrically programmed, was successfully developed for a high performance smart card. From the viewpoints of security and cost-efficiency, the e-fuse repair scheme with ferroelectric memory cell is the best way to improve the yield of the smart card. We realized a flexible and efficient repair scheme by controlling it with repair signals and the addresses. The successful operation of the e-fuse repair scheme was confirmed and the fixed attempt ratio was over 95%. Additionally, the one time programming cells were embodied by modifying the control scheme of the eFRAM for the smart card application. The cycle time and address access time of the eFRAM for the smart card application were 70ns and 50ns, respectively.

A novel sensing scheme using a gate-oxide reference cell is developed for achieving high yield of 1T1C FRAM. The sensing scheme generates highly uniform and fatigue-free reference level, and thus provides a reliable sensing margin. A novel technology to evaluate charge distribution of all memory cells is used for identifying the root causes of bit failure which are most critical factor for yield loss. Using this technology, hydrogen damage and etching damage are found to be the major loss factors. By eliminating the etch-damage with wet treatment and by using robust hydrogen-barrier, a wide sensing window, /spl Delta/Qref=74 fC, was achieved for highly manufacturable FRAM.

Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.

This paper proposes a novel method to evaluate the real cell ferroelectric capacitor with 4 Mb nonvolatile ferroelectric RAM which has a Cell Charge Evaluation Scheme (CCES). The charge value and the distribution of the memory cell ferroelectric capacitor can be evaluated by the CCES. Additionally, it can easily screen out weak bits which have smaller charges than normal cells by using the CCES as a bit-line reference voltage generator.

A 4 Mb 1T1C FeRAM with a common-plate folded bit-line architecture achieves low noise without cell area penalty in nonvolatile ferroelectric RAM. The decoder of common plate scheme reduces area to about 62% that of a conventional separate-plate scheme. The chip area is reduced by 9.2% to 111 mm/sup 2/. The bit-line capacitance imbalance is resolved without speed loss or area penalty.

A double-level metal, one-poly, 1T/lC 64k ferroelectric RAM has been successfully fabricated with 1.2~ conventional CMOS technology. By realizing aluminum bit line, aluminum plate line in the doublelevel metal process without degrading Pt/PZT/Pt ferroelectric capacitor and by adopting lT/lC cell archtecture, lOOns data access time was obtained at Vcc=S.OV which is faster by 40% than the commercialized 2T/2C FRAM with a single-level metal. A proper annealing processes was proved to be the key for the recovery of the ferroelectric capacitor degradation caused by the double-level metal integration process.