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Shallow Trench Isolation(STI) is widely used in advanced CMOS technologies. This paper describes a shallow trench isolation for 0.13um CMOS technologies development which utilizes AMAT Ultima Plus High Density Plasma (HDP) CVD oxide process to fill 0.18um wide and 0.5um deep trenches with void free. Through optimizing source/bias RF power, process gas flow and cross section verification, as a result, we got a robust gap-fill recipe with void free.

The influence of the SiN cap-layer deposition process including different pre-clean treatments on the voltage breakdown (VBD) and electromigration (EM) behavior of copper dual damascene metallization has been studied. A remarkable improvement for voltage breakdown and electromigration were revealed depending primarily on the pre-clean treatment before cap-layer deposition rather than the deposition process itself.

In advance Cu BEOL process, Encore Ta/TaN deposition process is widely used for barrier layer deposition to achieve lower via resistance and better electro migration and stress migration performance. However, wafer micro arcing existed frequently due to complex chamber design and DC/RF/AC/ESC adoption in Encore Ta process. To solve the micro arcing issue is the one of key topics in Encore Ta process. In this study, the formation mechanism of micro arcing is analyzed. Gas plug is introduced into Encore Ta process to prevent micro arcing.