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The recent boom in wireless consumer applications has emphasized the requirement for low-cost, highly integrated RF parts. pHEMTs have become the technology of choice for current system requirements. A key requirement for all systems is high reliability components that do not fail or degrade in performance during the life cycle of the product. A confident use of these technologies relies on our capacity to better understand their fault mechanisms, and our ability to deduce related fault models. [ABSTRACT FROM AUTHOR]

A fully integrated millimeter-wave power amplifier has been designed and fabricated using a 0.13 μm SiGe BiCMOS process technology. The design is based on extracting device parasitics and utilizing them in a matching network based on a bandpass topology. This design technique assisted in attaining a wideband performance without using any on-chip inductors or transformers. The amplifier operates over the Ka & V-band ranging from 36 GHz to 53 GHz with a peak saturated power of 17.7 dBm, peak power added efficiency (PAE) of 20.5% and a gain of 19.7 dB at 46 GHz. The performance is also validated with wideband 5G signals of 50 MHz and 100 MHz channel bandwidth using 64-QAM in n262 5G NR FR2 bands (47.2 GHz–48.2 GHz). The digital predistortion is used to linearize the PA in order to qualify the required spectral mask with an error vector magnitude of 2.2%. The proposed design is compact and occupies a chip area of 1.11 mm2, including the pads.

As the use of integrated radar sensors is becoming more common not only in traditional military and automotive but also in medical and industrial applications, the requirements for a radar sensor diversify. For some applications, bandwidth is critical, primarily defining the capability to distinguish targets. Mostly, varying the frequency of an oscillator in the mmWave and THz range is realized by tuning a dc voltage to a variable capacitance. While this is typical for integrated transceivers in silicon-germanium (SiGe) technology, the tunability of a single voltage-controlled oscillator (VCO) limits the bandwidth. This work presents an approach to overcome this limitation by using two simultaneously tuned VCOs combined with a mixer. The oscillators are tuned simultaneously in opposing directions, resulting in an ultra-wideband signal at the mixer's output. The resulting tuning range is the addition of both of the VCOs' respective tuning ranges. The transceiver is realized using the B11HFC SiGe technology, featuring VCOs at center frequencies of 52 GHz and 108 GHz, respectively. The transceivers' output with a center frequency of 111 GHz is continuously tunable over a range of 73.6 GHz (66%). Furthermore, the phase noise contributions from both VCOs along a receiver test are presented.

This article compares two SiGe Colpitts quadrature voltage-controlled oscillators (QVCO) with different coupling techniques in the low E-Band, intended to be used as signal sources for push-push frequency doublers. The first QVCO is based on a cross-coupled tail-current topology, while the second is based on a fundamental active coupling network. The cross-coupled QVCO has a center frequency of 64.3 GHz and a bandwidth of 2.5 GHz. This circuit realization provides up to 12.2 dBm output power per channel and has a power consumption of 385 mW, resulting in a dc-to-RF efficiency of 8.6%. The phase noise of this oscillator at 1 MHz offset frequency is as low as −105 dBc/Hz. The fundamentally coupled QVCO has a center frequency of 67 GHz with a bandwidth of 3.9 GHz. It provides 13.1 dBm output power per channel while consuming 410 mW of power, resulting in a dc-to-RF efficiency of 9.9%. The oscillator's phase noise at 1 MHz offset frequency is as low as −105.2 dBc/Hz. In addition to the presented circuits, this article introduces a method to measure the relative phase error of quadrature signals utilizing a vector network analyzer. This method is verified with measurements of the developed QVCOs.

Wireless communication and sensing applications seek higher frequencies to enable higher data rates or more precise localization using a wider modulation bandwidth. Particularly, 6G and autonomous driving research projects focus on the D-band. With higher frequencies, antennas can be placed closer together, allowing for more antennas in the same area and creating a narrower beam. However, a greater number of channels increases system complexity. Each antenna typically requires one vector modulator in a phased-array system, which entails four analog control voltages and four DACs. Consequently, increasing the frequency and utilizing more channels can result in an enlarged system size due to the complex PCB design. This article presents a phased-array chain consisting of a tunable branchline coupler based on varactor diodes, a digital vector modulator, and a power amplifier. The combination of varactor diodes and the VM enables coarse phase changes through 4-bit digital switching and precise phase adjustment through varactor tuning. This approach demonstrates that a four-element array only requires two DACs instead of 16 to cover the entire angular range. The phased-array chain was designed and manufactured using B11HFC silicon-germanium technology from Infineon Technologies AG.

In this work, we present an O-band dual-polarization coherent receiver optical sub-assembly (cROSA), monolithically integrated in a 0.25 $\mu$m BiCMOS technology. The receiver features 248 nm deep ultra violet compatible 2-dimensional grating couplers (2D-GRCs), and an adaptive polarization controller, suitable for mitigation of local oscillator induced power fading in self-homodyne transmission systems. The cROSA is evaluated in system experiments at 64 GBd quadrature-phase shift-keying. Experimental results are related to grating coupler induced polarization crosstalk through Monte-Carlo simulations. Second generation 2D-GRCs are proposed.

Radar systems got very popular in sensing applications in the last two decades besides the traditional military sector. Nowadays, many applications favor multiple-input multiple-output (MIMO) radar over phased-array radar. Here, time-division multiplexing (TDM) and code-division multiplexing (CDM), like a phase-modulated continuous wave (PMCW), are well-known techniques. However, every method needs special components on the MMIC. In this article, a $\text{125}\,\text{GHz}$ vector modulator (VM) circuit is presented, which can operate as a switchable amplifier in TDM systems, as a binary-phase modulator in CDM systems, and as a phase-shifter in phased-array systems. Based on simulations and $S$-parameter measurements, the VM itself and the three different operating modes are analyzed. We also present a technique to separate coupler imperfections from the $S$-parameter measurements to analyze the VM separately. We designed the VM with the B11HFC silicon-germanium technology ($f_{t} / f_{max} = 250/370\, \text{GHz}$), using both HBTs (heterojunction bipolar transistors) and CMOS transistors. Inside the VM, two cross-connected power amplifiers (PAs) are fed by an in-phase (I), and two cross-connected PAs are fed by a quadrature-phase (Q) signal. The four PAs are controlled by a 4-bit interface to switch them on or off, thus generating output signals in the range of $0^\circ$ to $360^\circ$.

In this work, the numerical simulation of a SiGe heterojunction bipolar transistor (HBT) for DC and AC performance operating at cryogenic temperature with a hydrodynamic carrier transport model is analyzed. A new modified temperature-dependent Si1−xGex energy bandgap model was used. Using a simplified 2D TCAD design structure, the device characteristics on 55 nm SiGe HBT technology and the mobility model are calibrated with experimental data. Base current reversal due to induced impact-ionization at the collector-base junction is analyzed, where the estimated collector-emitter breakdown voltage with the base open (BVCEO) is 1.48 V at 300 K. This reveals good voltage handling ability. At cryogenic temperatures, dopant incomplete ionization in the lightly doped collector region shows a 28% decrease in ionized dopant concentration at 50 K; this affects the base-collector depletion capacitance. The emitter electron barrier tunneling leakage on collector current is studied using a non-local e-barrier tunneling model at different temperatures that shows an improvement in peak DC gain at lower temperatures. Using the small-signal ac analysis, the cut-off frequency and the maximum oscillation frequency are extracted for high-frequency application, and the base widening effect is discussed. A comparison of this work with measured data on 90 nm SiGe HBT is also discussed in brief, which shows improvements in the simulated structure. [ABSTRACT FROM AUTHOR]

Dielectric spectroscopy in the sub-THz regime is a promising candidate for microfluidic-based analysis of biological cells and bio-molecules, since multiple vibrational and rotational transition energy levels exist in this frequency range (P. Siegel, "Terahertz technology in biology and medicine," IEEE Trans. Microw. Theor. Tech., vol. 52, pp. 2438–2447, 2004). This article presents our recent efforts in the implementation of microfluidic channel networks with silicon-based technologies to unleash the potential of an integrated sub-THz microfluidic sensor platform. Various aspects of dielectric sensors, readout systems, flowmeter design as well as implemention- and technology-related questions are addressed. Three dielectric sensor systems are presented operating at 240 GHz realizing transmission-based, reflection-based and full two-port architectures. Furthermore different silicon based microchannel integration techniques are discussed as well as a novel copper pillar-based PCB microchannel method is proposed and successfully demonstrated. [ABSTRACT FROM AUTHOR]

The most effective way to reduce phase noise in integrated harmonic oscillators is by rising the active power in the resonator, i.e., scaling down the tank impedance and increasing power consumption. However, in widespread parallel-tank oscillators, a lower bound is readily set by the smallest inductance that can be implemented without incurring into excessive degradation of the quality factor. Emerging multicore oscillators circumvent the issue only partially. In this article, a circuit topology that breaks the phase noise barrier of parallel-tank oscillators is presented. By exploiting the same tank at the series resonance, the remarkably lower tank resistance allows to considerably rise the active power for given voltage swing. As a result, the phase noise is radically reduced without the need for aggressive scaling of the resonator inductor. Two voltage-controlled oscillators (VCOs) in a BiCMOS 55-nm technology exploiting the concept at 10-GHz center frequency are presented. The first design targets an ultra-low phase noise and, with 9% tuning range, demonstrates −138 dBc/Hz at 1-MHz offset with 1.2-V supply and an excellent −190-dBc/Hz figure of merit (FoM). The second design leverages a different implementation of the tank to expand the frequency tuning range and to trade phase noise for power consumption. The tuning range is 16% with a minimum phase noise of −133 dBc/Hz at 1 MHz and −188-dBc/Hz best FoM. To the authors’ knowledge, the presented VCOs demonstrate experimentally the lowest phase noise ever reported with fully integrated oscillators in silicon technology. [ABSTRACT FROM AUTHOR]

Fast active quenching of single-photon avalanche diodes (SPADs) is important to reduce the afterpulsing probability (APP). An option to reduce the reaction time of electronics to a SPAD's avalanche is to design a quencher exploiting bipolar transistors. A quencher in a 0.35 μm CMOS technology with a nominal supply voltage of 3.3 V, which operated with excess bias voltages up to 6.6 V, was re-designed accordingly. In the new 0.35 μm pure-silicon BiCMOS quencher, the comparator takes advantage of a bipolar differential amplifier, which additionally gives the head room to increase the width of some CMOS transistors as well. The proposed BiCMOS quencher is able to drive the load of a wire-bonded 184 μm-diameter SPAD, while the CMOS design fails. A comparison, where both chips are measured with a wire-bonded, 34 μm-diameter SPAD, shows that the BiCMOS quencher has a reaction time, which is 330 ps to 1.1 ns faster than that of the CMOS quencher.

An efficient, broadband SiGe HBT cascode nonuniform distributed power amplifier (NDPA) is presented for low-cost, fully integrated Si-based phased arrays. Optimum load impedances at each SiGe HBT cascode in a four-stage NDPA core are obtained by scaling the characteristic impedance ($Z_{0}$) of the collector transmission lines (TLs) and tapering the SiGe HBT emitter area simultaneously. A novel compact, lumped-element two-section $\lambda $ /4 output impedance transformer (OIT) is proposed to lower the NDPA load impedance ($Z_{L}$) from 50 to 25 $\Omega $ over more than one decade bandwidth (BW). Each $\lambda $ /4 impedance transformer is realized by four cascaded CLC $\pi $ -networks integrated into a single three-turn symmetric inductor in order to achieve compact size, high passive efficiency, and high LC cutoff frequency ($f_{c}$). The systematic design approach of a lumped-element $\lambda $ /4 impedance transformer with an arbitrary $Z_{0}$ is described in detail. The prototype NDPA was fabricated in 0.13- $\mu \text{m}$ SiGe HBT BiCMOS technology. The proposed SiGe HBT cascode NDPA supports both high linearity (HL) and high gain (HG) modes, each suited to a specific application. The NDPA attains a peak power gain of 10.3/12.5 dB, a saturated output power ($P_{\mathrm {out}}$) of 21.3/21.5 dBm, and a power added efficiency (PAE) of 12.2%/12.5%–21.6%/22.0% for HL/HG modes, with a 3-dB BW from 1.5 to 24.0 GHz. The NDPA delivers 13.0-dBm average $P_{\mathrm {out}}$ with a PAE of 10.0% at 6-Gbit/s data rate 64 QAM modulation. [ABSTRACT FROM AUTHOR]

A frequency multiplier by six (sextupler) for local oscillation (LO) generation in $E$ -band is presented. It comprises a tripler, a doubler, and an output buffer. A detailed analysis is proposed to discuss the optimal order of the multiplication stages to minimize the unwanted harmonics of the input. Moreover, novel circuit topologies for the tripler and doubler are introduced. The tripler core is devised to reproduce the transcharacteristic of a third-order polynomial that ideally generates only the third harmonic of a sinusoidal input signal. By leveraging an envelope detector for adaptive biasing, the circuit maintains excellent suppression of the driving signal and unwanted harmonics over wide variations of the input power. The proposed topology improves output signal purity and current conversion efficiency against classical triplers based on the transistors biased in class C. The cascaded frequency doubler is based on a novel push–push configuration that provides a differential output and excellent odd-order harmonic rejection due to an enhanced robustness to amplitude and phase unbalances of the driving signal. The sextupler is fabricated in a 55-nm SiGe-BiCMOS technology. Driven with a 0-dBm input signal and consuming 63.1 mW of dc power, it delivers $P_{\mathrm {out}}$ up to 5.6 dBm at 72 GHz. $P_{\mathrm {out}}$ is above 0 dBm over 20-GHz bandwidth (BW), while undesired harmonics of the input are suppressed by more than 35 dB. Compared to previously reported millimeter-wave frequency multipliers, the sextupler demonstrates improved harmonic rejection, conversion gain, and efficiency, without compromising the operation BW and output power. [ABSTRACT FROM AUTHOR]

This letter presents a 220–261-GHz frequency multiplier-by-18 chain in a 130-nm SiGe BiCMOS technology. It consists of three amplifiers (12–15, 110–135, and 216–270 GHz), two frequency triplers (36–45 and 108–135 GHz), a third-order Chebyshev bandpass filter (36–45 GHz), and a modified Gilbert-cell-based frequency doubler (216–270 GHz). The peak output power is about 8 dBm at 240 GHz with a 3-dB bandwidth of 41 GHz for an input power of −7 dBm. The unwanted harmonics are suppressed more than 25 dBc over the frequency range of interest. It consumes a dc current of 114.7 mA from a supply voltage of 3.3 V in the quiescent operation and drains a current of 130 mA for an input power of −7 dBm, which results in a drain efficiency of 1.47%. The total circuit occupies an area of 0.58 mm 2 (1.35 mm $\times0.43$ mm). [ABSTRACT FROM AUTHOR]

This letter reports a compact-size 225–265 GHz quadrature receiver (RX), consisting of a low-noise amplifier (LNA), a power divider (PD), two down-conversion fundamental mixers, and an IQ generator, in a 130-nm SiGe BiCMOS technology with $f_{T}/f~_{\text {max}}$ of 300/500 GHz. The measured peak value of the down-conversion power gain is 20.6 dB at 240 GHz without IF amplification, and it achieves a 3-dB RF bandwidth of 40 GHz from 225 to 265 GHz. The measured minimum single-sideband (SSB) noise figure (NF) is 13.2 dB at 240 GHz and better than 14.2 dB along the 3-dB RF bandwidth. The amplitude and phase imbalances of the IF output signals were measured as less than 1.7 dB and 2°, respectively, over the frequency range of interest. The RX circuit draws a current of about 40.5 mA from a single-supply of 3.3 V. It occupies a total area of 0.42 mm 2 (0.97 mm $\times $ 0.43 mm), and the effective area is about 0.14 mm 2, excluding the pads and Marchand baluns placed for on- wafer probing. [ABSTRACT FROM AUTHOR]

This paper introduces a novel phase-shifting technique for quadrature voltage-controlled oscillators (QVCOs) utilizing an LC emitter degeneration architecture. The proposed technique enables a phase shift of up to ±90°in the transconductance of the coupling path while also generating a negative input resistance. This innovative approach avoids phase ambiguity, mitigates the trade-off between phase noise and phase error, and substantially reduces QVCO power consumption. Moreover, compared to conventional capacitance emitter degeneration methods, the LC emitter degeneration structure has a lower equivalent input capacitance, expanding the QVCO's frequency tuning range. The designed QVCO is implemented using a 180 nm SiGe BiCMOS technology, occupying a compact area of 0.037 mm 2. Post-layout simulation evaluations under various process, voltage, and temperature (PVT) conditions validate the robustness and reliability of the design. Results indicate a phase noise of 102.7 dBc/Hz at a 1 MHz offset from a 22.1 GHz carrier, a frequency tuning range of 25.2%, a phase error of 0.9°, and a power consumption of 12 mW from a 1.1 V supply, achieving a figure of merit (FoM) of 178.8 dBc/Hz. [ABSTRACT FROM AUTHOR]

Multiband coherent communication is being handled as a promising candidate to address the increasing demand for higher data rates and capacity. At the same time, coherent communication is expected to enter the data center domain in the near future. With coherent data links in both, data- and telecom, spanning multiple optical bands, novel approaches to coherent transceiver design and traffic engineering will become a necessity. In this work, we present a monolithically integrated silicon photonic coherent receiver for O- and C-band. The receiver features a 2 × 2 multi-mode interference coupler network as 90 $^\circ$ hybrid optimized for 1430 nm (E-band). The total power consumption is 460 mW at a footprint of approximately 6 mm $^{2}$ , and an opto-electrical bandwidth of 33 GHz. 64 GBd operation is demonstrated in O- and C-band, which is competitive to the state-of-the-art for silicon photonic coherent receiver in the C-band, and the highest symbol rate to date for O-band coherent communication. [ABSTRACT FROM AUTHOR]

This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer- $N$ phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, the proposed signal source shows a −73.1-dBc reference spur, −113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and −90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fsrms at 40.96 GHz and 122 fsrms (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is −3.24 dBm, and the power consumption is 372 mW. [ABSTRACT FROM AUTHOR]

Microwave-induced thermoacoustic (TA) imaging, combining high microwave contrast with high ultrasonic resolution has the potential to revolutionize applications such as continuous healthcare monitoring, point-of-care imaging, and biometric authentication. However, the size, cost, and integration of a high-power microwave transmitter is a key bottleneck in making TA imaging truly portable, affordable, and ubiquitous. Toward that end, this work presents a compact 4.9-GHz pulsed power amplifier (PA) with a 4.87-mm2 active area implemented in a 55-nm BiCMOS technology, operating in a duty-cycled mode and achieving 37.3-dBm peak output power—the highest demonstrated peak power in PAs fabricated on a silicon substrate with deep submicron CMOS integration. We also reconstruct the first known high-fidelity TA images of tissue phantoms using an integrated silicon PA. [ABSTRACT FROM AUTHOR]

A wide tuning range, low-phase-noise SiGe BiCMOS LC voltage-controlled oscillator (VCO) covering both the Ku- and Ka-bands is presented in this letter. The proposed VCO using a cross-coupled topology creates the fundamental harmonic from 14.35 to 17.86 GHz and the second harmonic, which is drawn from the common-mode point through a matched buffer, covering from 28.7 to 35.72 GHz. A transformer-coupled tank, which takes advantage of tank parasitics to create harmonic resonances, is used to reduce the phase noise (PN). The 5-bit binary-weighted capacitor bank is connected to the transformer secondary to create a wide tuning range, which is measured from 14.35 to 17.86 GHz (21.1%) and 28.7 to 35.72 GHz. Brilliant PN of −115.5 and −109 dBc/Hz at 1-MHz offset is measured at 14.53- and 29.1-GHz carrier frequencies individually. The proposed VCO with an extra output of the second harmonic exhibits little PN deterioration. [ABSTRACT FROM AUTHOR]

Fast active quenching of single-photon avalanche diodes (SPADs) is important to reduce the afterpulsing probability (APP). An option to reduce the reaction time of electronics to a SPAD's avalanche is to design a quencher exploiting bipolar transistors. A quencher in a 0.35 μm CMOS technology with a nominal supply voltage of 3.3 V, which operated with excess bias voltages up to 6.6 V, was re-designed accordingly. In the new 0.35 μm pure-silicon BiCMOS quencher, the comparator takes advantage of a bipolar differential amplifier, which additionally gives the head room to increase the width of some CMOS transistors as well. The proposed BiCMOS quencher is able to drive the load of a wire-bonded 184 μm-diameter SPAD, while the CMOS design fails. A comparison, where both chips are measured with a wire-bonded, 34 μm-diameter SPAD, shows that the BiCMOS quencher has a reaction time, which is 330 ps to 1.1 ns faster than that of the CMOS quencher. [ABSTRACT FROM AUTHOR]

This letter presents a 140-GHz frequency-modulated continuous-wave (FMCW) radar sensor for automotive applications. The monolithic microwave integrated circuit (MMIC) inside of the sensor features one transmit (TX) and one receive (RX) channel as well as the possibility to apply binary phase shift keying (BPSK) modulation to the transmitted signal. The chip is bonded on a printed circuit board (PCB) that features substrate integrated waveguides (SIWs) to minimize losses in the signal distribution. It provides rectangular waveguide (RWG) outputs for the $D$ -band to facilitate the connection of measurement equipment and antennas. The complete sensor system is controlled by a backend board that is connected via pin headers on top of the RF board with the bonded chip. [ABSTRACT FROM AUTHOR]

This paper presents design, mathematical analysis, and measurement of low noise single-stage transimpedance amplifier (TIA) with scalable bandwidth using 130 nm bipolar complementary metal-oxide-semiconductor (BiCMOS) silicon-germanium (SiGe) process. Common-emitter (CE) shunt-shunt feedback topology with active inductor peaking has been used in the design for improving noise, gain and driving capability of TIA by decreasing the input and output impedance, respectively. The use of active inductive peaking in CE shunt-shunt feedback topology has resulted in a new TIA configuration with better performance. The circuit has been optimized for low noise by adopting the proposed design technique. Validity of the mathematical analysis and design for the proposed TIA has been established with the help of simulations as well as measurement results. The measurement results of Ku-band TIA (10 MHz to 14 GHz) have demonstrated a transimpedance gain of $53.2~dB\Omega $ , input-referred current noise of 16.8 pA/ $\sqrt {Hz}$ with power consumption of $9.8~~mW $ . The design architecture is adaptable for higher frequency bands, which has been demonstrated by designing another TIA covering K- and Ka-bands (10 MHz to 35 GHz) with transimpedance gain of 33.4 dB $\Omega $ , input-referred current noise of 29.4 pA/ $\sqrt {Hz}$ with power consumption of $28.1~~mW $ in the post-layout simulation results, and occupies same chip area as that of 14 GHz, i.e., $0.1\times 0.21\,\,mm^{2}$

The COVID-19 pandemic is spreading around the world causing more than 177 million cases and over 3.8 million deaths according to the European Centre for Disease Prevention and Control. The virus has devastating effects on economies, health, and well-being of worldwide population. Due to the high increase in daily cases, the available number of COVID-19 test kits in under-developed countries is scarce. Hence, it is vital to implement an effective screening method of patients using chest radiography since the equipment already exists. With the presence of automatic detection systems, any abnormalities in chest radiography that characterizes COVID-19 can be identified. Several artificial-intelligence algorithms have been proposed to detect the virus. However, neural networks training is considered to be timeconsuming. Since computations in training neural networks are spent on floating-point multiplications, high computational power is required. Multipliers consume the most space and power among all arithmetic operators in deep neural networks. This paper proposes a 15 Gbps high-speed bipolar-complementary-metal-oxide-semiconductor (BiCMOS) exclusive-nor (XNOR) gate to replace multipliers in binarized neural networks. The proposed gate can be implemented on BiCMOS-based fieldprogrammable gate arrays (FPGAs). This will significantly improve the response time in identifying chest abnormalities in CT scans and X-rays. [ABSTRACT FROM AUTHOR]

This work presents a ${D}$ -band monostatic radar system operating from 144.6 to 161 GHz, which is placed inside a 3-D-printed low-cost case with a built-in lens to boost the antenna (ANT) directivity. The monolithic microwave integrated circuit (MMIC) is manufactured in a 130-nm BiCMOS process and includes a compact transceiver architecture consisting of an oscillator, a diode-based mixer, and an on-chip antenna. The implemented topology allows to significantly improve the signal-to-noise ratio and features a built-in self-test (BIST) structure with the possibility to provide on-chip antenna characterization using power sensors in combination with a directional coupler. Housed inside the robust printed package, the MMIC has only dc and baseband frequency connections, which offers ease of handling and poses the low-cost potential for a variety of applications. The complete transceiver chip consumes only 84.7 mA from a 3.3-V supply and its size is 1964 $\mu \text{m}\,\,\times1448\,\,\mu \text{m}$. Together with the package the sensor measures a size of 42.2 mm $\times42.2$ mm $\times45.7$ mm. [ABSTRACT FROM AUTHOR]

This article presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/de-embedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the ground plane and the floorplan of the devices under test are also compared. The influence of RF probe geometry on the coupling with the substrate and adjacent structures is also considered to evaluate the accuracy of the measurement, especially using EM simulation methodology. Finally, the importance of measuring above 110 GHz is demonstrated for SiGe HBT parameter extraction. The validation of the compact model is confirmed thanks to an EM-SPICE co-simulation that integrates the whole calibration cum de-embedding procedure.

This article presents a fully integrated terahertz (THz) comb/pulse radiator and a broadband frequency-comb heterodyne receiver for sensing and imaging applications. The chipset is fabricated in the GlobalFoundries 90-nm SiGe BiCMOS process. The comb radiator utilizes p-i-n diode sharp reverse recovery to generate THz frequency comb/pulses. The repetition rate of the radiated pulses is locked to a stable off-chip source, which can be adjusted to as high as 15 GHz. By using a low-phase noise off-chip source rather than an on-chip oscillator, low phase noise and high-frequency stability are achieved. The phase noise of 405-GHz tone is −82 dBc at a 10-kHz offset frequency. The radiated tones are characterized from 220 GHz up to 1.1 THz using VDI SAX modules with the measured EIRP of −11, −15, and −36 dBm at 405, 500, and 750 GHz, respectively. In addition, a THz frequency comb detector using a Schottky barrier diode passive mixer is presented. The detector uses a broadband comb as LO for heterodyne detection of any arbitrary spectrum in mm-wave/THz band by adjusting the spacing of the LO comb from 100 s of MHz up to 15 GHz with a resolution of 2 Hz. The receiver chip is characterized from 220 up to 500 GHz with the measured NF of 24.5, 36, and 44 dB at 270, 405, and 495 GHz, respectively. Moreover, a dual-comb technique using the radiator and receiver chips is demonstrated, promising a compact low-cost solution for dual-comb sensing applications. The radiator and receiver chips consume a dc power of 40 and 38 mW, respectively. [ABSTRACT FROM AUTHOR]

Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a −11.5 dBm input 1 dB compression point have been measured. [ABSTRACT FROM AUTHOR]

In this work, performance of conventional gyrator-C based active inductor is studied and two designs of single-ended active inductors based on modified gyrator-C topology employing SiGe HBTs are proposed using 130 nm BiCMOS technology which provides high quality factor with low-power consumption. The performance in terms of inductive bandwidth, S11, noise figure, quality factor and power consumption have been compared and the tradeoff between performance parameters are discussed. In the proposed work, first design of active inductor produces high value of inductive bandwidth (271 MHz–3.7 GHz) with moderate value of quality factor (437), whereas second design produces moderate range of inductive bandwidth (182 MHz–2.3 GHz) with high quality factor (6014). The proposed active inductors are used in second order LC band pass filter and the performance metrics of filter in terms of 1 dB compression point (− 18.88 and − 18.55), IIP3 (− 14.68 and − 9.02) and passband gain is investigated. The study suggests that proposed designs of active inductors are suitable candidate for high performance, low power RF applications with nearly 1 GHz bandwidth. [ABSTRACT FROM AUTHOR]

A wideband, low phase variation 6‐bit digital step attenuator (DSA) is presented. To further expand the operation bandwidth while keeping low attenuation and phase error, modified π/T‐type attenuator structures are introduced. In the large attenuation unit, the modified π‐type attenuator structure is adopted, which includes middle adjusting capacitance and bypass compensating capacitance. Moreover, the reduced T‐type structure with bypass compensation capacitance is used in the small attenuation units. The influence of the introduced capacitance on various attenuation units is analyzed. To prove the effectiveness of the modified structure on extending the bandwidth, a DSA with a broad bandwidth of DC‐25 GHz and low attenuation and phase error is realized in a 0.18 μm SiGe BiCMOS technology. The attenuation range of the attenuator is 31.5 dB with 0.5‐dB step, which is controlled by 6 bits digital input. Its root‐mean‐square (RMS) attenuation error is lower than 0.3 dB, and the phase error (RMS) is below 4.9°. The insertion loss is lower than 11 dB, and the core area is 0.33 mm2. [ABSTRACT FROM AUTHOR]

We demonstrate a four-to-one 100-GS/s time interleaver realized in a 55-nm BiCMOS technology. The interleaver comprises two stages of two-to-one sub-interleavers. Each sub-interleaver is implemented using a return-to-zero generation and summing architecture. This sub-interleaver architecture ensures lower clock feedthrough and contains an inherent feed-forward equalizer. Effective number of bits (ENOB) measurements have been performed revealing the interleaver’s ENOB of 4.9 at 3 GHz. In addition, the transfer function is measured to show the capabilities of the inherent feed-forward equalizer of the sub-interleavers. The measured analog output bandwidth of the four-to-one interleaver is 73 GHz. Finally, a 100-GBd PAM-4 (200 Gb/s) signal is generated by interleaving four 25-GBd PAM-4 streams while consuming 700 mW. [ABSTRACT FROM AUTHOR]

We present a co-designed Dicke switch and low-noise amplifier (LNA) in which the switch incorporates a transformer-based topology and serves as the input matching network of the LNA. This topology is configured to minimize the amplifier gain mismatch between the two switching states caused by process variations while providing a low noise figure (NF). The circuit is implemented in a 0.13-μm SiGe BiCMOS technology, and it achieves more than 20-dB gain and minimum NF values of 4.5 and 0.58 dB at 300 and 20 K, respectively. It consumes a dc power of 15 mW. The front-end switch presents a peak isolation of 17 dB, and the input return loss is better than 15 dB across 45–70 GHz. A noise source is also coupled to the front-end circuitry to enable on-chip calibration. The noise performance and reliability of several on-chip p-n junctions were characterized, and the one with the highest excess noise ratio was coupled to the front-end circuitry. To the best of our knowledge, the lowest NF of an integrated switch and LNA at V-band frequencies is achieved in the present work, along with the first reliability study of on-chip noise sources in a SiGe BiCMOS technology. [ABSTRACT FROM AUTHOR]

This letter proposes a new emitter-base-collector-base-emitter (EBCBE) SiGe HBT suited for high power RF switches. Two collector-base-emitter (CBE) SiGe HBTs are merged into a single EBCBE SiGe HBT, not only to double its maximum voltage swing, but also to decrease its active area and parasitics. To further boost its power handling, a capacitive voltage distribution and a collector floating are incorporated into the new EBCBE SiGe HBT. A X-band λ/4 shunt single-pole-double-throw (SPDT) switch using the EBCBE SiGe HBT achieves measured insertion losses and isolations of 1.2/1.3 and 29.2/23.0 dB at 10 GHz in TX/RX modes, respectively. In TX mode, measured input 1-dB power compression (P1dB) is 25.4 dBm, and it can be extended to 28.5 dBm at −0.6 V base bias of the EBCBE SiGe HBT. [ABSTRACT FROM AUTHOR]

In this brief, A two-stage power amplifier (PA) with a four-way series-parallel power combiner is presented for Ka-band applications. A compact power stage with optimized cascode transistors is proposed to minimize the parasitic effects and boost the amplifier output power at the mm-wave frequencies. The output network employs two spiral transformers and a transmission-line combiner to realize low-loss power matching and broadband series-parallel combining. The PA is fabricated in a 130-nm SiGe BiCMOS technology and it occupies a core area of 0.48 mm2. The PA achieves a peak gain of 25.3 dB with the 3-dB bandwidth of 30-to-41 GHz. At the frequency of 35 GHz, the measured saturated output power (PSAT), 1-dB compressed power (OP1dB), and power-added efficiency (PAE) are 22.8 dBm, 22.6 dBm, and 27%, respectively. [ABSTRACT FROM AUTHOR]

This article presents $G$ -band monostatic and bistatic radar transceivers (TRX) incorporating on-chip antennas for short-range high-precision applications. The circuits were fabricated using a silicon–germanium (SiGe) BiCMOS technology offering heterojunction bipolar transistors (HBTs) with $\bf {f}_{\mathbf {T}}/\bf {f}_{\mathbf {MAX}}$ of 300/500 GHz. The monostatic TRX implements a tunable leakage canceller (LC) for enhanced transmitter (TX)-to-receiver (RX) leakage compensation and hence improved detectability of weakly reflecting near targets. A standalone monostatic TRX characterized at on-wafer level achieves 4-dBm maximum output power ($\bf {P}_{\mathbf {TX}}$) and 19-dB peak conversion gain ($\bf {G}_{\mathbf {RX}}$) with 3-dB bandwidths of 18 and 17GHz for the TX and the RX, respectively. The bistatic version reaches $\bf {P}_{\mathbf {TX}}$ of 13 dBm and $\bf {G}_{\mathbf {RX}}$ of 24 dB expanding the 3-dB bandwidths to 32 and 34 GHz for the TX and RX, respectively. A double-folded dipole antenna providing 5-dBi gain at 170 GHz was implemented using localized backside etching (LBE) and integrated with the transceivers. A frequency-modulated continuous-wave (FMCW) radar demonstrator incorporating an external phase-locked loop (PLL) was built to evaluate both TRXs and tunable leakage cancellation feature available in the monostatic variant. The maximum equivalent isotropic radiated power ($\bf {EIRP}$), including on-chip antennas, is 8 and 18 dBm for the monostatic and bistatic TRX, respectively. The radars support sweep bandwidth up to 20 GHz reaching 2.1 cm spatial resolution. For a target at 1 m distance the measured ranging precision is $105~\mu \text{m}$ and $13~\mu \text{m}$ for monostatic and bistatic TRX, accordingly. Activation of leakage cancellation effectively suppresses close-in noise and extends the minimum detectable range remarkably. [ABSTRACT FROM AUTHOR]

This brief presents two dual-band low noise amplifiers (LNAs) in Q/V-band fabricated in 0.18- ${\mu }\text{m}$ SiGe BiCMOS technology. The developed LNAs function over the dual (44/60 GHz)-band with an integrated filtering function and achieve peak power gain of 19.1 dB with minimal gain imbalance of less than 0.2 dB between the two bands. The achieved 3-dB bandwidths are more than 6 GHz for each band of the two LNAs with the lowest measured noise figure of 5.6 dB in the targeted frequency bands. The synthesized Q-enhanced metamaterial transmission line structures proposed in this brief contribute a dual-band operation at 44/60 GHz with a rejection of more than 30 dB between the two bands. The Colpitts style negative generation circuit is utilized in conjunction with composite right/left-handed metamaterial transmission line and its dual structure, which is unprecedented, to realize multi-band millimeter-wave integrated circuits. [ABSTRACT FROM AUTHOR]

This letter presents the design of a 140–160 GHz vector-modulator-type phase shifter, integrated in a 55-nm BiCMOS technology. The circuit is optimized to minimize the occupied area and maximize the linearity, facilitating its integration in D-band phased arrays. Test results show an average insertion loss of 4.5 dB, an OP 1 dB of −3.7 dBm, and rms gain/phase errors lower than 1.4 dB and 7.5°. The circuit core occupies 0.05 mm2, consuming less than 66 mW of dc power. [ABSTRACT FROM AUTHOR]

This letter presents a 28–40-GHz 5-bit digital step attenuator (DSA) in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. The DSA achieves low amplitude and phase variations by using the following techniques: 1) combination of distributed, T-type, and modified $\Pi $ -type attenuators can ensure a low amplitude variation while maintaining a compact size; 2) interstage matching is designed to relax the loading effect between each stage; 3) inductive compensation is adopted to reduce the phase error for 8- and 16-dB attenuation cells. The DSA exhibits a 31-dB tuning range with 1-dB tuning step. The measured rms amplitude and phase errors are < 0.43 dB and < 5.4° over 28–40 GHz, respectively. The insertion loss is 5.4–9.1 dB from 28 to 40 GHz. [ABSTRACT FROM AUTHOR]

In this work, a dual-mode (divide-by-2 and divide-by-3) dynamic frequency divider is presented. A tunable delay gated ring oscillator (TDGRO) topology is proposed for dual-mode operation and bandwidth extension. It uses a 130-nm gate length SiGe BiCMOS technology with the $f_{t}$ and $f_{\mathrm {max}}$ of 250 and 370 GHz, respectively. Verification shows that it works at $W$ -band from 70 to 114 GHz (47.8% bandwidth) for divide-by-2 and works at $D$ -band from 105 to 160 GHz (41.5% bandwidth) for divide-by-3. This divider can be used in integrated phase-locked loops (PLLs) at millimeter-wave frequencies. [ABSTRACT FROM AUTHOR]

This paper presents a 802.11ac low-noise amplifier with bypass function integrated in 0.36 μm SiGe BiCMOS process. In order to meet the specifications of the criteria, the methods for optimizing noise, power gain and stability were given. In the circuit design, the SiGe HBTs were designed with inductive emitter degeneration structure. According to the simulation results, the HBT low-noise amplifier is unconditionally stable when the power supply voltage is 5 V and the noise figure(NF) is about 2.2 dB with small signal gain 13.3 dB, and 7.2 dB with insertion loss about 7.2 dB for LNA enabled and LNA bypass status, respectively. The input third order intercept point is about 10.2 dBm with two-tone signal at 2.412 and 2.437 GHz, respectively. Total input power is 0 dBm(-3 dBm/tone).