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This article presents an exact mid-band gain-expression for the CMOS operational-transconductance-amplifier (OTA) with low-voltage-cascode-current-mirror (LVCCM) load. Its small-signal analysis is not available in any CMOS text-book or other published sources/articles. A simplified and innovative technique is employed in performing this analysis with an in depth tutorial flavor. It shows that the derived mid-band gain of the CMOS OTA with LVCCM load is significantly more accurate than that obtained using the highly approximate classical gain-expression of the OTA employing a standard cascode-current-mirror equivalence which may be used in textbooks and other articles. Circuit simulations employing the 180-nm and 65-nm TSMC CMOS process technologies has been performed to indicate the progressively higher accuracy of the derived exact gain-expression for the LVCCM loaded OTA with technology scaling. This new analysis indicates an additional degree of freedom in tuning the gain of the OTA with LVCCM load using an additional transconductance parameter, gm5,6 of (M5, M6). A simplified expression is also deduced which provides an improvement over the classical approximate expression, due to the additional design insight and accuracy provided by this additional parameter while still being amenable to first order gain evaluation in a simplified way. The presented analysis is new and has not been reported before in open literature in any form. [ABSTRACT FROM AUTHOR]

This paper presents a low-power CMOS temperature and process compensated 150.9 MHz Very-high-frequency (VHF) voltage-controlled-ring-oscillator (VCRO) for on-chip integration. The design employs a CMOS temperature-sensor and novel feedback control circuitry to generate the internal control-voltage for the VCRO which ensures oscillation in the vicinity of the desired frequency despite variations in temperature. The control circuitry is the implementation of an empirical equation expressing a temperature sensor-voltage into a specific control-voltage for three different process corners using three different switches. The control-voltage calibrates against temperature variation for the specific process-corner in order to maintain the same frequency of oscillation. Simulations shows that the proposed design maintains the oscillator’s frequency within 0.39% from −10°C to 90°C. The fabricated chip implemented in 130-nm GF 8HP Si-Ge BiCMOS process, occupies an area of 0.0242-mm2 and consumes 325 $\mu \text{W}$ while operating with a 1 V supply-voltage. The performance was verified through experimental immersion of DUT (device-under-test) in a temperature-controlled water-bath in the range 22.5°C–70°C.

An improved class AB version of the super source follower is used to implement a compact and power-efficient second order analog low-pass filter. The proposed circuit achieves a 41% power reduction as well as an improvement in linearity and pass band gain with respect to its class A counterpart. Measurement results of a test chip prototype fabricated in a 180 nm CMOS technology show a power consumption ranging from 50.3 $\mu \text{W}$ to 85.27 $\mu \text{W}$ for cutoff frequencies from 600 kHz to 890 kHz, with a supply voltage of ±0.75 V. A third order intermodulation distortion of −35.34 dB (for an input signal of 0.4 mVpp and 350 kHz) and a THD of −69.7 dB (for an input signal of 0.4 mVpp and 100 kHz) are measured, which results in an improvement with respect to the conventional class A version of 13.98 dB and 43.6 dB, respectively. The silicon area is 0.0592 mm2 (using external capacitors). [ABSTRACT FROM AUTHOR]

This paper presents the small-signal operation of a $g_{\mathrm {m}}$ -boosted inverter-cascode transimpedance amplifier which has not been reported previously and whose comprehensive analysis is not available in any reported article or text-book. A simplified sequential equivalent-circuit method is employed which eliminates the need for complicated circuit analysis techniques. The analysis shows that the gain and the gain-bandwidth of the $g_{\mathrm {m}}$ -boosted inverter-cascode transimpedance-amplifier is enhanced by the gain of the $g_{\mathrm {m}}$ -boosting amplifier. This is due to the increased output impedance of the TIA, and, the reduced input-referred miller-effect capacitance through miller-effect trade-off employing the $g_{\mathrm {m}}$ -boosting loop. To verify the actual performance improvement achieved, circuit simulation results as well as measured experimental results are also provided.

Summary: This paper presents an elegant technique for the mid‐band analysis of a "nonideal" drain‐loaded source‐follower. The analysis of the drain‐loaded source‐follower is then applied to the superposition‐based mismatch differential‐gain analysis of a differential amplifier. This novel technique provides a more comprehensive mismatch gain analysis of the differential amplifier compared to that available in text books and other published sources. The presented analysis of a "nonideal" drain‐loaded source‐follower has not been reported before in open literature in any form. This new method renders the need for the well‐known and commonly employed "voltage‐divider" form of the source‐follower analysis unnecessary. A more accurate differential‐amplifier mismatch gain expression is attained using a much simpler source‐follower mid‐band analysis technique. [ABSTRACT FROM AUTHOR]

This paper presents a new highly-simplified and elegant technique for the mid-band analysis of the source-follower which is extended for the analysis of gm-boosted source-follower and a non-ideal drain-loaded source-follower. The accurate analysis of the drain-loaded source-follower is then applied to the superposition-based accurate differential-gain analysis of a mismatched non-ideal differential-amplifier. This new generalized methodology provides a more comprehensive mismatch gain analysis of the non-ideal differential amplifier compared to that presently available in text-books and other published sources. The drain loaded source-follower was not presented before in any form, and, the new source-follower analysis and the analysis of the drain-loaded source-follower has not been reported before. The presented methodology renders unnecessary the need for the commonly employed "voltage-divider" form of the source-follower analysis and the associated circuit transformations/derivations to employ the voltage-divider form. A more accurate non-ideal differential-amplifier mismatch gain expression is attained by including an elegant drain-loaded source-follower analysis. Simulation results for the derivations are also provided. Comparison of Cadence AC simulation results for the mismatched differential amplifier (with various loads), with the previous and the newly presented analytical mismatch differential gain expressions confirm the superiority of the presented new generalized method. [ABSTRACT FROM AUTHOR]

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a squarer/divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130-nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system. [ABSTRACT FROM AUTHOR]

This brief paper investigates the small-signal mid-band behavior of g -boosted follower-amplifiers which has not been explored previously and whose analysis is not available in text-books or any other source. Both g -boosted source follower and g -boosted emitter follower are considered in the mid-band analysis. A novel circuit/source transformation based 'pictorial' technique with progressively simplified circuit diagrams is employed for this mid-band analysis which generally eliminates the need for solving nodal or mesh equations. Final expression is often achieved by inspection of the simplified circuit without the need for circuit analysis. The paper also discusses g -boosted BiCMOS follower amplifier using substrate PNP device in a pure CMOS process. The analysis demonstrates that the unity gain accuracy of follower-amplifier can be considerably enhanced using the g -boosting technique without sacrificing bandwidth. [ABSTRACT FROM AUTHOR]

This paper is devoted to fault diagnosis of nonlinear analog CMOS circuits designed in nanometer technology. A method that allows diagnosing a single soft short and local parameter variations, occurring simultaneously, is developed. The method exploits DC measurements at limited number of points in the test phase. The diagnostic test leads to a system of nonlinear algebraic equations, not given in explicit analytical form, that may have multiple solutions. The solutions determine the sets comprising one soft short value and several values of the preliminary selected parameters. To find them an extended simplicial algorithm is developed. It allows tracing different space curves, leading to different solutions. Moreover, a procedure for selecting the actual solution from among the obtained ones is proposed. For illustration a representative numerical example is discussed in detail. [ABSTRACT FROM AUTHOR]

This article demonstrates simplified mid-band derivations for CMOS cascode and g -boosted cascode. While the cascode mid-band analysis is addressed in some textbooks through varying brief treatments, it is provided in this paper in a more in-depth and consolidated form using an easy approach. The detailed analysis of g -boosted cascode stage is mostly not available in textbooks (or any Web source) despite being an important analog building block in achieving gain enhancements. The mid-band analysis of this stage is made easy in this paper using a simple short circuit and inspection technique. There is no need to write or solve lengthy equations. Transformation of dependent current sources through ' opportunistic short circuits' is utilized often in achieving this ease in derivation. An interesting new concept of ' Algebraic ground' or ' Meta- ground' is introduced in relation to the g -boosted cascode. Some novel compound cascode stages with simplified approach to their mid-band derivations is also provided. Additional insight is also provided through a comparison of the cascode with the g -boosted cascode using the simplified models and derivations which is rarely available elsewhere. [ABSTRACT FROM AUTHOR]

This article simplifies several small-signal CMOS circuit analysis techniques from their existing forms in textbook approaches. Several CMOS loads and circuit topologies are analyzed through a simplified “incremental perturbation” approach, and solutions can sometimes be found almost by “common-sense” inspection with some use of Norton’s and Thevenin’s transformations. In many cases there is no need to write and solve multiple equations, but just the utilization of “incremental KVL or incremental KCL.” Elimination, reduction, merger or conversion of dependent current sources through “opportunistic short circuits” is a central idea behind this methodology. [ABSTRACT FROM AUTHOR]

A novel Gm-C filter design technique is presented. It is based on floating-gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential Gm-C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all-pole Gm-C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low-power second-order Butterworth Gm-C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5-µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A technique to improve the input and output range of CMOS transconductors with resistive current division for continuous tuning is presented. Using it, a tunable transconductor is proposed which features high linearity over a wide input range and simplicity. Measurement results of the transconductor, fabricated in a 0.5 μm CMOS process, show an IM3 of -66 dB for a ±1.65V supply and two input tones centered at 1MHz of 1 Vpp each, and only 0.7 mW of power consumption. This represents an improvement of 13 dB versus the same transconductor using conventional current division. [ABSTRACT FROM AUTHOR]

In this paper an analog voltage-mode median filter, which operates on a 3 × 3 kernel is presented. The filter is implemented in a 0.35 μm CMOS technology. The proposed solution is based on voltage comparators and a bubble sort configuration. As a result, a fast (34 ns) time response with low power consumption (1.25 mW for 3.3 V) is achieved. The key advantage of the configuration is relatively high accuracy of signal processing, which allows the calculation of the median of signals with the difference in amplitude as small as 10 mV. This feature allows the application of the filter to vision systems with up to 7 bit equivalent resolution. The analytical and statistical analysis of the filter resolution, and analysis of its speed limitations are presented and compared to measurement results. Based on the achieved results, a set of guidelines for the filter design and optimisation is presented. [ABSTRACT FROM AUTHOR]

A Gm-C third-order Chebyshev low-pass filter with a novel switched capacitor frequency tuning technique for a zero-IF Bluetooth receiver has been designed. The frequency tuning scheme is simpler and has more relaxed specifications than conventional ones. Furthermore, a highly linear pseudo-differential transconductor with a compact feedback loop able to operate with low supply voltage has been used. This control loop holds the input transistors in triode region and provides high output resistance, keeping high linearity in a wide range of transconductance. The filter bandwidth is 0.5 MHz and the overall scheme consumes 1.1 mA from a 1.8-V supply. The measured third-order intermodulation (IM3) distortion of the filter for a 1 Vpp two-tone signal centered at 300 kHz is -65 dB. [ABSTRACT FROM AUTHOR]

SUMMARY A class AB version of the conventional super source follower (SSF) is described. The circuit greatly increases slew rate (SR) and current efficiency, maintaining the low distortion and low output resistance of the SSF. Class AB operation is achieved without extra power dissipation or supply requirements, and without bandwidth or noise degradation. The circuit can advantageously replace the SSF in a wide variety of analog systems, opening a new research line in analog design. To illustrate the widespread application of this cell, a class AB differential unity-gain buffer, a class AB differential current mirror and two class AB differential transconductors are designed, fabricated in a 0.5µm CMOS technology and tested. Measurement results using a dual supply of ±1.65V show that the proposed class AB version of the SSF improves SR by a factor 21.5 and increases bandwidth by 10%, keeping noise level, input range, power consumption, and supply requirements unaltered. The fabricated class AB current mirror features a THD at 100 kHz of − 62dB for signal currents 20 times larger than the bias current. The fabricated transconductors feature an IM3 at 1 MHz of − 56.6dB for output currents more than 13 times larger than the bias currents. Copyright © 2011 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

CMOS current-mode analog multiplier/divider circuit is presented. It is suited to standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5 μm CMOS test chip prototype verify the approach employed. The circuit consumes 120 μW using a single supply voltage of 1.5 V and requires a silicon area of 150 × 140 μm. [ABSTRACT FROM AUTHOR]

Different design procedures to operate MOS translinear loops at low supply voltage are presented. They utilize innovative biasing strategies based on flipped voltage followers and floating batteries. An alternate topology based on coupled negative feedback loops is also introduced. Simulation and measurement results for various test chip prototypes validate the proposed techniques and allow comparison among them. [ABSTRACT FROM AUTHOR]

A family of tunable MOS resistors based on quasi-floating-gate (QFG) transistors biased in the triode region is analyzed in this paper. From the study results, a new device that outperforms previous implementations, is presented. By means of a capacitive divider, the ac component of the drain-to-source voltage scaled with a factor α ⩽ 1 is added to the gate-to-source voltage leading to a cancellation of the nonlinear terms. The effect of α on resistor linearity is analytically studied. Simulation results are also provided for different technologies. Finally, a complete transconductor has been built which preserves the linearity of the MOS resistor. Three versions of the transconductor have been fabricated for different values of α (α = 0,0.5, and 1) in a 0.5 μm CMOS technology with ±1.65-V supply voltage. Experimental results show (for α = 1) a THD of -57 dB (HD2 = -70 dB) at 1 MHz for 2-V peak-to-peak differential input signal with a nominal ac-transconductance of 200 μA/V and a power consumption of 3.2 mW. [ABSTRACT FROM AUTHOR]

A novel linear tunable transconductor based, on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-μm CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-Vpp input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption. [ABSTRACT FROM AUTHOR]

A technique to achieve highly linear scaling of differential currents in CMOS technology is presented. It is based on operation in weak or moderate inversion, and features performance improvements over previous proposals aimed to the same goal, like reduced supply voltage requirements, increased power efficiency, and avoidance of bulk effect. As an example, this technique is applied to attain continuous tuning for two novel voltage-to current converters, achieving highly linear programmable transconductance over a rail to-rail input range. Both implementations fabricated in a O.5-ඵtm CMOS technology using a dual supply of ±1.5 V achieve a THD of -60 dB with differential input swings of 6 Vpp (i.e., twice the supply voltage). The area and power consumption are 0.12 mm2 and 2.6 mW for the first implementation and 0.11 mm2 and 2.2 mW for the second one, respectively. [ABSTRACT FROM AUTHOR]

A supplementary linearization technique for CMOS differential pairs with resistive source degeneration is proposed. The approach exploits an auxiliary (degenerated) differential pair to drive the bulk terminals of the main pair. Transistor-level simulations on a design using a 0.25-μm process and powered with 2.5 V and 1 mA, show that total harmonic distortion (THD) in the voltage-to-current conversion is decreased by 10 dB (for an input differential signal with a peak amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the traditional source-degenerated transconductor. This THO improvement is achieved with a negligible increase in power consumption. [ABSTRACT FROM AUTHOR]

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-μm CMOS process. Experimental results show a greatly improved slew rate by factors 30–60 and gain-bandwidth product by factors 11.5–17 when compared to a classical Class-A OTA. The circuits are operated at ±1-V supply voltage with only 10 μA of bias current. [ABSTRACT FROM AUTHOR]

An integrator employing the log-domain principle and fabricated in a 0.8-μm CMOS process is presented. It uses floating-gate MOS transistors biased in weak inversion to achieve low-voltage operation and low power consumption. The circuit does not suffer from initial charge trapped in the floating gates, thus not requiring postfabrication charge removal. It can be frequency tuned over more than three decades, from 25 Hz to 35 kHz, and uses a 1.2-V single supply to achieve a dynamic range at 1% THD of 75 dB thanks to its balanced class-AB operation. For cutoff frequencies in the range of 100 Hz, the supply voltage can be reduced down to 1 V. The circuit occupies an active area of 0.1 mm² and dissipates 4.7 μW. The technique employed can be readily extended to high-order filters. [ABSTRACT FROM AUTHOR]

A new low-voltage CMOS winner-take-all (WTA) circuit is presented. The proposed circuit exhibits a linear increase of complexity with the number of inputs at the rate of only three transistors per input and it is based on a modified version of the common source scheme. In this case, each input follower is enhanced by local shunt feedback to increase its gain and to reduce its output impedance. Simulations demonstrate the potential of the circuit to operate at very high speed, with high precision and with a supply voltage close to a transistor's threshold voltage. Experimental verification of the circuit using a 0.5-pm CMOS technology is also provided. [ABSTRACT FROM AUTHOR]

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-μm implementation achieves a SFDR of 68 dB and a THD of -66.5 dB using a dual supply of ±1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion. [ABSTRACT FROM AUTHOR]

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-μm CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-μA quiescent currents and ±1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal. [ABSTRACT FROM AUTHOR]

Two schemes for power-efficient gain-programmable V-I conversion based on class AB CMOS mirrors are introduced. The proposed topologies also allow for high-speed gain-programmable precision rectification. Experimental results from a test chip prototype in 0.5-μ m CMOS technology with ±1 V supplies are shown that validate the proposed circuits. [ABSTRACT FROM AUTHOR]

A compact, four-quadrant analog CMOS multiplier featuring wide dynamic range is presented. The capacitive voltage division obtained by the use of Floating-Gate MOS (FGMOS) transistors, and an accurate wide-swing current mirror based on active bootstrapping, allow a wide input range, low harmonic distortion, and high linearity. Simulation and measurement results for a 0.8 μm CMOS prototype demonstrate the validity of the proposed approach. [ABSTRACT FROM AUTHOR]

A novel first-order CMOS log-domain filter is presented. The internal voltage swing compression due to its instantaneous voltage companding nature, together with the use of Floating-Gate MOS transistors and its class AB differential topology, allows operation with a single 1 V supply while maintaining at the same time a large input range. Moreover, operation in weak inversion leads to very low power consumption. The filter can be tuned in more than one decade through its bias currents. Simulation and measurement results of an experimental prototype fabricated in a 0.8 μm CMOS technology demonstrate on silicon the feasibility of the proposed technique, which can be readily extended to higher-order filters. [ABSTRACT FROM AUTHOR]

The LINC transmitter is an architecture that provides linear amplification using nonlinear but power efficient amplifiers. One crucial signal processing function of LINC is the signal component separator (SCS) which forms two constant-amplitude phase-modulated signals from the source signal. This paper presents an analog SCS chip implemented in a 0.35 μm CMOS process using a novel design based on the so-called voltage-translinear circuit principle. An experimental LINC transmitter was built with the SCS chip, nonlinear amplifiers and a power combiner. Test results showed that all output spurious levels some -55 dBc and -48 dBc could be obtained with a North American Digital Cellular (NADC) signal and an IS-95 signal, respectively. This implies a high degree of linearity. [ABSTRACT FROM AUTHOR]

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are provided in order to verify their correct operation. [ABSTRACT FROM AUTHOR]

The power feedback technique is a simple and low cost linearization scheme suitable for consumer products such as hand sets. This paper presents a custom chip for linearization of RF power amplifiers using power feedback. The chip, implemented in a standard double-metal double-poly 0.6 μm CMOS process, operates with 3.3 V supply voltage and consumes 62 mW. When it was used to linearize a commercially available high efficiency RF power amplifier at 850 MHz, experimental results showed that out-of-band power at 30 kHz offset was reduced some 10 dB for a π/4-shifted DQPSK modulated North American digital cellular (NADC) signal. For the same level of adjacent channel interference (ACI), the efficiency was increased from 35% to 48%. [ABSTRACT FROM AUTHOR]

A 2.4-GHz CMOS VCO is presented employing pMOS transistors as voltage-controlled capacitances and on-chip hollow spiral inductors. The design was implemented in a standard digital 0.8μm CMOS process and exhibits a 15% tuning range at 2.5 V supply voltage and 9 mA supply current. Phase-noise measurements show a phase-noise of about −118 dBc/Hz at 1 MHz from the carrier. [ABSTRACT FROM AUTHOR]

A technique to achieve highly linear current scaling in CMOS technologies is proposed. It is based on two balanced electronically programmable current mirrors operating in moderate inversion. The scaling factor can be continuously adjusted in a wide range. This technique can be employed to achieve or to extend gain adjustment in amplifiers. As an application example, a variable-gain differential current amplifier and a tunable transconductor are presented. Measurement results of the transconductor implemented in a 0.5-μm CMOS technology validate in silicon the proposed approach. [ABSTRACT FROM AUTHOR]

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-µm CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-µA peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm² of silicon area and features 0.96 mW of static power consumption. [ABSTRACT FROM AUTHOR]